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dt-bindings: arm: Convert ARM CCI-400 binding to a schema
The ARM CCI-400 Interconnect is supported by Linux thanks to its device
tree binding.
Now that we have the DT validation in place, let's convert the device
tree bindings for that driver over to a YAML schema.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210901091852.479202-7-maxime@cerno.tech
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Maxime Ripard
and committed by
Rob Herring
ddf6cc9a
bf99826f
+256
-224
+216
Documentation/devicetree/bindings/arm/arm,cci-400.yaml
+216
Documentation/devicetree/bindings/arm/arm,cci-400.yaml
···
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM CCI Cache Coherent Interconnect Device Tree Binding
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+
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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description: >
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ARM multi-cluster systems maintain intra-cluster coherency through a cache
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coherent interconnect (CCI) that is capable of monitoring bus transactions
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and manage coherency, TLB invalidations and memory barriers.
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+
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It allows snooping and distributed virtual memory message broadcast across
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clusters, through memory mapped interface, with a global control register
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space and multiple sets of interface control registers, one per slave
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interface.
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+
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properties:
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$nodename:
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pattern: "^cci(@[0-9a-f]+)?$"
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+
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compatible:
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enum:
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- arm,cci-400
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- arm,cci-500
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- arm,cci-550
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+
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reg:
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maxItems: 1
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description: >
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Specifies base physical address of CCI control registers common to all
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interfaces.
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+
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"#address-cells": true
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"#size-cells": true
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ranges: true
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+
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patternProperties:
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"^slave-if@[0-9a-f]+$":
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type: object
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+
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properties:
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compatible:
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const: arm,cci-400-ctrl-if
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+
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interface-type:
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enum:
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- ace
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- ace-lite
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+
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reg:
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maxItems: 1
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+
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required:
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- compatible
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- interface-type
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- reg
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+
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additionalProperties: false
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+
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"^pmu@[0-9a-f]+$":
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type: object
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+
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properties:
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compatible:
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oneOf:
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- const: arm,cci-400-pmu,r0
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- const: arm,cci-400-pmu,r1
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- const: arm,cci-400-pmu
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deprecated: true
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description: >
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Permitted only where OS has secure access to CCI registers
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- const: arm,cci-500-pmu,r0
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- const: arm,cci-550-pmu,r0
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+
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interrupts:
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minItems: 1
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maxItems: 8
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description: >
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List of counter overflow interrupts, one per counter. The interrupts
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must be specified starting with the cycle counter overflow interrupt,
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followed by counter0 overflow interrupt, counter1 overflow
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interrupt,... ,counterN overflow interrupt.
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+
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The CCI PMU has an interrupt signal for each counter. The number of
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interrupts must be equal to the number of counters.
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+
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reg:
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maxItems: 1
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+
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required:
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- compatible
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- interrupts
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- reg
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+
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additionalProperties: false
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+
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required:
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- "#address-cells"
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- "#size-cells"
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- compatible
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- ranges
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- reg
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+
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additionalProperties: false
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+
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examples:
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- |
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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+
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compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
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model = "V2P-CA15_CA7";
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arm,hbi = <0x249>;
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interrupt-parent = <&gic>;
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+
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/*
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* This CCI node corresponds to a CCI component whose control
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* registers sits at address 0x000000002c090000.
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*
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* CCI slave interface @0x000000002c091000 is connected to dma
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* controller dma0.
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*
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* CCI slave interface @0x000000002c094000 is connected to CPUs
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* {CPU0, CPU1};
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*
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* CCI slave interface @0x000000002c095000 is connected to CPUs
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* {CPU2, CPU3};
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*/
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+
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cpus {
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#size-cells = <0>;
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+
#address-cells = <1>;
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+
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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cci-control-port = <&cci_control1>;
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+
reg = <0x0>;
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+
};
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+
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CPU1: cpu@1 {
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+
device_type = "cpu";
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compatible = "arm,cortex-a15";
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cci-control-port = <&cci_control1>;
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reg = <0x1>;
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};
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+
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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cci-control-port = <&cci_control2>;
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+
reg = <0x100>;
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};
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+
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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cci-control-port = <&cci_control2>;
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+
reg = <0x101>;
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+
};
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};
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+
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dma0: dma@3000000 {
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/* compatible = "arm,pl330", "arm,primecell"; */
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cci-control-port = <&cci_control0>;
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reg = <0x0 0x3000000 0x0 0x1000>;
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+
interrupts = <10>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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+
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cci@2c090000 {
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compatible = "arm,cci-400";
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+
#address-cells = <1>;
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+
#size-cells = <1>;
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reg = <0x0 0x2c090000 0 0x1000>;
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+
ranges = <0x0 0x0 0x2c090000 0x10000>;
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+
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cci_control0: slave-if@1000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace-lite";
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reg = <0x1000 0x1000>;
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};
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+
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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+
};
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+
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cci_control2: slave-if@5000 {
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+
compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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+
};
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+
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pmu@9000 {
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compatible = "arm,cci-400-pmu";
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reg = <0x9000 0x5000>;
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+
interrupts = <0 101 4>,
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<0 102 4>,
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<0 103 4>,
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<0 104 4>,
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<0 105 4>;
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};
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};
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};
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+
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...
+38
Documentation/devicetree/bindings/arm/cci-control-port.yaml
+38
Documentation/devicetree/bindings/arm/cci-control-port.yaml
···
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CCI Interconnect Bus Masters binding
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+
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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+
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description: |
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Masters in the device tree connected to a CCI port (inclusive of CPUs
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and their cpu nodes).
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select: true
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+
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properties:
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cci-control-port:
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$ref: /schemas/types.yaml#/definitions/phandle
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+
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additionalProperties: true
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+
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examples:
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- |
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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+
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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cci-control-port = <&cci_control1>;
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reg = <0>;
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};
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};
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+
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...
-224
Documentation/devicetree/bindings/arm/cci.txt
-224
Documentation/devicetree/bindings/arm/cci.txt
···
1
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=======================================================
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ARM CCI cache coherent interconnect binding description
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=======================================================
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-
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ARM multi-cluster systems maintain intra-cluster coherency through a
6
-
cache coherent interconnect (CCI) that is capable of monitoring bus
7
-
transactions and manage coherency, TLB invalidations and memory barriers.
8
-
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It allows snooping and distributed virtual memory message broadcast across
10
-
clusters, through memory mapped interface, with a global control register
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-
space and multiple sets of interface control registers, one per slave
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-
interface.
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-
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* CCI interconnect node
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-
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Description: Describes a CCI cache coherent Interconnect component
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-
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Node name must be "cci".
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Node's parent must be the root node /, and the address space visible
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through the CCI interconnect is the same as the one seen from the
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root node (ie from CPUs perspective as per DT standard).
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Every CCI node has to define the following properties:
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-
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- compatible
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Usage: required
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Value type: <string>
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Definition: must contain one of the following:
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"arm,cci-400"
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"arm,cci-500"
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"arm,cci-550"
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-
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- reg
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Usage: required
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Value type: Integer cells. A register entry, expressed as a pair
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of cells, containing base and size.
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Definition: A standard property. Specifies base physical
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address of CCI control registers common to all
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interfaces.
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-
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- ranges:
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Usage: required
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Value type: Integer cells. An array of range entries, expressed
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as a tuple of cells, containing child address,
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parent address and the size of the region in the
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child address space.
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Definition: A standard property. Follow rules in the Devicetree
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Specification for hierarchical bus addressing. CCI
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interfaces addresses refer to the parent node
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addressing scheme to declare their register bases.
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-
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CCI interconnect node can define the following child nodes:
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-
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- CCI control interface nodes
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-
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Node name must be "slave-if".
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Parent node must be CCI interconnect node.
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-
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A CCI control interface node must contain the following
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properties:
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-
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be set to
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"arm,cci-400-ctrl-if"
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-
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- interface-type:
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Usage: required
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Value type: <string>
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Definition: must be set to one of {"ace", "ace-lite"}
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depending on the interface type the node
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represents.
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-
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- reg:
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Usage: required
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Value type: Integer cells. A register entry, expressed
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as a pair of cells, containing base and
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size.
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Definition: the base address and size of the
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corresponding interface programming
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registers.
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-
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- CCI PMU node
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-
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Parent node must be CCI interconnect node.
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-
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A CCI pmu node must contain the following properties:
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-
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must contain one of:
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"arm,cci-400-pmu,r0"
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"arm,cci-400-pmu,r1"
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"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
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secure access to CCI registers
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"arm,cci-500-pmu,r0"
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"arm,cci-550-pmu,r0"
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- reg:
100
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Usage: required
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Value type: Integer cells. A register entry, expressed
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as a pair of cells, containing base and
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size.
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Definition: the base address and size of the
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corresponding interface programming
106
-
registers.
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-
108
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- interrupts:
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Usage: required
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Value type: Integer cells. Array of interrupt specifier
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entries, as defined in
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../interrupt-controller/interrupts.txt.
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Definition: list of counter overflow interrupts, one per
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counter. The interrupts must be specified
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starting with the cycle counter overflow
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interrupt, followed by counter0 overflow
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-
interrupt, counter1 overflow interrupt,...
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-
,counterN overflow interrupt.
119
-
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The CCI PMU has an interrupt signal for each
121
-
counter. The number of interrupts must be
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-
equal to the number of counters.
123
-
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-
* CCI interconnect bus masters
125
-
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Description: masters in the device tree connected to a CCI port
127
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(inclusive of CPUs and their cpu nodes).
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-
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A CCI interconnect bus master node must contain the following
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-
properties:
131
-
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- cci-control-port:
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Usage: required
134
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Value type: <phandle>
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Definition: a phandle containing the CCI control interface node
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the master is connected to.
137
-
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Example:
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-
140
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cpus {
141
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#size-cells = <0>;
142
-
#address-cells = <1>;
143
-
144
-
CPU0: cpu@0 {
145
-
device_type = "cpu";
146
-
compatible = "arm,cortex-a15";
147
-
cci-control-port = <&cci_control1>;
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-
reg = <0x0>;
149
-
};
150
-
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-
CPU1: cpu@1 {
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-
device_type = "cpu";
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-
compatible = "arm,cortex-a15";
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-
cci-control-port = <&cci_control1>;
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-
reg = <0x1>;
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-
};
157
-
158
-
CPU2: cpu@100 {
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-
device_type = "cpu";
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-
compatible = "arm,cortex-a7";
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-
cci-control-port = <&cci_control2>;
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-
reg = <0x100>;
163
-
};
164
-
165
-
CPU3: cpu@101 {
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-
device_type = "cpu";
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-
compatible = "arm,cortex-a7";
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-
cci-control-port = <&cci_control2>;
169
-
reg = <0x101>;
170
-
};
171
-
172
-
};
173
-
174
-
dma0: dma@3000000 {
175
-
compatible = "arm,pl330", "arm,primecell";
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-
cci-control-port = <&cci_control0>;
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-
reg = <0x0 0x3000000 0x0 0x1000>;
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interrupts = <10>;
179
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#dma-cells = <1>;
180
-
#dma-channels = <8>;
181
-
#dma-requests = <32>;
182
-
};
183
-
184
-
cci@2c090000 {
185
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compatible = "arm,cci-400";
186
-
#address-cells = <1>;
187
-
#size-cells = <1>;
188
-
reg = <0x0 0x2c090000 0 0x1000>;
189
-
ranges = <0x0 0x0 0x2c090000 0x10000>;
190
-
191
-
cci_control0: slave-if@1000 {
192
-
compatible = "arm,cci-400-ctrl-if";
193
-
interface-type = "ace-lite";
194
-
reg = <0x1000 0x1000>;
195
-
};
196
-
197
-
cci_control1: slave-if@4000 {
198
-
compatible = "arm,cci-400-ctrl-if";
199
-
interface-type = "ace";
200
-
reg = <0x4000 0x1000>;
201
-
};
202
-
203
-
cci_control2: slave-if@5000 {
204
-
compatible = "arm,cci-400-ctrl-if";
205
-
interface-type = "ace";
206
-
reg = <0x5000 0x1000>;
207
-
};
208
-
209
-
pmu@9000 {
210
-
compatible = "arm,cci-400-pmu";
211
-
reg = <0x9000 0x5000>;
212
-
interrupts = <0 101 4>,
213
-
<0 102 4>,
214
-
<0 103 4>,
215
-
<0 104 4>,
216
-
<0 105 4>;
217
-
};
218
-
};
219
-
220
-
This CCI node corresponds to a CCI component whose control registers sits
221
-
at address 0x000000002c090000.
222
-
CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
223
-
CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
224
-
CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};