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Merge tag 'mvebu-irqchip-3.14' of git://git.infradead.org/linux-mvebu into irq/core
mvebu irqchip changes for v3.14
- add Dove PMU interrupt controller
Duh. I completely forgot about that one...
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+144
+17
Documentation/devicetree/bindings/interrupt-controller/marvell,dove-pmu-intc.txt
+17
Documentation/devicetree/bindings/interrupt-controller/marvell,dove-pmu-intc.txt
···
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Marvell Dove Power Management Unit interrupt controller
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Required properties:
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- compatible: shall be "marvell,dove-pmu-intc"
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- reg: base address of PMU interrupt registers starting with CAUSE register
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- interrupts: PMU interrupt of the main interrupt controller
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
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Example:
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pmu_intc: pmu-interrupt-ctrl@d0050 {
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compatible = "marvell,dove-pmu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xd0050 0x8>;
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interrupts = <33>;
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};
+1
drivers/irqchip/Makefile
+1
drivers/irqchip/Makefile
+126
drivers/irqchip/irq-dove.c
+126
drivers/irqchip/irq-dove.c
···
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/*
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* Marvell Dove SoCs PMU IRQ chip driver.
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*
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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#define DOVE_PMU_IRQ_CAUSE 0x00
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#define DOVE_PMU_IRQ_MASK 0x04
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static void dove_pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_domain *d = irq_get_handler_data(irq);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
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u32 stat = readl_relaxed(gc->reg_base + DOVE_PMU_IRQ_CAUSE) &
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gc->mask_cache;
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while (stat) {
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u32 hwirq = ffs(stat) - 1;
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generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq));
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stat &= ~(1 << hwirq);
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}
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}
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static void pmu_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = ~d->mask;
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/*
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* The PMU mask register is not RW0C: it is RW. This means that
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* the bits take whatever value is written to them; if you write
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* a '1', you will set the interrupt.
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*
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* Unfortunately this means there is NO race free way to clear
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* these interrupts.
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*
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* So, let's structure the code so that the window is as small as
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* possible.
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*/
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irq_gc_lock(gc);
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mask &= irq_reg_readl(gc->reg_base + ct->regs.ack);
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irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
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irq_gc_unlock(gc);
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}
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static int __init dove_pmu_irq_init(struct device_node *np,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct resource r;
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struct irq_domain *domain;
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struct irq_chip_generic *gc;
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int ret, irq, nrirqs = 7;
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domain = irq_domain_add_linear(np, nrirqs,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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pr_err("%s: unable to add irq domain\n", np->name);
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return -ENOMEM;
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}
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ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
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handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%s: unable to alloc irq domain gc\n", np->name);
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return ret;
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}
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ret = of_address_to_resource(np, 0, &r);
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if (ret) {
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pr_err("%s: unable to get resource\n", np->name);
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return ret;
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}
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if (!request_mem_region(r.start, resource_size(&r), np->name)) {
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pr_err("%s: unable to request mem region\n", np->name);
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return -ENOMEM;
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}
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/* Map the parent interrupt for the chained handler */
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("%s: unable to parse irq\n", np->name);
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return -EINVAL;
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}
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->reg_base = ioremap(r.start, resource_size(&r));
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if (!gc->reg_base) {
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pr_err("%s: unable to map resource\n", np->name);
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return -ENOMEM;
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}
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gc->chip_types[0].regs.ack = DOVE_PMU_IRQ_CAUSE;
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gc->chip_types[0].regs.mask = DOVE_PMU_IRQ_MASK;
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gc->chip_types[0].chip.irq_ack = pmu_irq_ack;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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/* mask and clear all interrupts */
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writel(0, gc->reg_base + DOVE_PMU_IRQ_MASK);
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writel(0, gc->reg_base + DOVE_PMU_IRQ_CAUSE);
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irq_set_handler_data(irq, domain);
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irq_set_chained_handler(irq, dove_pmu_irq_handler);
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return 0;
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}
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IRQCHIP_DECLARE(dove_pmu_intc,
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"marvell,dove-pmu-intc", dove_pmu_irq_init);