Merge tag 'dma-mapping-5.2' of git://git.infradead.org/users/hch/dma-mapping

+6 -7

Documentation/DMA-API-HOWTO.txt

··· 365 365 driver needs regions sized smaller than a page, you may prefer using 366 366 the dma_pool interface, described below. 367 367 368 - The consistent DMA mapping interfaces, for non-NULL dev, will by 369 - default return a DMA address which is 32-bit addressable. Even if the 370 - device indicates (via DMA mask) that it may address the upper 32-bits, 371 - consistent allocation will only return > 32-bit addresses for DMA if 372 - the consistent DMA mask has been explicitly changed via 373 - dma_set_coherent_mask(). This is true of the dma_pool interface as 374 - well. 368 + The consistent DMA mapping interfaces, will by default return a DMA address 369 + which is 32-bit addressable. Even if the device indicates (via the DMA mask) 370 + that it may address the upper 32-bits, consistent allocation will only 371 + return > 32-bit addresses for DMA if the consistent DMA mask has been 372 + explicitly changed via dma_set_coherent_mask(). This is true of the 373 + dma_pool interface as well. 375 374 376 375 dma_alloc_coherent() returns two values: the virtual address which you 377 376 can use to access it from the CPU and dma_handle which you pass to the

+7 -1

arch/arm/kernel/dma-isa.c

··· 55 55 return chan < 4 ? count : (count << 1); 56 56 } 57 57 58 + static struct device isa_dma_dev = { 59 + .init_name = "fallback device", 60 + .coherent_dma_mask = ~(dma_addr_t)0, 61 + .dma_mask = &isa_dma_dev.coherent_dma_mask, 62 + }; 63 + 58 64 static void isa_enable_dma(unsigned int chan, dma_t *dma) 59 65 { 60 66 if (dma->invalid) { ··· 95 89 dma->sg = &dma->buf; 96 90 dma->sgcount = 1; 97 91 dma->buf.length = dma->count; 98 - dma->buf.dma_address = dma_map_single(NULL, 92 + dma->buf.dma_address = dma_map_single(&isa_dma_dev, 99 93 dma->addr, dma->count, 100 94 direction); 101 95 }

+7 -1

arch/arm/mach-rpc/dma.c

··· 151 151 free_irq(idma->irq, idma); 152 152 } 153 153 154 + static struct device isa_dma_dev = { 155 + .init_name = "fallback device", 156 + .coherent_dma_mask = ~(dma_addr_t)0, 157 + .dma_mask = &isa_dma_dev.coherent_dma_mask, 158 + }; 159 + 154 160 static void iomd_enable_dma(unsigned int chan, dma_t *dma) 155 161 { 156 162 struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); ··· 174 168 idma->dma.sg = &idma->dma.buf; 175 169 idma->dma.sgcount = 1; 176 170 idma->dma.buf.length = idma->dma.count; 177 - idma->dma.buf.dma_address = dma_map_single(NULL, 171 + idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev, 178 172 idma->dma.addr, idma->dma.count, 179 173 idma->dma.dma_mode == DMA_MODE_READ ? 180 174 DMA_FROM_DEVICE : DMA_TO_DEVICE);

+1

arch/arm64/Kconfig

··· 13 13 select ARCH_HAS_DEVMEM_IS_ALLOWED 14 14 select ARCH_HAS_DMA_COHERENT_TO_PFN 15 15 select ARCH_HAS_DMA_MMAP_PGPROT 16 + select ARCH_HAS_DMA_PREP_COHERENT 16 17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 17 18 select ARCH_HAS_ELF_RANDOMIZE 18 19 select ARCH_HAS_FAST_MULTIPLIER

+1

arch/csky/Kconfig

··· 1 1 config CSKY 2 2 def_bool y 3 3 select ARCH_32BIT_OFF_T 4 + select ARCH_HAS_DMA_PREP_COHERENT 4 5 select ARCH_HAS_SYNC_DMA_FOR_CPU 5 6 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 6 7 select ARCH_USE_BUILTIN_BSWAP

-10

arch/x86/include/asm/dma-mapping.h

··· 13 13 #include <asm/swiotlb.h> 14 14 #include <linux/dma-contiguous.h> 15 15 16 - #ifdef CONFIG_ISA 17 - # define ISA_DMA_BIT_MASK DMA_BIT_MASK(24) 18 - #else 19 - # define ISA_DMA_BIT_MASK DMA_BIT_MASK(32) 20 - #endif 21 - 22 16 extern int iommu_merge; 23 - extern struct device x86_dma_fallback_dev; 24 17 extern int panic_on_overflow; 25 18 26 19 extern const struct dma_map_ops *dma_ops; ··· 22 29 { 23 30 return dma_ops; 24 31 } 25 - 26 - bool arch_dma_alloc_attrs(struct device **dev); 27 - #define arch_dma_alloc_attrs arch_dma_alloc_attrs 28 32 29 33 #endif

-6

arch/x86/kernel/amd_gart_64.c

··· 233 233 unsigned long bus; 234 234 phys_addr_t paddr = page_to_phys(page) + offset; 235 235 236 - if (!dev) 237 - dev = &x86_dma_fallback_dev; 238 - 239 236 if (!need_iommu(dev, paddr, size)) 240 237 return paddr; 241 238 ··· 388 391 389 392 if (nents == 0) 390 393 return 0; 391 - 392 - if (!dev) 393 - dev = &x86_dma_fallback_dev; 394 394 395 395 out = 0; 396 396 start = 0;

-20

arch/x86/kernel/pci-dma.c

··· 51 51 52 52 extern struct iommu_table_entry __iommu_table[], __iommu_table_end[]; 53 53 54 - /* Dummy device used for NULL arguments (normally ISA). */ 55 - struct device x86_dma_fallback_dev = { 56 - .init_name = "fallback device", 57 - .coherent_dma_mask = ISA_DMA_BIT_MASK, 58 - .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask, 59 - }; 60 - EXPORT_SYMBOL(x86_dma_fallback_dev); 61 - 62 54 void __init pci_iommu_alloc(void) 63 55 { 64 56 struct iommu_table_entry *p; ··· 68 76 } 69 77 } 70 78 } 71 - 72 - bool arch_dma_alloc_attrs(struct device **dev) 73 - { 74 - if (!*dev) 75 - *dev = &x86_dma_fallback_dev; 76 - 77 - if (!is_device_dma_capable(*dev)) 78 - return false; 79 - return true; 80 - 81 - } 82 - EXPORT_SYMBOL(arch_dma_alloc_attrs); 83 79 84 80 /* 85 81 * See <Documentation/x86/x86_64/boot-options.txt> for the iommu kernel

+10 -8

drivers/parport/parport_ip32.c

··· 568 568 569 569 /** 570 570 * parport_ip32_dma_start - begins a DMA transfer 571 + * @p: partport to work on 571 572 * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE 572 573 * @addr: pointer to data buffer 573 574 * @count: buffer size ··· 576 575 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 577 576 * correctly balanced. 578 577 */ 579 - static int parport_ip32_dma_start(enum dma_data_direction dir, 580 - void *addr, size_t count) 578 + static int parport_ip32_dma_start(struct parport *p, 579 + enum dma_data_direction dir, void *addr, size_t count) 581 580 { 582 581 unsigned int limit; 583 582 u64 ctrl; ··· 602 601 603 602 /* Prepare DMA pointers */ 604 603 parport_ip32_dma.dir = dir; 605 - parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir); 604 + parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir); 606 605 parport_ip32_dma.len = count; 607 606 parport_ip32_dma.next = parport_ip32_dma.buf; 608 607 parport_ip32_dma.left = parport_ip32_dma.len; ··· 626 625 627 626 /** 628 627 * parport_ip32_dma_stop - ends a running DMA transfer 628 + * @p: partport to work on 629 629 * 630 630 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 631 631 * correctly balanced. 632 632 */ 633 - static void parport_ip32_dma_stop(void) 633 + static void parport_ip32_dma_stop(struct parport *p) 634 634 { 635 635 u64 ctx_a; 636 636 u64 ctx_b; ··· 687 685 enable_irq(MACEISA_PAR_CTXB_IRQ); 688 686 parport_ip32_dma.irq_on = 1; 689 687 690 - dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len, 691 - parport_ip32_dma.dir); 688 + dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf, 689 + parport_ip32_dma.len, parport_ip32_dma.dir); 692 690 } 693 691 694 692 /** ··· 1447 1445 1448 1446 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1449 1447 1450 - parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len); 1448 + parport_ip32_dma_start(p, DMA_TO_DEVICE, (void *)buf, len); 1451 1449 reinit_completion(&priv->irq_complete); 1452 1450 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN); 1453 1451 ··· 1463 1461 if (ecr & ECR_SERVINTR) 1464 1462 break; /* DMA transfer just finished */ 1465 1463 } 1466 - parport_ip32_dma_stop(); 1464 + parport_ip32_dma_stop(p); 1467 1465 written = len - parport_ip32_dma_get_residue(); 1468 1466 1469 1467 priv->irq_mode = PARPORT_IP32_IRQ_FWD;

+7 -6

drivers/video/fbdev/da8xx-fb.c

··· 1097 1097 1098 1098 unregister_framebuffer(info); 1099 1099 fb_dealloc_cmap(&info->cmap); 1100 - dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, 1100 + dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base, 1101 1101 par->p_palette_base); 1102 - dma_free_coherent(NULL, par->vram_size, par->vram_virt, 1102 + dma_free_coherent(par->dev, par->vram_size, par->vram_virt, 1103 1103 par->vram_phys); 1104 1104 pm_runtime_put_sync(&dev->dev); 1105 1105 pm_runtime_disable(&dev->dev); ··· 1425 1425 par->vram_size = roundup(par->vram_size/8, ulcm); 1426 1426 par->vram_size = par->vram_size * LCD_NUM_BUFFERS; 1427 1427 1428 - par->vram_virt = dma_alloc_coherent(NULL, 1428 + par->vram_virt = dma_alloc_coherent(par->dev, 1429 1429 par->vram_size, 1430 1430 &par->vram_phys, 1431 1431 GFP_KERNEL | GFP_DMA); ··· 1446 1446 da8xx_fb_fix.line_length - 1; 1447 1447 1448 1448 /* allocate palette buffer */ 1449 - par->v_palette_base = dma_alloc_coherent(NULL, PALETTE_SIZE, 1449 + par->v_palette_base = dma_alloc_coherent(par->dev, PALETTE_SIZE, 1450 1450 &par->p_palette_base, 1451 1451 GFP_KERNEL | GFP_DMA); 1452 1452 if (!par->v_palette_base) { ··· 1532 1532 fb_dealloc_cmap(&da8xx_fb_info->cmap); 1533 1533 1534 1534 err_release_pl_mem: 1535 - dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, 1535 + dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base, 1536 1536 par->p_palette_base); 1537 1537 1538 1538 err_release_fb_mem: 1539 - dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); 1539 + dma_free_coherent(par->dev, par->vram_size, par->vram_virt, 1540 + par->vram_phys); 1540 1541 1541 1542 err_release_fb: 1542 1543 framebuffer_release(da8xx_fb_info);

+8 -16

drivers/video/fbdev/gbefb.c

··· 1162 1162 } 1163 1163 gbe_revision = gbe->ctrlstat & 15; 1164 1164 1165 - gbe_tiles.cpu = 1166 - dma_alloc_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), 1167 - &gbe_tiles.dma, GFP_KERNEL); 1165 + gbe_tiles.cpu = dmam_alloc_coherent(&p_dev->dev, 1166 + GBE_TLB_SIZE * sizeof(uint16_t), 1167 + &gbe_tiles.dma, GFP_KERNEL); 1168 1168 if (!gbe_tiles.cpu) { 1169 1169 printk(KERN_ERR "gbefb: couldn't allocate tiles table\n"); 1170 1170 ret = -ENOMEM; ··· 1178 1178 if (!gbe_mem) { 1179 1179 printk(KERN_ERR "gbefb: couldn't map framebuffer\n"); 1180 1180 ret = -ENOMEM; 1181 - goto out_tiles_free; 1181 + goto out_release_mem_region; 1182 1182 } 1183 1183 1184 1184 gbe_dma_addr = 0; 1185 1185 } else { 1186 1186 /* try to allocate memory with the classical allocator 1187 1187 * this has high chance to fail on low memory machines */ 1188 - gbe_mem = dma_alloc_wc(NULL, gbe_mem_size, &gbe_dma_addr, 1189 - GFP_KERNEL); 1188 + gbe_mem = dmam_alloc_attrs(&p_dev->dev, gbe_mem_size, 1189 + &gbe_dma_addr, GFP_KERNEL, 1190 + DMA_ATTR_WRITE_COMBINE); 1190 1191 if (!gbe_mem) { 1191 1192 printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n"); 1192 1193 ret = -ENOMEM; 1193 - goto out_tiles_free; 1194 + goto out_release_mem_region; 1194 1195 } 1195 1196 1196 1197 gbe_mem_phys = (unsigned long) gbe_dma_addr; ··· 1238 1237 1239 1238 out_gbe_unmap: 1240 1239 arch_phys_wc_del(par->wc_cookie); 1241 - if (gbe_dma_addr) 1242 - dma_free_wc(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); 1243 - out_tiles_free: 1244 - dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), 1245 - (void *)gbe_tiles.cpu, gbe_tiles.dma); 1246 1240 out_release_mem_region: 1247 1241 release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); 1248 1242 out_release_framebuffer: ··· 1254 1258 unregister_framebuffer(info); 1255 1259 gbe_turn_off(); 1256 1260 arch_phys_wc_del(par->wc_cookie); 1257 - if (gbe_dma_addr) 1258 - dma_free_wc(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys); 1259 - dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), 1260 - (void *)gbe_tiles.cpu, gbe_tiles.dma); 1261 1261 release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); 1262 1262 gbefb_remove_sysfs(&p_dev->dev); 1263 1263 framebuffer_release(info);

+3 -1

drivers/video/fbdev/pxa3xx-gcu.c

··· 96 96 }; 97 97 98 98 struct pxa3xx_gcu_priv { 99 + struct device *dev; 99 100 void __iomem *mmio_base; 100 101 struct clk *clk; 101 102 struct pxa3xx_gcu_shared *shared; ··· 494 493 if (size != SHARED_SIZE) 495 494 return -EINVAL; 496 495 497 - return dma_mmap_coherent(NULL, vma, 496 + return dma_mmap_coherent(priv->dev, vma, 498 497 priv->shared, priv->shared_phys, size); 499 498 500 499 case SHARED_SIZE >> PAGE_SHIFT: ··· 671 670 672 671 platform_set_drvdata(pdev, priv); 673 672 priv->resource_mem = r; 673 + priv->dev = dev; 674 674 pxa3xx_gcu_reset(priv); 675 675 pxa3xx_gcu_init_debug_timer(priv); 676 676

+3 -3

include/linux/dma-mapping.h

··· 267 267 268 268 static inline const struct dma_map_ops *get_dma_ops(struct device *dev) 269 269 { 270 - if (dev && dev->dma_ops) 270 + if (dev->dma_ops) 271 271 return dev->dma_ops; 272 - return get_arch_dma_ops(dev ? dev->bus : NULL); 272 + return get_arch_dma_ops(dev->bus); 273 273 } 274 274 275 275 static inline void set_dma_ops(struct device *dev, ··· 650 650 651 651 static inline u64 dma_get_mask(struct device *dev) 652 652 { 653 - if (dev && dev->dma_mask && *dev->dma_mask) 653 + if (dev->dma_mask && *dev->dma_mask) 654 654 return *dev->dma_mask; 655 655 return DMA_BIT_MASK(32); 656 656 }

+6

include/linux/dma-noncoherent.h

··· 72 72 } 73 73 #endif /* CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL */ 74 74 75 + #ifdef CONFIG_ARCH_HAS_DMA_PREP_COHERENT 75 76 void arch_dma_prep_coherent(struct page *page, size_t size); 77 + #else 78 + static inline void arch_dma_prep_coherent(struct page *page, size_t size) 79 + { 80 + } 81 + #endif /* CONFIG_ARCH_HAS_DMA_PREP_COHERENT */ 76 82 77 83 #endif /* _LINUX_DMA_NONCOHERENT_H */

+4

kernel/dma/Kconfig

··· 38 38 config ARCH_HAS_SYNC_DMA_FOR_CPU_ALL 39 39 bool 40 40 41 + config ARCH_HAS_DMA_PREP_COHERENT 42 + bool 43 + 41 44 config ARCH_HAS_DMA_COHERENT_TO_PFN 42 45 bool 43 46 ··· 60 57 61 58 config DMA_REMAP 62 59 depends on MMU 60 + select GENERIC_ALLOCATOR 63 61 bool 64 62 65 63 config DMA_DIRECT_REMAP

+1 -1

kernel/dma/direct.c

··· 311 311 size_t size) 312 312 { 313 313 return swiotlb_force != SWIOTLB_FORCE && 314 - (!dev || dma_capable(dev, dma_addr, size)); 314 + dma_capable(dev, dma_addr, size); 315 315 } 316 316 317 317 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,

+1 -8

kernel/dma/mapping.c

··· 238 238 } 239 239 EXPORT_SYMBOL_GPL(dma_get_required_mask); 240 240 241 - #ifndef arch_dma_alloc_attrs 242 - #define arch_dma_alloc_attrs(dev) (true) 243 - #endif 244 - 245 241 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 246 242 gfp_t flag, unsigned long attrs) 247 243 { 248 244 const struct dma_map_ops *ops = get_dma_ops(dev); 249 245 void *cpu_addr; 250 246 251 - WARN_ON_ONCE(dev && !dev->coherent_dma_mask); 247 + WARN_ON_ONCE(!dev->coherent_dma_mask); 252 248 253 249 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) 254 250 return cpu_addr; 255 251 256 252 /* let the implementation decide on the zone to allocate from: */ 257 253 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); 258 - 259 - if (!arch_dma_alloc_attrs(&dev)) 260 - return NULL; 261 254 262 255 if (dma_is_direct(ops)) 263 256 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);