drm/amd/include: add ip offset header for aldebaran (v5)

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

v1: re-use arct ip base offset array for aldebaran (Le)
v2: create aldebaran ip base offset array for major ip
blocks (Hawking)
v3: re-use arct VCN ip base offset array for aldebaran
(James)
v4: correct MP1 ip base offset array (Hawking)
v5: update VCN ip base offset array to aldebaran one
(Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Le Ma <le.ma@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by

Alex Deucher 5 years ago dd9dd425 d46b417a

+1738

1 changed file

expand all

drivers

gpu

drm

amd

include

aldebaran_ip_offset.h

+1738

drivers/gpu/drm/amd/include/aldebaran_ip_offset.h

··· 1 + /* 2 + * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _aldebaran_ip_offset_HEADER 22 + #define _aldebaran_ip_offset_HEADER 23 + 24 + #define MAX_INSTANCE 7 25 + #define MAX_SEGMENT 6 26 + 27 + struct IP_BASE_INSTANCE { 28 + unsigned int segment[MAX_SEGMENT]; 29 + }; 30 + 31 + struct IP_BASE { 32 + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 33 + }; 34 + 35 + static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } }, 36 + { { 0, 0, 0, 0, 0, 0 } }, 37 + { { 0, 0, 0, 0, 0, 0 } }, 38 + { { 0, 0, 0, 0, 0, 0 } }, 39 + { { 0, 0, 0, 0, 0, 0 } }, 40 + { { 0, 0, 0, 0, 0, 0 } }, 41 + { { 0, 0, 0, 0, 0, 0 } } } }; 42 + static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 43 + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 44 + { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 45 + { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 46 + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 47 + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 48 + { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } }; 49 + static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } }, 50 + { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } }, 51 + { { 0x00000280, 0x02416000, 0, 0, 0, 0 } }, 52 + { { 0, 0, 0, 0, 0, 0 } }, 53 + { { 0, 0, 0, 0, 0, 0 } }, 54 + { { 0, 0, 0, 0, 0, 0 } }, 55 + { { 0, 0, 0, 0, 0, 0 } } } }; 56 + static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } }, 57 + { { 0, 0, 0, 0, 0, 0 } }, 58 + { { 0, 0, 0, 0, 0, 0 } }, 59 + { { 0, 0, 0, 0, 0, 0 } }, 60 + { { 0, 0, 0, 0, 0, 0 } }, 61 + { { 0, 0, 0, 0, 0, 0 } }, 62 + { { 0, 0, 0, 0, 0, 0 } } } }; 63 + static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, 64 + { { 0, 0, 0, 0, 0, 0 } }, 65 + { { 0, 0, 0, 0, 0, 0 } }, 66 + { { 0, 0, 0, 0, 0, 0 } }, 67 + { { 0, 0, 0, 0, 0, 0 } }, 68 + { { 0, 0, 0, 0, 0, 0 } }, 69 + { { 0, 0, 0, 0, 0, 0 } } } }; 70 + static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } }, 71 + { { 0, 0, 0, 0, 0, 0 } }, 72 + { { 0, 0, 0, 0, 0, 0 } }, 73 + { { 0, 0, 0, 0, 0, 0 } }, 74 + { { 0, 0, 0, 0, 0, 0 } }, 75 + { { 0, 0, 0, 0, 0, 0 } }, 76 + { { 0, 0, 0, 0, 0, 0 } } } }; 77 + static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, 78 + { { 0, 0, 0, 0, 0, 0 } }, 79 + { { 0, 0, 0, 0, 0, 0 } }, 80 + { { 0, 0, 0, 0, 0, 0 } }, 81 + { { 0, 0, 0, 0, 0, 0 } }, 82 + { { 0, 0, 0, 0, 0, 0 } }, 83 + { { 0, 0, 0, 0, 0, 0 } } } }; 84 + static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } }, 85 + { { 0, 0, 0, 0, 0, 0 } }, 86 + { { 0, 0, 0, 0, 0, 0 } }, 87 + { { 0, 0, 0, 0, 0, 0 } }, 88 + { { 0, 0, 0, 0, 0, 0 } }, 89 + { { 0, 0, 0, 0, 0, 0 } }, 90 + { { 0, 0, 0, 0, 0, 0 } } } }; 91 + static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } }, 92 + { { 0, 0, 0, 0, 0, 0 } }, 93 + { { 0, 0, 0, 0, 0, 0 } }, 94 + { { 0, 0, 0, 0, 0, 0 } }, 95 + { { 0, 0, 0, 0, 0, 0 } }, 96 + { { 0, 0, 0, 0, 0, 0 } }, 97 + { { 0, 0, 0, 0, 0, 0 } } } }; 98 + static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } }, 99 + { { 0, 0, 0, 0, 0, 0 } }, 100 + { { 0, 0, 0, 0, 0, 0 } }, 101 + { { 0, 0, 0, 0, 0, 0 } }, 102 + { { 0, 0, 0, 0, 0, 0 } }, 103 + { { 0, 0, 0, 0, 0, 0 } }, 104 + { { 0, 0, 0, 0, 0, 0 } } } }; 105 + static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } }, 106 + { { 0, 0, 0, 0, 0, 0 } }, 107 + { { 0, 0, 0, 0, 0, 0 } }, 108 + { { 0, 0, 0, 0, 0, 0 } }, 109 + { { 0, 0, 0, 0, 0, 0 } }, 110 + { { 0, 0, 0, 0, 0, 0 } }, 111 + { { 0, 0, 0, 0, 0, 0 } } } }; 112 + static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } }, 113 + { { 0, 0, 0, 0, 0, 0 } }, 114 + { { 0, 0, 0, 0, 0, 0 } }, 115 + { { 0, 0, 0, 0, 0, 0 } }, 116 + { { 0, 0, 0, 0, 0, 0 } }, 117 + { { 0, 0, 0, 0, 0, 0 } }, 118 + { { 0, 0, 0, 0, 0, 0 } } } }; 119 + static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } }, 120 + { { 0, 0, 0, 0, 0, 0 } }, 121 + { { 0, 0, 0, 0, 0, 0 } }, 122 + { { 0, 0, 0, 0, 0, 0 } }, 123 + { { 0, 0, 0, 0, 0, 0 } }, 124 + { { 0, 0, 0, 0, 0, 0 } }, 125 + { { 0, 0, 0, 0, 0, 0 } } } }; 126 + static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, 127 + { { 0, 0, 0, 0, 0, 0 } }, 128 + { { 0, 0, 0, 0, 0, 0 } }, 129 + { { 0, 0, 0, 0, 0, 0 } }, 130 + { { 0, 0, 0, 0, 0, 0 } }, 131 + { { 0, 0, 0, 0, 0, 0 } }, 132 + { { 0, 0, 0, 0, 0, 0 } } } }; 133 + static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 134 + { { 0, 0, 0, 0, 0, 0 } }, 135 + { { 0, 0, 0, 0, 0, 0 } }, 136 + { { 0, 0, 0, 0, 0, 0 } }, 137 + { { 0, 0, 0, 0, 0, 0 } }, 138 + { { 0, 0, 0, 0, 0, 0 } }, 139 + { { 0, 0, 0, 0, 0, 0 } } } }; 140 + static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 141 + { { 0, 0, 0, 0, 0, 0 } }, 142 + { { 0, 0, 0, 0, 0, 0 } }, 143 + { { 0, 0, 0, 0, 0, 0 } }, 144 + { { 0, 0, 0, 0, 0, 0 } }, 145 + { { 0, 0, 0, 0, 0, 0 } }, 146 + { { 0, 0, 0, 0, 0, 0 } } } }; 147 + static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 148 + { { 0, 0, 0, 0, 0, 0 } }, 149 + { { 0, 0, 0, 0, 0, 0 } }, 150 + { { 0, 0, 0, 0, 0, 0 } }, 151 + { { 0, 0, 0, 0, 0, 0 } }, 152 + { { 0, 0, 0, 0, 0, 0 } }, 153 + { { 0, 0, 0, 0, 0, 0 } } } }; 154 + static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, 155 + { { 0, 0, 0, 0, 0, 0 } }, 156 + { { 0, 0, 0, 0, 0, 0 } }, 157 + { { 0, 0, 0, 0, 0, 0 } }, 158 + { { 0, 0, 0, 0, 0, 0 } }, 159 + { { 0, 0, 0, 0, 0, 0 } }, 160 + { { 0, 0, 0, 0, 0, 0 } } } }; 161 + static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } }, 162 + { { 0, 0, 0, 0, 0, 0 } }, 163 + { { 0, 0, 0, 0, 0, 0 } }, 164 + { { 0, 0, 0, 0, 0, 0 } }, 165 + { { 0, 0, 0, 0, 0, 0 } }, 166 + { { 0, 0, 0, 0, 0, 0 } }, 167 + { { 0, 0, 0, 0, 0, 0 } } } }; 168 + static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, 169 + { { 0, 0, 0, 0, 0, 0 } }, 170 + { { 0, 0, 0, 0, 0, 0 } }, 171 + { { 0, 0, 0, 0, 0, 0 } }, 172 + { { 0, 0, 0, 0, 0, 0 } }, 173 + { { 0, 0, 0, 0, 0, 0 } }, 174 + { { 0, 0, 0, 0, 0, 0 } } } }; 175 + static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, 176 + { { 0, 0, 0, 0, 0, 0 } }, 177 + { { 0, 0, 0, 0, 0, 0 } }, 178 + { { 0, 0, 0, 0, 0, 0 } }, 179 + { { 0, 0, 0, 0, 0, 0 } }, 180 + { { 0, 0, 0, 0, 0, 0 } }, 181 + { { 0, 0, 0, 0, 0, 0 } } } }; 182 + static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, 183 + { { 0, 0, 0, 0, 0, 0 } }, 184 + { { 0, 0, 0, 0, 0, 0 } }, 185 + { { 0, 0, 0, 0, 0, 0 } }, 186 + { { 0, 0, 0, 0, 0, 0 } }, 187 + { { 0, 0, 0, 0, 0, 0 } }, 188 + { { 0, 0, 0, 0, 0, 0 } } } }; 189 + static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, 190 + { { 0, 0, 0, 0, 0, 0 } }, 191 + { { 0, 0, 0, 0, 0, 0 } }, 192 + { { 0, 0, 0, 0, 0, 0 } }, 193 + { { 0, 0, 0, 0, 0, 0 } }, 194 + { { 0, 0, 0, 0, 0, 0 } }, 195 + { { 0, 0, 0, 0, 0, 0 } } } }; 196 + static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, 197 + { { 0, 0, 0, 0, 0, 0 } }, 198 + { { 0, 0, 0, 0, 0, 0 } }, 199 + { { 0, 0, 0, 0, 0, 0 } }, 200 + { { 0, 0, 0, 0, 0, 0 } }, 201 + { { 0, 0, 0, 0, 0, 0 } }, 202 + { { 0, 0, 0, 0, 0, 0 } } } }; 203 + static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } }, 204 + { { 0, 0, 0, 0, 0, 0 } }, 205 + { { 0, 0, 0, 0, 0, 0 } }, 206 + { { 0, 0, 0, 0, 0, 0 } }, 207 + { { 0, 0, 0, 0, 0, 0 } }, 208 + { { 0, 0, 0, 0, 0, 0 } }, 209 + { { 0, 0, 0, 0, 0, 0 } } } }; 210 + static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, 211 + { { 0, 0, 0, 0, 0, 0 } }, 212 + { { 0, 0, 0, 0, 0, 0 } }, 213 + { { 0, 0, 0, 0, 0, 0 } }, 214 + { { 0, 0, 0, 0, 0, 0 } }, 215 + { { 0, 0, 0, 0, 0, 0 } }, 216 + { { 0, 0, 0, 0, 0, 0 } } } }; 217 + static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } }, 218 + { { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } }, 219 + { { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } }, 220 + { { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } }, 221 + { { 0, 0, 0, 0, 0, 0 } }, 222 + { { 0, 0, 0, 0, 0, 0 } }, 223 + { { 0, 0, 0, 0, 0, 0 } } } }; 224 + static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, 225 + { { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } }, 226 + { { 0, 0, 0, 0, 0, 0 } }, 227 + { { 0, 0, 0, 0, 0, 0 } }, 228 + { { 0, 0, 0, 0, 0, 0 } }, 229 + { { 0, 0, 0, 0, 0, 0 } }, 230 + { { 0, 0, 0, 0, 0, 0 } } } }; 231 + static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } }, 232 + { { 0, 0, 0, 0, 0, 0 } }, 233 + { { 0, 0, 0, 0, 0, 0 } }, 234 + { { 0, 0, 0, 0, 0, 0 } }, 235 + { { 0, 0, 0, 0, 0, 0 } }, 236 + { { 0, 0, 0, 0, 0, 0 } }, 237 + { { 0, 0, 0, 0, 0, 0 } } } }; 238 + static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } }, 239 + { { 0, 0, 0, 0, 0, 0 } }, 240 + { { 0, 0, 0, 0, 0, 0 } }, 241 + { { 0, 0, 0, 0, 0, 0 } }, 242 + { { 0, 0, 0, 0, 0, 0 } }, 243 + { { 0, 0, 0, 0, 0, 0 } }, 244 + { { 0, 0, 0, 0, 0, 0 } } } }; 245 + static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } }, 246 + { { 0, 0, 0, 0, 0, 0 } }, 247 + { { 0, 0, 0, 0, 0, 0 } }, 248 + { { 0, 0, 0, 0, 0, 0 } }, 249 + { { 0, 0, 0, 0, 0, 0 } }, 250 + { { 0, 0, 0, 0, 0, 0 } }, 251 + { { 0, 0, 0, 0, 0, 0 } } } }; 252 + static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } }, 253 + { { 0, 0, 0, 0, 0, 0 } }, 254 + { { 0, 0, 0, 0, 0, 0 } }, 255 + { { 0, 0, 0, 0, 0, 0 } }, 256 + { { 0, 0, 0, 0, 0, 0 } }, 257 + { { 0, 0, 0, 0, 0, 0 } }, 258 + { { 0, 0, 0, 0, 0, 0 } } } }; 259 + static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } }, 260 + { { 0x04740000, 0x04A00000, 0, 0, 0, 0 } }, 261 + { { 0x04780000, 0x04A40000, 0, 0, 0, 0 } }, 262 + { { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } }, 263 + { { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } }, 264 + { { 0x04840000, 0x04B00000, 0, 0, 0, 0 } }, 265 + { { 0, 0, 0, 0, 0, 0 } } } }; 266 + 267 + 268 + #define ATHUB_BASE__INST0_SEG0 0x00000C20 269 + #define ATHUB_BASE__INST0_SEG1 0x02408C00 270 + #define ATHUB_BASE__INST0_SEG2 0 271 + #define ATHUB_BASE__INST0_SEG3 0 272 + #define ATHUB_BASE__INST0_SEG4 0 273 + #define ATHUB_BASE__INST0_SEG5 0 274 + 275 + #define ATHUB_BASE__INST1_SEG0 0 276 + #define ATHUB_BASE__INST1_SEG1 0 277 + #define ATHUB_BASE__INST1_SEG2 0 278 + #define ATHUB_BASE__INST1_SEG3 0 279 + #define ATHUB_BASE__INST1_SEG4 0 280 + #define ATHUB_BASE__INST1_SEG5 0 281 + 282 + #define ATHUB_BASE__INST2_SEG0 0 283 + #define ATHUB_BASE__INST2_SEG1 0 284 + #define ATHUB_BASE__INST2_SEG2 0 285 + #define ATHUB_BASE__INST2_SEG3 0 286 + #define ATHUB_BASE__INST2_SEG4 0 287 + #define ATHUB_BASE__INST2_SEG5 0 288 + 289 + #define ATHUB_BASE__INST3_SEG0 0 290 + #define ATHUB_BASE__INST3_SEG1 0 291 + #define ATHUB_BASE__INST3_SEG2 0 292 + #define ATHUB_BASE__INST3_SEG3 0 293 + #define ATHUB_BASE__INST3_SEG4 0 294 + #define ATHUB_BASE__INST3_SEG5 0 295 + 296 + #define ATHUB_BASE__INST4_SEG0 0 297 + #define ATHUB_BASE__INST4_SEG1 0 298 + #define ATHUB_BASE__INST4_SEG2 0 299 + #define ATHUB_BASE__INST4_SEG3 0 300 + #define ATHUB_BASE__INST4_SEG4 0 301 + #define ATHUB_BASE__INST4_SEG5 0 302 + 303 + #define ATHUB_BASE__INST5_SEG0 0 304 + #define ATHUB_BASE__INST5_SEG1 0 305 + #define ATHUB_BASE__INST5_SEG2 0 306 + #define ATHUB_BASE__INST5_SEG3 0 307 + #define ATHUB_BASE__INST5_SEG4 0 308 + #define ATHUB_BASE__INST5_SEG5 0 309 + 310 + #define ATHUB_BASE__INST6_SEG0 0 311 + #define ATHUB_BASE__INST6_SEG1 0 312 + #define ATHUB_BASE__INST6_SEG2 0 313 + #define ATHUB_BASE__INST6_SEG3 0 314 + #define ATHUB_BASE__INST6_SEG4 0 315 + #define ATHUB_BASE__INST6_SEG5 0 316 + 317 + #define CLK_BASE__INST0_SEG0 0x00016C00 318 + #define CLK_BASE__INST0_SEG1 0x02401800 319 + #define CLK_BASE__INST0_SEG2 0 320 + #define CLK_BASE__INST0_SEG3 0 321 + #define CLK_BASE__INST0_SEG4 0 322 + #define CLK_BASE__INST0_SEG5 0 323 + 324 + #define CLK_BASE__INST1_SEG0 0x00016E00 325 + #define CLK_BASE__INST1_SEG1 0x02401C00 326 + #define CLK_BASE__INST1_SEG2 0 327 + #define CLK_BASE__INST1_SEG3 0 328 + #define CLK_BASE__INST1_SEG4 0 329 + #define CLK_BASE__INST1_SEG5 0 330 + 331 + #define CLK_BASE__INST2_SEG0 0x00017000 332 + #define CLK_BASE__INST2_SEG1 0x02402000 333 + #define CLK_BASE__INST2_SEG2 0 334 + #define CLK_BASE__INST2_SEG3 0 335 + #define CLK_BASE__INST2_SEG4 0 336 + #define CLK_BASE__INST2_SEG5 0 337 + 338 + #define CLK_BASE__INST3_SEG0 0x00017200 339 + #define CLK_BASE__INST3_SEG1 0x02402400 340 + #define CLK_BASE__INST3_SEG2 0 341 + #define CLK_BASE__INST3_SEG3 0 342 + #define CLK_BASE__INST3_SEG4 0 343 + #define CLK_BASE__INST3_SEG5 0 344 + 345 + #define CLK_BASE__INST4_SEG0 0x0001B000 346 + #define CLK_BASE__INST4_SEG1 0x0242D800 347 + #define CLK_BASE__INST4_SEG2 0 348 + #define CLK_BASE__INST4_SEG3 0 349 + #define CLK_BASE__INST4_SEG4 0 350 + #define CLK_BASE__INST4_SEG5 0 351 + 352 + #define CLK_BASE__INST5_SEG0 0x0001B200 353 + #define CLK_BASE__INST5_SEG1 0x0242DC00 354 + #define CLK_BASE__INST5_SEG2 0 355 + #define CLK_BASE__INST5_SEG3 0 356 + #define CLK_BASE__INST5_SEG4 0 357 + #define CLK_BASE__INST5_SEG5 0 358 + 359 + #define CLK_BASE__INST6_SEG0 0x00017E00 360 + #define CLK_BASE__INST6_SEG1 0x0240BC00 361 + #define CLK_BASE__INST6_SEG2 0 362 + #define CLK_BASE__INST6_SEG3 0 363 + #define CLK_BASE__INST6_SEG4 0 364 + #define CLK_BASE__INST6_SEG5 0 365 + 366 + #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 367 + #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 368 + #define DBGU_IO0_BASE__INST0_SEG2 0 369 + #define DBGU_IO0_BASE__INST0_SEG3 0 370 + #define DBGU_IO0_BASE__INST0_SEG4 0 371 + #define DBGU_IO0_BASE__INST0_SEG5 0 372 + 373 + #define DBGU_IO0_BASE__INST1_SEG0 0x00000260 374 + #define DBGU_IO0_BASE__INST1_SEG1 0x02413C00 375 + #define DBGU_IO0_BASE__INST1_SEG2 0 376 + #define DBGU_IO0_BASE__INST1_SEG3 0 377 + #define DBGU_IO0_BASE__INST1_SEG4 0 378 + #define DBGU_IO0_BASE__INST1_SEG5 0 379 + 380 + #define DBGU_IO0_BASE__INST2_SEG0 0x00000280 381 + #define DBGU_IO0_BASE__INST2_SEG1 0x02416000 382 + #define DBGU_IO0_BASE__INST2_SEG2 0 383 + #define DBGU_IO0_BASE__INST2_SEG3 0 384 + #define DBGU_IO0_BASE__INST2_SEG4 0 385 + #define DBGU_IO0_BASE__INST2_SEG5 0 386 + 387 + #define DBGU_IO0_BASE__INST3_SEG0 0 388 + #define DBGU_IO0_BASE__INST3_SEG1 0 389 + #define DBGU_IO0_BASE__INST3_SEG2 0 390 + #define DBGU_IO0_BASE__INST3_SEG3 0 391 + #define DBGU_IO0_BASE__INST3_SEG4 0 392 + #define DBGU_IO0_BASE__INST3_SEG5 0 393 + 394 + #define DBGU_IO0_BASE__INST4_SEG0 0 395 + #define DBGU_IO0_BASE__INST4_SEG1 0 396 + #define DBGU_IO0_BASE__INST4_SEG2 0 397 + #define DBGU_IO0_BASE__INST4_SEG3 0 398 + #define DBGU_IO0_BASE__INST4_SEG4 0 399 + #define DBGU_IO0_BASE__INST4_SEG5 0 400 + 401 + #define DBGU_IO0_BASE__INST5_SEG0 0 402 + #define DBGU_IO0_BASE__INST5_SEG1 0 403 + #define DBGU_IO0_BASE__INST5_SEG2 0 404 + #define DBGU_IO0_BASE__INST5_SEG3 0 405 + #define DBGU_IO0_BASE__INST5_SEG4 0 406 + #define DBGU_IO0_BASE__INST5_SEG5 0 407 + 408 + #define DBGU_IO0_BASE__INST6_SEG0 0 409 + #define DBGU_IO0_BASE__INST6_SEG1 0 410 + #define DBGU_IO0_BASE__INST6_SEG2 0 411 + #define DBGU_IO0_BASE__INST6_SEG3 0 412 + #define DBGU_IO0_BASE__INST6_SEG4 0 413 + #define DBGU_IO0_BASE__INST6_SEG5 0 414 + 415 + #define DF_BASE__INST0_SEG0 0x00007000 416 + #define DF_BASE__INST0_SEG1 0x0240B800 417 + #define DF_BASE__INST0_SEG2 0x07C00000 418 + #define DF_BASE__INST0_SEG3 0 419 + #define DF_BASE__INST0_SEG4 0 420 + #define DF_BASE__INST0_SEG5 0 421 + 422 + #define DF_BASE__INST1_SEG0 0 423 + #define DF_BASE__INST1_SEG1 0 424 + #define DF_BASE__INST1_SEG2 0 425 + #define DF_BASE__INST1_SEG3 0 426 + #define DF_BASE__INST1_SEG4 0 427 + #define DF_BASE__INST1_SEG5 0 428 + 429 + #define DF_BASE__INST2_SEG0 0 430 + #define DF_BASE__INST2_SEG1 0 431 + #define DF_BASE__INST2_SEG2 0 432 + #define DF_BASE__INST2_SEG3 0 433 + #define DF_BASE__INST2_SEG4 0 434 + #define DF_BASE__INST2_SEG5 0 435 + 436 + #define DF_BASE__INST3_SEG0 0 437 + #define DF_BASE__INST3_SEG1 0 438 + #define DF_BASE__INST3_SEG2 0 439 + #define DF_BASE__INST3_SEG3 0 440 + #define DF_BASE__INST3_SEG4 0 441 + #define DF_BASE__INST3_SEG5 0 442 + 443 + #define DF_BASE__INST4_SEG0 0 444 + #define DF_BASE__INST4_SEG1 0 445 + #define DF_BASE__INST4_SEG2 0 446 + #define DF_BASE__INST4_SEG3 0 447 + #define DF_BASE__INST4_SEG4 0 448 + #define DF_BASE__INST4_SEG5 0 449 + 450 + #define DF_BASE__INST5_SEG0 0 451 + #define DF_BASE__INST5_SEG1 0 452 + #define DF_BASE__INST5_SEG2 0 453 + #define DF_BASE__INST5_SEG3 0 454 + #define DF_BASE__INST5_SEG4 0 455 + #define DF_BASE__INST5_SEG5 0 456 + 457 + #define DF_BASE__INST6_SEG0 0 458 + #define DF_BASE__INST6_SEG1 0 459 + #define DF_BASE__INST6_SEG2 0 460 + #define DF_BASE__INST6_SEG3 0 461 + #define DF_BASE__INST6_SEG4 0 462 + #define DF_BASE__INST6_SEG5 0 463 + 464 + #define FUSE_BASE__INST0_SEG0 0x00017400 465 + #define FUSE_BASE__INST0_SEG1 0x02401400 466 + #define FUSE_BASE__INST0_SEG2 0 467 + #define FUSE_BASE__INST0_SEG3 0 468 + #define FUSE_BASE__INST0_SEG4 0 469 + #define FUSE_BASE__INST0_SEG5 0 470 + 471 + #define FUSE_BASE__INST1_SEG0 0 472 + #define FUSE_BASE__INST1_SEG1 0 473 + #define FUSE_BASE__INST1_SEG2 0 474 + #define FUSE_BASE__INST1_SEG3 0 475 + #define FUSE_BASE__INST1_SEG4 0 476 + #define FUSE_BASE__INST1_SEG5 0 477 + 478 + #define FUSE_BASE__INST2_SEG0 0 479 + #define FUSE_BASE__INST2_SEG1 0 480 + #define FUSE_BASE__INST2_SEG2 0 481 + #define FUSE_BASE__INST2_SEG3 0 482 + #define FUSE_BASE__INST2_SEG4 0 483 + #define FUSE_BASE__INST2_SEG5 0 484 + 485 + #define FUSE_BASE__INST3_SEG0 0 486 + #define FUSE_BASE__INST3_SEG1 0 487 + #define FUSE_BASE__INST3_SEG2 0 488 + #define FUSE_BASE__INST3_SEG3 0 489 + #define FUSE_BASE__INST3_SEG4 0 490 + #define FUSE_BASE__INST3_SEG5 0 491 + 492 + #define FUSE_BASE__INST4_SEG0 0 493 + #define FUSE_BASE__INST4_SEG1 0 494 + #define FUSE_BASE__INST4_SEG2 0 495 + #define FUSE_BASE__INST4_SEG3 0 496 + #define FUSE_BASE__INST4_SEG4 0 497 + #define FUSE_BASE__INST4_SEG5 0 498 + 499 + #define FUSE_BASE__INST5_SEG0 0 500 + #define FUSE_BASE__INST5_SEG1 0 501 + #define FUSE_BASE__INST5_SEG2 0 502 + #define FUSE_BASE__INST5_SEG3 0 503 + #define FUSE_BASE__INST5_SEG4 0 504 + #define FUSE_BASE__INST5_SEG5 0 505 + 506 + #define FUSE_BASE__INST6_SEG0 0 507 + #define FUSE_BASE__INST6_SEG1 0 508 + #define FUSE_BASE__INST6_SEG2 0 509 + #define FUSE_BASE__INST6_SEG3 0 510 + #define FUSE_BASE__INST6_SEG4 0 511 + #define FUSE_BASE__INST6_SEG5 0 512 + 513 + #define GC_BASE__INST0_SEG0 0x00002000 514 + #define GC_BASE__INST0_SEG1 0x0000A000 515 + #define GC_BASE__INST0_SEG2 0x02402C00 516 + #define GC_BASE__INST0_SEG3 0 517 + #define GC_BASE__INST0_SEG4 0 518 + #define GC_BASE__INST0_SEG5 0 519 + 520 + #define GC_BASE__INST1_SEG0 0 521 + #define GC_BASE__INST1_SEG1 0 522 + #define GC_BASE__INST1_SEG2 0 523 + #define GC_BASE__INST1_SEG3 0 524 + #define GC_BASE__INST1_SEG4 0 525 + #define GC_BASE__INST1_SEG5 0 526 + 527 + #define GC_BASE__INST2_SEG0 0 528 + #define GC_BASE__INST2_SEG1 0 529 + #define GC_BASE__INST2_SEG2 0 530 + #define GC_BASE__INST2_SEG3 0 531 + #define GC_BASE__INST2_SEG4 0 532 + #define GC_BASE__INST2_SEG5 0 533 + 534 + #define GC_BASE__INST3_SEG0 0 535 + #define GC_BASE__INST3_SEG1 0 536 + #define GC_BASE__INST3_SEG2 0 537 + #define GC_BASE__INST3_SEG3 0 538 + #define GC_BASE__INST3_SEG4 0 539 + #define GC_BASE__INST3_SEG5 0 540 + 541 + #define GC_BASE__INST4_SEG0 0 542 + #define GC_BASE__INST4_SEG1 0 543 + #define GC_BASE__INST4_SEG2 0 544 + #define GC_BASE__INST4_SEG3 0 545 + #define GC_BASE__INST4_SEG4 0 546 + #define GC_BASE__INST4_SEG5 0 547 + 548 + #define GC_BASE__INST5_SEG0 0 549 + #define GC_BASE__INST5_SEG1 0 550 + #define GC_BASE__INST5_SEG2 0 551 + #define GC_BASE__INST5_SEG3 0 552 + #define GC_BASE__INST5_SEG4 0 553 + #define GC_BASE__INST5_SEG5 0 554 + 555 + #define GC_BASE__INST6_SEG0 0 556 + #define GC_BASE__INST6_SEG1 0 557 + #define GC_BASE__INST6_SEG2 0 558 + #define GC_BASE__INST6_SEG3 0 559 + #define GC_BASE__INST6_SEG4 0 560 + #define GC_BASE__INST6_SEG5 0 561 + 562 + #define HDP_BASE__INST0_SEG0 0x00000F20 563 + #define HDP_BASE__INST0_SEG1 0x0240A400 564 + #define HDP_BASE__INST0_SEG2 0 565 + #define HDP_BASE__INST0_SEG3 0 566 + #define HDP_BASE__INST0_SEG4 0 567 + #define HDP_BASE__INST0_SEG5 0 568 + 569 + #define HDP_BASE__INST1_SEG0 0 570 + #define HDP_BASE__INST1_SEG1 0 571 + #define HDP_BASE__INST1_SEG2 0 572 + #define HDP_BASE__INST1_SEG3 0 573 + #define HDP_BASE__INST1_SEG4 0 574 + #define HDP_BASE__INST1_SEG5 0 575 + 576 + #define HDP_BASE__INST2_SEG0 0 577 + #define HDP_BASE__INST2_SEG1 0 578 + #define HDP_BASE__INST2_SEG2 0 579 + #define HDP_BASE__INST2_SEG3 0 580 + #define HDP_BASE__INST2_SEG4 0 581 + #define HDP_BASE__INST2_SEG5 0 582 + 583 + #define HDP_BASE__INST3_SEG0 0 584 + #define HDP_BASE__INST3_SEG1 0 585 + #define HDP_BASE__INST3_SEG2 0 586 + #define HDP_BASE__INST3_SEG3 0 587 + #define HDP_BASE__INST3_SEG4 0 588 + #define HDP_BASE__INST3_SEG5 0 589 + 590 + #define HDP_BASE__INST4_SEG0 0 591 + #define HDP_BASE__INST4_SEG1 0 592 + #define HDP_BASE__INST4_SEG2 0 593 + #define HDP_BASE__INST4_SEG3 0 594 + #define HDP_BASE__INST4_SEG4 0 595 + #define HDP_BASE__INST4_SEG5 0 596 + 597 + #define HDP_BASE__INST5_SEG0 0 598 + #define HDP_BASE__INST5_SEG1 0 599 + #define HDP_BASE__INST5_SEG2 0 600 + #define HDP_BASE__INST5_SEG3 0 601 + #define HDP_BASE__INST5_SEG4 0 602 + #define HDP_BASE__INST5_SEG5 0 603 + 604 + #define HDP_BASE__INST6_SEG0 0 605 + #define HDP_BASE__INST6_SEG1 0 606 + #define HDP_BASE__INST6_SEG2 0 607 + #define HDP_BASE__INST6_SEG3 0 608 + #define HDP_BASE__INST6_SEG4 0 609 + #define HDP_BASE__INST6_SEG5 0 610 + 611 + #define IOAGR0_BASE__INST0_SEG0 0x02419000 612 + #define IOAGR0_BASE__INST0_SEG1 0x056C0000 613 + #define IOAGR0_BASE__INST0_SEG2 0 614 + #define IOAGR0_BASE__INST0_SEG3 0 615 + #define IOAGR0_BASE__INST0_SEG4 0 616 + #define IOAGR0_BASE__INST0_SEG5 0 617 + 618 + #define IOAGR0_BASE__INST1_SEG0 0 619 + #define IOAGR0_BASE__INST1_SEG1 0 620 + #define IOAGR0_BASE__INST1_SEG2 0 621 + #define IOAGR0_BASE__INST1_SEG3 0 622 + #define IOAGR0_BASE__INST1_SEG4 0 623 + #define IOAGR0_BASE__INST1_SEG5 0 624 + 625 + #define IOAGR0_BASE__INST2_SEG0 0 626 + #define IOAGR0_BASE__INST2_SEG1 0 627 + #define IOAGR0_BASE__INST2_SEG2 0 628 + #define IOAGR0_BASE__INST2_SEG3 0 629 + #define IOAGR0_BASE__INST2_SEG4 0 630 + #define IOAGR0_BASE__INST2_SEG5 0 631 + 632 + #define IOAGR0_BASE__INST3_SEG0 0 633 + #define IOAGR0_BASE__INST3_SEG1 0 634 + #define IOAGR0_BASE__INST3_SEG2 0 635 + #define IOAGR0_BASE__INST3_SEG3 0 636 + #define IOAGR0_BASE__INST3_SEG4 0 637 + #define IOAGR0_BASE__INST3_SEG5 0 638 + 639 + #define IOAGR0_BASE__INST4_SEG0 0 640 + #define IOAGR0_BASE__INST4_SEG1 0 641 + #define IOAGR0_BASE__INST4_SEG2 0 642 + #define IOAGR0_BASE__INST4_SEG3 0 643 + #define IOAGR0_BASE__INST4_SEG4 0 644 + #define IOAGR0_BASE__INST4_SEG5 0 645 + 646 + #define IOAGR0_BASE__INST5_SEG0 0 647 + #define IOAGR0_BASE__INST5_SEG1 0 648 + #define IOAGR0_BASE__INST5_SEG2 0 649 + #define IOAGR0_BASE__INST5_SEG3 0 650 + #define IOAGR0_BASE__INST5_SEG4 0 651 + #define IOAGR0_BASE__INST5_SEG5 0 652 + 653 + #define IOAGR0_BASE__INST6_SEG0 0 654 + #define IOAGR0_BASE__INST6_SEG1 0 655 + #define IOAGR0_BASE__INST6_SEG2 0 656 + #define IOAGR0_BASE__INST6_SEG3 0 657 + #define IOAGR0_BASE__INST6_SEG4 0 658 + #define IOAGR0_BASE__INST6_SEG5 0 659 + 660 + #define IOAPIC0_BASE__INST0_SEG0 0x00A00000 661 + #define IOAPIC0_BASE__INST0_SEG1 0x0241F000 662 + #define IOAPIC0_BASE__INST0_SEG2 0x050C0000 663 + #define IOAPIC0_BASE__INST0_SEG3 0 664 + #define IOAPIC0_BASE__INST0_SEG4 0 665 + #define IOAPIC0_BASE__INST0_SEG5 0 666 + 667 + #define IOAPIC0_BASE__INST1_SEG0 0 668 + #define IOAPIC0_BASE__INST1_SEG1 0 669 + #define IOAPIC0_BASE__INST1_SEG2 0 670 + #define IOAPIC0_BASE__INST1_SEG3 0 671 + #define IOAPIC0_BASE__INST1_SEG4 0 672 + #define IOAPIC0_BASE__INST1_SEG5 0 673 + 674 + #define IOAPIC0_BASE__INST2_SEG0 0 675 + #define IOAPIC0_BASE__INST2_SEG1 0 676 + #define IOAPIC0_BASE__INST2_SEG2 0 677 + #define IOAPIC0_BASE__INST2_SEG3 0 678 + #define IOAPIC0_BASE__INST2_SEG4 0 679 + #define IOAPIC0_BASE__INST2_SEG5 0 680 + 681 + #define IOAPIC0_BASE__INST3_SEG0 0 682 + #define IOAPIC0_BASE__INST3_SEG1 0 683 + #define IOAPIC0_BASE__INST3_SEG2 0 684 + #define IOAPIC0_BASE__INST3_SEG3 0 685 + #define IOAPIC0_BASE__INST3_SEG4 0 686 + #define IOAPIC0_BASE__INST3_SEG5 0 687 + 688 + #define IOAPIC0_BASE__INST4_SEG0 0 689 + #define IOAPIC0_BASE__INST4_SEG1 0 690 + #define IOAPIC0_BASE__INST4_SEG2 0 691 + #define IOAPIC0_BASE__INST4_SEG3 0 692 + #define IOAPIC0_BASE__INST4_SEG4 0 693 + #define IOAPIC0_BASE__INST4_SEG5 0 694 + 695 + #define IOAPIC0_BASE__INST5_SEG0 0 696 + #define IOAPIC0_BASE__INST5_SEG1 0 697 + #define IOAPIC0_BASE__INST5_SEG2 0 698 + #define IOAPIC0_BASE__INST5_SEG3 0 699 + #define IOAPIC0_BASE__INST5_SEG4 0 700 + #define IOAPIC0_BASE__INST5_SEG5 0 701 + 702 + #define IOAPIC0_BASE__INST6_SEG0 0 703 + #define IOAPIC0_BASE__INST6_SEG1 0 704 + #define IOAPIC0_BASE__INST6_SEG2 0 705 + #define IOAPIC0_BASE__INST6_SEG3 0 706 + #define IOAPIC0_BASE__INST6_SEG4 0 707 + #define IOAPIC0_BASE__INST6_SEG5 0 708 + 709 + #define IOHC0_BASE__INST0_SEG0 0x00010000 710 + #define IOHC0_BASE__INST0_SEG1 0x02406000 711 + #define IOHC0_BASE__INST0_SEG2 0x04EC0000 712 + #define IOHC0_BASE__INST0_SEG3 0 713 + #define IOHC0_BASE__INST0_SEG4 0 714 + #define IOHC0_BASE__INST0_SEG5 0 715 + 716 + #define IOHC0_BASE__INST1_SEG0 0 717 + #define IOHC0_BASE__INST1_SEG1 0 718 + #define IOHC0_BASE__INST1_SEG2 0 719 + #define IOHC0_BASE__INST1_SEG3 0 720 + #define IOHC0_BASE__INST1_SEG4 0 721 + #define IOHC0_BASE__INST1_SEG5 0 722 + 723 + #define IOHC0_BASE__INST2_SEG0 0 724 + #define IOHC0_BASE__INST2_SEG1 0 725 + #define IOHC0_BASE__INST2_SEG2 0 726 + #define IOHC0_BASE__INST2_SEG3 0 727 + #define IOHC0_BASE__INST2_SEG4 0 728 + #define IOHC0_BASE__INST2_SEG5 0 729 + 730 + #define IOHC0_BASE__INST3_SEG0 0 731 + #define IOHC0_BASE__INST3_SEG1 0 732 + #define IOHC0_BASE__INST3_SEG2 0 733 + #define IOHC0_BASE__INST3_SEG3 0 734 + #define IOHC0_BASE__INST3_SEG4 0 735 + #define IOHC0_BASE__INST3_SEG5 0 736 + 737 + #define IOHC0_BASE__INST4_SEG0 0 738 + #define IOHC0_BASE__INST4_SEG1 0 739 + #define IOHC0_BASE__INST4_SEG2 0 740 + #define IOHC0_BASE__INST4_SEG3 0 741 + #define IOHC0_BASE__INST4_SEG4 0 742 + #define IOHC0_BASE__INST4_SEG5 0 743 + 744 + #define IOHC0_BASE__INST5_SEG0 0 745 + #define IOHC0_BASE__INST5_SEG1 0 746 + #define IOHC0_BASE__INST5_SEG2 0 747 + #define IOHC0_BASE__INST5_SEG3 0 748 + #define IOHC0_BASE__INST5_SEG4 0 749 + #define IOHC0_BASE__INST5_SEG5 0 750 + 751 + #define IOHC0_BASE__INST6_SEG0 0 752 + #define IOHC0_BASE__INST6_SEG1 0 753 + #define IOHC0_BASE__INST6_SEG2 0 754 + #define IOHC0_BASE__INST6_SEG3 0 755 + #define IOHC0_BASE__INST6_SEG4 0 756 + #define IOHC0_BASE__INST6_SEG5 0 757 + 758 + #define L1IMUIOAGR0_BASE__INST0_SEG0 0x0240CC00 759 + #define L1IMUIOAGR0_BASE__INST0_SEG1 0x05200000 760 + #define L1IMUIOAGR0_BASE__INST0_SEG2 0 761 + #define L1IMUIOAGR0_BASE__INST0_SEG3 0 762 + #define L1IMUIOAGR0_BASE__INST0_SEG4 0 763 + #define L1IMUIOAGR0_BASE__INST0_SEG5 0 764 + 765 + #define L1IMUIOAGR0_BASE__INST1_SEG0 0 766 + #define L1IMUIOAGR0_BASE__INST1_SEG1 0 767 + #define L1IMUIOAGR0_BASE__INST1_SEG2 0 768 + #define L1IMUIOAGR0_BASE__INST1_SEG3 0 769 + #define L1IMUIOAGR0_BASE__INST1_SEG4 0 770 + #define L1IMUIOAGR0_BASE__INST1_SEG5 0 771 + 772 + #define L1IMUIOAGR0_BASE__INST2_SEG0 0 773 + #define L1IMUIOAGR0_BASE__INST2_SEG1 0 774 + #define L1IMUIOAGR0_BASE__INST2_SEG2 0 775 + #define L1IMUIOAGR0_BASE__INST2_SEG3 0 776 + #define L1IMUIOAGR0_BASE__INST2_SEG4 0 777 + #define L1IMUIOAGR0_BASE__INST2_SEG5 0 778 + 779 + #define L1IMUIOAGR0_BASE__INST3_SEG0 0 780 + #define L1IMUIOAGR0_BASE__INST3_SEG1 0 781 + #define L1IMUIOAGR0_BASE__INST3_SEG2 0 782 + #define L1IMUIOAGR0_BASE__INST3_SEG3 0 783 + #define L1IMUIOAGR0_BASE__INST3_SEG4 0 784 + #define L1IMUIOAGR0_BASE__INST3_SEG5 0 785 + 786 + #define L1IMUIOAGR0_BASE__INST4_SEG0 0 787 + #define L1IMUIOAGR0_BASE__INST4_SEG1 0 788 + #define L1IMUIOAGR0_BASE__INST4_SEG2 0 789 + #define L1IMUIOAGR0_BASE__INST4_SEG3 0 790 + #define L1IMUIOAGR0_BASE__INST4_SEG4 0 791 + #define L1IMUIOAGR0_BASE__INST4_SEG5 0 792 + 793 + #define L1IMUIOAGR0_BASE__INST5_SEG0 0 794 + #define L1IMUIOAGR0_BASE__INST5_SEG1 0 795 + #define L1IMUIOAGR0_BASE__INST5_SEG2 0 796 + #define L1IMUIOAGR0_BASE__INST5_SEG3 0 797 + #define L1IMUIOAGR0_BASE__INST5_SEG4 0 798 + #define L1IMUIOAGR0_BASE__INST5_SEG5 0 799 + 800 + #define L1IMUIOAGR0_BASE__INST6_SEG0 0 801 + #define L1IMUIOAGR0_BASE__INST6_SEG1 0 802 + #define L1IMUIOAGR0_BASE__INST6_SEG2 0 803 + #define L1IMUIOAGR0_BASE__INST6_SEG3 0 804 + #define L1IMUIOAGR0_BASE__INST6_SEG4 0 805 + #define L1IMUIOAGR0_BASE__INST6_SEG5 0 806 + 807 + #define L1IMUPCIE0_BASE__INST0_SEG0 0x0240C800 808 + #define L1IMUPCIE0_BASE__INST0_SEG1 0x051C0000 809 + #define L1IMUPCIE0_BASE__INST0_SEG2 0 810 + #define L1IMUPCIE0_BASE__INST0_SEG3 0 811 + #define L1IMUPCIE0_BASE__INST0_SEG4 0 812 + #define L1IMUPCIE0_BASE__INST0_SEG5 0 813 + 814 + #define L1IMUPCIE0_BASE__INST1_SEG0 0 815 + #define L1IMUPCIE0_BASE__INST1_SEG1 0 816 + #define L1IMUPCIE0_BASE__INST1_SEG2 0 817 + #define L1IMUPCIE0_BASE__INST1_SEG3 0 818 + #define L1IMUPCIE0_BASE__INST1_SEG4 0 819 + #define L1IMUPCIE0_BASE__INST1_SEG5 0 820 + 821 + #define L1IMUPCIE0_BASE__INST2_SEG0 0 822 + #define L1IMUPCIE0_BASE__INST2_SEG1 0 823 + #define L1IMUPCIE0_BASE__INST2_SEG2 0 824 + #define L1IMUPCIE0_BASE__INST2_SEG3 0 825 + #define L1IMUPCIE0_BASE__INST2_SEG4 0 826 + #define L1IMUPCIE0_BASE__INST2_SEG5 0 827 + 828 + #define L1IMUPCIE0_BASE__INST3_SEG0 0 829 + #define L1IMUPCIE0_BASE__INST3_SEG1 0 830 + #define L1IMUPCIE0_BASE__INST3_SEG2 0 831 + #define L1IMUPCIE0_BASE__INST3_SEG3 0 832 + #define L1IMUPCIE0_BASE__INST3_SEG4 0 833 + #define L1IMUPCIE0_BASE__INST3_SEG5 0 834 + 835 + #define L1IMUPCIE0_BASE__INST4_SEG0 0 836 + #define L1IMUPCIE0_BASE__INST4_SEG1 0 837 + #define L1IMUPCIE0_BASE__INST4_SEG2 0 838 + #define L1IMUPCIE0_BASE__INST4_SEG3 0 839 + #define L1IMUPCIE0_BASE__INST4_SEG4 0 840 + #define L1IMUPCIE0_BASE__INST4_SEG5 0 841 + 842 + #define L1IMUPCIE0_BASE__INST5_SEG0 0 843 + #define L1IMUPCIE0_BASE__INST5_SEG1 0 844 + #define L1IMUPCIE0_BASE__INST5_SEG2 0 845 + #define L1IMUPCIE0_BASE__INST5_SEG3 0 846 + #define L1IMUPCIE0_BASE__INST5_SEG4 0 847 + #define L1IMUPCIE0_BASE__INST5_SEG5 0 848 + 849 + #define L1IMUPCIE0_BASE__INST6_SEG0 0 850 + #define L1IMUPCIE0_BASE__INST6_SEG1 0 851 + #define L1IMUPCIE0_BASE__INST6_SEG2 0 852 + #define L1IMUPCIE0_BASE__INST6_SEG3 0 853 + #define L1IMUPCIE0_BASE__INST6_SEG4 0 854 + #define L1IMUPCIE0_BASE__INST6_SEG5 0 855 + 856 + #define L2IMU0_BASE__INST0_SEG0 0x00007DC0 857 + #define L2IMU0_BASE__INST0_SEG1 0x00900000 858 + #define L2IMU0_BASE__INST0_SEG2 0x02407000 859 + #define L2IMU0_BASE__INST0_SEG3 0x04FC0000 860 + #define L2IMU0_BASE__INST0_SEG4 0x055C0000 861 + #define L2IMU0_BASE__INST0_SEG5 0 862 + 863 + #define L2IMU0_BASE__INST1_SEG0 0 864 + #define L2IMU0_BASE__INST1_SEG1 0 865 + #define L2IMU0_BASE__INST1_SEG2 0 866 + #define L2IMU0_BASE__INST1_SEG3 0 867 + #define L2IMU0_BASE__INST1_SEG4 0 868 + #define L2IMU0_BASE__INST1_SEG5 0 869 + 870 + #define L2IMU0_BASE__INST2_SEG0 0 871 + #define L2IMU0_BASE__INST2_SEG1 0 872 + #define L2IMU0_BASE__INST2_SEG2 0 873 + #define L2IMU0_BASE__INST2_SEG3 0 874 + #define L2IMU0_BASE__INST2_SEG4 0 875 + #define L2IMU0_BASE__INST2_SEG5 0 876 + 877 + #define L2IMU0_BASE__INST3_SEG0 0 878 + #define L2IMU0_BASE__INST3_SEG1 0 879 + #define L2IMU0_BASE__INST3_SEG2 0 880 + #define L2IMU0_BASE__INST3_SEG3 0 881 + #define L2IMU0_BASE__INST3_SEG4 0 882 + #define L2IMU0_BASE__INST3_SEG5 0 883 + 884 + #define L2IMU0_BASE__INST4_SEG0 0 885 + #define L2IMU0_BASE__INST4_SEG1 0 886 + #define L2IMU0_BASE__INST4_SEG2 0 887 + #define L2IMU0_BASE__INST4_SEG3 0 888 + #define L2IMU0_BASE__INST4_SEG4 0 889 + #define L2IMU0_BASE__INST4_SEG5 0 890 + 891 + #define L2IMU0_BASE__INST5_SEG0 0 892 + #define L2IMU0_BASE__INST5_SEG1 0 893 + #define L2IMU0_BASE__INST5_SEG2 0 894 + #define L2IMU0_BASE__INST5_SEG3 0 895 + #define L2IMU0_BASE__INST5_SEG4 0 896 + #define L2IMU0_BASE__INST5_SEG5 0 897 + 898 + #define L2IMU0_BASE__INST6_SEG0 0 899 + #define L2IMU0_BASE__INST6_SEG1 0 900 + #define L2IMU0_BASE__INST6_SEG2 0 901 + #define L2IMU0_BASE__INST6_SEG3 0 902 + #define L2IMU0_BASE__INST6_SEG4 0 903 + #define L2IMU0_BASE__INST6_SEG5 0 904 + 905 + #define MMHUB_BASE__INST0_SEG0 0x0001A000 906 + #define MMHUB_BASE__INST0_SEG1 0x02408800 907 + #define MMHUB_BASE__INST0_SEG2 0 908 + #define MMHUB_BASE__INST0_SEG3 0 909 + #define MMHUB_BASE__INST0_SEG4 0 910 + #define MMHUB_BASE__INST0_SEG5 0 911 + 912 + #define MMHUB_BASE__INST1_SEG0 0 913 + #define MMHUB_BASE__INST1_SEG1 0 914 + #define MMHUB_BASE__INST1_SEG2 0 915 + #define MMHUB_BASE__INST1_SEG3 0 916 + #define MMHUB_BASE__INST1_SEG4 0 917 + #define MMHUB_BASE__INST1_SEG5 0 918 + 919 + #define MMHUB_BASE__INST2_SEG0 0 920 + #define MMHUB_BASE__INST2_SEG1 0 921 + #define MMHUB_BASE__INST2_SEG2 0 922 + #define MMHUB_BASE__INST2_SEG3 0 923 + #define MMHUB_BASE__INST2_SEG4 0 924 + #define MMHUB_BASE__INST2_SEG5 0 925 + 926 + #define MMHUB_BASE__INST3_SEG0 0 927 + #define MMHUB_BASE__INST3_SEG1 0 928 + #define MMHUB_BASE__INST3_SEG2 0 929 + #define MMHUB_BASE__INST3_SEG3 0 930 + #define MMHUB_BASE__INST3_SEG4 0 931 + #define MMHUB_BASE__INST3_SEG5 0 932 + 933 + #define MMHUB_BASE__INST4_SEG0 0 934 + #define MMHUB_BASE__INST4_SEG1 0 935 + #define MMHUB_BASE__INST4_SEG2 0 936 + #define MMHUB_BASE__INST4_SEG3 0 937 + #define MMHUB_BASE__INST4_SEG4 0 938 + #define MMHUB_BASE__INST4_SEG5 0 939 + 940 + #define MMHUB_BASE__INST5_SEG0 0 941 + #define MMHUB_BASE__INST5_SEG1 0 942 + #define MMHUB_BASE__INST5_SEG2 0 943 + #define MMHUB_BASE__INST5_SEG3 0 944 + #define MMHUB_BASE__INST5_SEG4 0 945 + #define MMHUB_BASE__INST5_SEG5 0 946 + 947 + #define MMHUB_BASE__INST6_SEG0 0 948 + #define MMHUB_BASE__INST6_SEG1 0 949 + #define MMHUB_BASE__INST6_SEG2 0 950 + #define MMHUB_BASE__INST6_SEG3 0 951 + #define MMHUB_BASE__INST6_SEG4 0 952 + #define MMHUB_BASE__INST6_SEG5 0 953 + 954 + #define MP0_BASE__INST0_SEG0 0x00016000 955 + #define MP0_BASE__INST0_SEG1 0x00DC0000 956 + #define MP0_BASE__INST0_SEG2 0x00E00000 957 + #define MP0_BASE__INST0_SEG3 0x00E40000 958 + #define MP0_BASE__INST0_SEG4 0x0243FC00 959 + #define MP0_BASE__INST0_SEG5 0 960 + 961 + #define MP0_BASE__INST1_SEG0 0 962 + #define MP0_BASE__INST1_SEG1 0 963 + #define MP0_BASE__INST1_SEG2 0 964 + #define MP0_BASE__INST1_SEG3 0 965 + #define MP0_BASE__INST1_SEG4 0 966 + #define MP0_BASE__INST1_SEG5 0 967 + 968 + #define MP0_BASE__INST2_SEG0 0 969 + #define MP0_BASE__INST2_SEG1 0 970 + #define MP0_BASE__INST2_SEG2 0 971 + #define MP0_BASE__INST2_SEG3 0 972 + #define MP0_BASE__INST2_SEG4 0 973 + #define MP0_BASE__INST2_SEG5 0 974 + 975 + #define MP0_BASE__INST3_SEG0 0 976 + #define MP0_BASE__INST3_SEG1 0 977 + #define MP0_BASE__INST3_SEG2 0 978 + #define MP0_BASE__INST3_SEG3 0 979 + #define MP0_BASE__INST3_SEG4 0 980 + #define MP0_BASE__INST3_SEG5 0 981 + 982 + #define MP0_BASE__INST4_SEG0 0 983 + #define MP0_BASE__INST4_SEG1 0 984 + #define MP0_BASE__INST4_SEG2 0 985 + #define MP0_BASE__INST4_SEG3 0 986 + #define MP0_BASE__INST4_SEG4 0 987 + #define MP0_BASE__INST4_SEG5 0 988 + 989 + #define MP0_BASE__INST5_SEG0 0 990 + #define MP0_BASE__INST5_SEG1 0 991 + #define MP0_BASE__INST5_SEG2 0 992 + #define MP0_BASE__INST5_SEG3 0 993 + #define MP0_BASE__INST5_SEG4 0 994 + #define MP0_BASE__INST5_SEG5 0 995 + 996 + #define MP0_BASE__INST6_SEG0 0 997 + #define MP0_BASE__INST6_SEG1 0 998 + #define MP0_BASE__INST6_SEG2 0 999 + #define MP0_BASE__INST6_SEG3 0 1000 + #define MP0_BASE__INST6_SEG4 0 1001 + #define MP0_BASE__INST6_SEG5 0 1002 + 1003 + #define MP1_BASE__INST0_SEG0 0x00016000 1004 + #define MP1_BASE__INST0_SEG1 0x00DC0000 1005 + #define MP1_BASE__INST0_SEG2 0x00E00000 1006 + #define MP1_BASE__INST0_SEG3 0x00E40000 1007 + #define MP1_BASE__INST0_SEG4 0x0243FC00 1008 + #define MP1_BASE__INST0_SEG5 0 1009 + 1010 + #define MP1_BASE__INST1_SEG0 0 1011 + #define MP1_BASE__INST1_SEG1 0 1012 + #define MP1_BASE__INST1_SEG2 0 1013 + #define MP1_BASE__INST1_SEG3 0 1014 + #define MP1_BASE__INST1_SEG4 0 1015 + #define MP1_BASE__INST1_SEG5 0 1016 + 1017 + #define MP1_BASE__INST2_SEG0 0 1018 + #define MP1_BASE__INST2_SEG1 0 1019 + #define MP1_BASE__INST2_SEG2 0 1020 + #define MP1_BASE__INST2_SEG3 0 1021 + #define MP1_BASE__INST2_SEG4 0 1022 + #define MP1_BASE__INST2_SEG5 0 1023 + 1024 + #define MP1_BASE__INST3_SEG0 0 1025 + #define MP1_BASE__INST3_SEG1 0 1026 + #define MP1_BASE__INST3_SEG2 0 1027 + #define MP1_BASE__INST3_SEG3 0 1028 + #define MP1_BASE__INST3_SEG4 0 1029 + #define MP1_BASE__INST3_SEG5 0 1030 + 1031 + #define MP1_BASE__INST4_SEG0 0 1032 + #define MP1_BASE__INST4_SEG1 0 1033 + #define MP1_BASE__INST4_SEG2 0 1034 + #define MP1_BASE__INST4_SEG3 0 1035 + #define MP1_BASE__INST4_SEG4 0 1036 + #define MP1_BASE__INST4_SEG5 0 1037 + 1038 + #define MP1_BASE__INST5_SEG0 0 1039 + #define MP1_BASE__INST5_SEG1 0 1040 + #define MP1_BASE__INST5_SEG2 0 1041 + #define MP1_BASE__INST5_SEG3 0 1042 + #define MP1_BASE__INST5_SEG4 0 1043 + #define MP1_BASE__INST5_SEG5 0 1044 + 1045 + #define MP1_BASE__INST6_SEG0 0 1046 + #define MP1_BASE__INST6_SEG1 0 1047 + #define MP1_BASE__INST6_SEG2 0 1048 + #define MP1_BASE__INST6_SEG3 0 1049 + #define MP1_BASE__INST6_SEG4 0 1050 + #define MP1_BASE__INST6_SEG5 0 1051 + 1052 + #define NBIO_BASE__INST0_SEG0 0x00000000 1053 + #define NBIO_BASE__INST0_SEG1 0x00000014 1054 + #define NBIO_BASE__INST0_SEG2 0x00000D20 1055 + #define NBIO_BASE__INST0_SEG3 0x00010400 1056 + #define NBIO_BASE__INST0_SEG4 0x0241B000 1057 + #define NBIO_BASE__INST0_SEG5 0x04040000 1058 + 1059 + #define NBIO_BASE__INST1_SEG0 0 1060 + #define NBIO_BASE__INST1_SEG1 0 1061 + #define NBIO_BASE__INST1_SEG2 0 1062 + #define NBIO_BASE__INST1_SEG3 0 1063 + #define NBIO_BASE__INST1_SEG4 0 1064 + #define NBIO_BASE__INST1_SEG5 0 1065 + 1066 + #define NBIO_BASE__INST2_SEG0 0 1067 + #define NBIO_BASE__INST2_SEG1 0 1068 + #define NBIO_BASE__INST2_SEG2 0 1069 + #define NBIO_BASE__INST2_SEG3 0 1070 + #define NBIO_BASE__INST2_SEG4 0 1071 + #define NBIO_BASE__INST2_SEG5 0 1072 + 1073 + #define NBIO_BASE__INST3_SEG0 0 1074 + #define NBIO_BASE__INST3_SEG1 0 1075 + #define NBIO_BASE__INST3_SEG2 0 1076 + #define NBIO_BASE__INST3_SEG3 0 1077 + #define NBIO_BASE__INST3_SEG4 0 1078 + #define NBIO_BASE__INST3_SEG5 0 1079 + 1080 + #define NBIO_BASE__INST4_SEG0 0 1081 + #define NBIO_BASE__INST4_SEG1 0 1082 + #define NBIO_BASE__INST4_SEG2 0 1083 + #define NBIO_BASE__INST4_SEG3 0 1084 + #define NBIO_BASE__INST4_SEG4 0 1085 + #define NBIO_BASE__INST4_SEG5 0 1086 + 1087 + #define NBIO_BASE__INST5_SEG0 0 1088 + #define NBIO_BASE__INST5_SEG1 0 1089 + #define NBIO_BASE__INST5_SEG2 0 1090 + #define NBIO_BASE__INST5_SEG3 0 1091 + #define NBIO_BASE__INST5_SEG4 0 1092 + #define NBIO_BASE__INST5_SEG5 0 1093 + 1094 + #define NBIO_BASE__INST6_SEG0 0 1095 + #define NBIO_BASE__INST6_SEG1 0 1096 + #define NBIO_BASE__INST6_SEG2 0 1097 + #define NBIO_BASE__INST6_SEG3 0 1098 + #define NBIO_BASE__INST6_SEG4 0 1099 + #define NBIO_BASE__INST6_SEG5 0 1100 + 1101 + #define OSSSYS_BASE__INST0_SEG0 0x000010A0 1102 + #define OSSSYS_BASE__INST0_SEG1 0x0240A000 1103 + #define OSSSYS_BASE__INST0_SEG2 0 1104 + #define OSSSYS_BASE__INST0_SEG3 0 1105 + #define OSSSYS_BASE__INST0_SEG4 0 1106 + #define OSSSYS_BASE__INST0_SEG5 0 1107 + 1108 + #define OSSSYS_BASE__INST1_SEG0 0 1109 + #define OSSSYS_BASE__INST1_SEG1 0 1110 + #define OSSSYS_BASE__INST1_SEG2 0 1111 + #define OSSSYS_BASE__INST1_SEG3 0 1112 + #define OSSSYS_BASE__INST1_SEG4 0 1113 + #define OSSSYS_BASE__INST1_SEG5 0 1114 + 1115 + #define OSSSYS_BASE__INST2_SEG0 0 1116 + #define OSSSYS_BASE__INST2_SEG1 0 1117 + #define OSSSYS_BASE__INST2_SEG2 0 1118 + #define OSSSYS_BASE__INST2_SEG3 0 1119 + #define OSSSYS_BASE__INST2_SEG4 0 1120 + #define OSSSYS_BASE__INST2_SEG5 0 1121 + 1122 + #define OSSSYS_BASE__INST3_SEG0 0 1123 + #define OSSSYS_BASE__INST3_SEG1 0 1124 + #define OSSSYS_BASE__INST3_SEG2 0 1125 + #define OSSSYS_BASE__INST3_SEG3 0 1126 + #define OSSSYS_BASE__INST3_SEG4 0 1127 + #define OSSSYS_BASE__INST3_SEG5 0 1128 + 1129 + #define OSSSYS_BASE__INST4_SEG0 0 1130 + #define OSSSYS_BASE__INST4_SEG1 0 1131 + #define OSSSYS_BASE__INST4_SEG2 0 1132 + #define OSSSYS_BASE__INST4_SEG3 0 1133 + #define OSSSYS_BASE__INST4_SEG4 0 1134 + #define OSSSYS_BASE__INST4_SEG5 0 1135 + 1136 + #define OSSSYS_BASE__INST5_SEG0 0 1137 + #define OSSSYS_BASE__INST5_SEG1 0 1138 + #define OSSSYS_BASE__INST5_SEG2 0 1139 + #define OSSSYS_BASE__INST5_SEG3 0 1140 + #define OSSSYS_BASE__INST5_SEG4 0 1141 + #define OSSSYS_BASE__INST5_SEG5 0 1142 + 1143 + #define OSSSYS_BASE__INST6_SEG0 0 1144 + #define OSSSYS_BASE__INST6_SEG1 0 1145 + #define OSSSYS_BASE__INST6_SEG2 0 1146 + #define OSSSYS_BASE__INST6_SEG3 0 1147 + #define OSSSYS_BASE__INST6_SEG4 0 1148 + #define OSSSYS_BASE__INST6_SEG5 0 1149 + 1150 + #define PCIE0_BASE__INST0_SEG0 0x02411800 1151 + #define PCIE0_BASE__INST0_SEG1 0x04440000 1152 + #define PCIE0_BASE__INST0_SEG2 0 1153 + #define PCIE0_BASE__INST0_SEG3 0 1154 + #define PCIE0_BASE__INST0_SEG4 0 1155 + #define PCIE0_BASE__INST0_SEG5 0 1156 + 1157 + #define PCIE0_BASE__INST1_SEG0 0 1158 + #define PCIE0_BASE__INST1_SEG1 0 1159 + #define PCIE0_BASE__INST1_SEG2 0 1160 + #define PCIE0_BASE__INST1_SEG3 0 1161 + #define PCIE0_BASE__INST1_SEG4 0 1162 + #define PCIE0_BASE__INST1_SEG5 0 1163 + 1164 + #define PCIE0_BASE__INST2_SEG0 0 1165 + #define PCIE0_BASE__INST2_SEG1 0 1166 + #define PCIE0_BASE__INST2_SEG2 0 1167 + #define PCIE0_BASE__INST2_SEG3 0 1168 + #define PCIE0_BASE__INST2_SEG4 0 1169 + #define PCIE0_BASE__INST2_SEG5 0 1170 + 1171 + #define PCIE0_BASE__INST3_SEG0 0 1172 + #define PCIE0_BASE__INST3_SEG1 0 1173 + #define PCIE0_BASE__INST3_SEG2 0 1174 + #define PCIE0_BASE__INST3_SEG3 0 1175 + #define PCIE0_BASE__INST3_SEG4 0 1176 + #define PCIE0_BASE__INST3_SEG5 0 1177 + 1178 + #define PCIE0_BASE__INST4_SEG0 0 1179 + #define PCIE0_BASE__INST4_SEG1 0 1180 + #define PCIE0_BASE__INST4_SEG2 0 1181 + #define PCIE0_BASE__INST4_SEG3 0 1182 + #define PCIE0_BASE__INST4_SEG4 0 1183 + #define PCIE0_BASE__INST4_SEG5 0 1184 + 1185 + #define PCIE0_BASE__INST5_SEG0 0 1186 + #define PCIE0_BASE__INST5_SEG1 0 1187 + #define PCIE0_BASE__INST5_SEG2 0 1188 + #define PCIE0_BASE__INST5_SEG3 0 1189 + #define PCIE0_BASE__INST5_SEG4 0 1190 + #define PCIE0_BASE__INST5_SEG5 0 1191 + 1192 + #define PCIE0_BASE__INST6_SEG0 0 1193 + #define PCIE0_BASE__INST6_SEG1 0 1194 + #define PCIE0_BASE__INST6_SEG2 0 1195 + #define PCIE0_BASE__INST6_SEG3 0 1196 + #define PCIE0_BASE__INST6_SEG4 0 1197 + #define PCIE0_BASE__INST6_SEG5 0 1198 + 1199 + #define SDMA0_BASE__INST0_SEG0 0x00001260 1200 + #define SDMA0_BASE__INST0_SEG1 0x02445400 1201 + #define SDMA0_BASE__INST0_SEG2 0 1202 + #define SDMA0_BASE__INST0_SEG3 0 1203 + #define SDMA0_BASE__INST0_SEG4 0 1204 + #define SDMA0_BASE__INST0_SEG5 0 1205 + 1206 + #define SDMA0_BASE__INST1_SEG0 0 1207 + #define SDMA0_BASE__INST1_SEG1 0 1208 + #define SDMA0_BASE__INST1_SEG2 0 1209 + #define SDMA0_BASE__INST1_SEG3 0 1210 + #define SDMA0_BASE__INST1_SEG4 0 1211 + #define SDMA0_BASE__INST1_SEG5 0 1212 + 1213 + #define SDMA0_BASE__INST2_SEG0 0 1214 + #define SDMA0_BASE__INST2_SEG1 0 1215 + #define SDMA0_BASE__INST2_SEG2 0 1216 + #define SDMA0_BASE__INST2_SEG3 0 1217 + #define SDMA0_BASE__INST2_SEG4 0 1218 + #define SDMA0_BASE__INST2_SEG5 0 1219 + 1220 + #define SDMA0_BASE__INST3_SEG0 0 1221 + #define SDMA0_BASE__INST3_SEG1 0 1222 + #define SDMA0_BASE__INST3_SEG2 0 1223 + #define SDMA0_BASE__INST3_SEG3 0 1224 + #define SDMA0_BASE__INST3_SEG4 0 1225 + #define SDMA0_BASE__INST3_SEG5 0 1226 + 1227 + #define SDMA0_BASE__INST4_SEG0 0 1228 + #define SDMA0_BASE__INST4_SEG1 0 1229 + #define SDMA0_BASE__INST4_SEG2 0 1230 + #define SDMA0_BASE__INST4_SEG3 0 1231 + #define SDMA0_BASE__INST4_SEG4 0 1232 + #define SDMA0_BASE__INST4_SEG5 0 1233 + 1234 + #define SDMA0_BASE__INST5_SEG0 0 1235 + #define SDMA0_BASE__INST5_SEG1 0 1236 + #define SDMA0_BASE__INST5_SEG2 0 1237 + #define SDMA0_BASE__INST5_SEG3 0 1238 + #define SDMA0_BASE__INST5_SEG4 0 1239 + #define SDMA0_BASE__INST5_SEG5 0 1240 + 1241 + #define SDMA0_BASE__INST6_SEG0 0 1242 + #define SDMA0_BASE__INST6_SEG1 0 1243 + #define SDMA0_BASE__INST6_SEG2 0 1244 + #define SDMA0_BASE__INST6_SEG3 0 1245 + #define SDMA0_BASE__INST6_SEG4 0 1246 + #define SDMA0_BASE__INST6_SEG5 0 1247 + 1248 + #define SDMA1_BASE__INST0_SEG0 0x00001860 1249 + #define SDMA1_BASE__INST0_SEG1 0x02445800 1250 + #define SDMA1_BASE__INST0_SEG2 0 1251 + #define SDMA1_BASE__INST0_SEG3 0 1252 + #define SDMA1_BASE__INST0_SEG4 0 1253 + #define SDMA1_BASE__INST0_SEG5 0 1254 + 1255 + #define SDMA1_BASE__INST1_SEG0 0x0001E000 1256 + #define SDMA1_BASE__INST1_SEG1 0x02446400 1257 + #define SDMA1_BASE__INST1_SEG2 0 1258 + #define SDMA1_BASE__INST1_SEG3 0 1259 + #define SDMA1_BASE__INST1_SEG4 0 1260 + #define SDMA1_BASE__INST1_SEG5 0 1261 + 1262 + #define SDMA1_BASE__INST2_SEG0 0x0001E400 1263 + #define SDMA1_BASE__INST2_SEG1 0x02446800 1264 + #define SDMA1_BASE__INST2_SEG2 0 1265 + #define SDMA1_BASE__INST2_SEG3 0 1266 + #define SDMA1_BASE__INST2_SEG4 0 1267 + #define SDMA1_BASE__INST2_SEG5 0 1268 + 1269 + #define SDMA1_BASE__INST3_SEG0 0x0001E800 1270 + #define SDMA1_BASE__INST3_SEG1 0x02446C00 1271 + #define SDMA1_BASE__INST3_SEG2 0 1272 + #define SDMA1_BASE__INST3_SEG3 0 1273 + #define SDMA1_BASE__INST3_SEG4 0 1274 + #define SDMA1_BASE__INST3_SEG5 0 1275 + 1276 + #define SDMA1_BASE__INST4_SEG0 0 1277 + #define SDMA1_BASE__INST4_SEG1 0 1278 + #define SDMA1_BASE__INST4_SEG2 0 1279 + #define SDMA1_BASE__INST4_SEG3 0 1280 + #define SDMA1_BASE__INST4_SEG4 0 1281 + #define SDMA1_BASE__INST4_SEG5 0 1282 + 1283 + #define SDMA1_BASE__INST5_SEG0 0 1284 + #define SDMA1_BASE__INST5_SEG1 0 1285 + #define SDMA1_BASE__INST5_SEG2 0 1286 + #define SDMA1_BASE__INST5_SEG3 0 1287 + #define SDMA1_BASE__INST5_SEG4 0 1288 + #define SDMA1_BASE__INST5_SEG5 0 1289 + 1290 + #define SDMA1_BASE__INST6_SEG0 0 1291 + #define SDMA1_BASE__INST6_SEG1 0 1292 + #define SDMA1_BASE__INST6_SEG2 0 1293 + #define SDMA1_BASE__INST6_SEG3 0 1294 + #define SDMA1_BASE__INST6_SEG4 0 1295 + #define SDMA1_BASE__INST6_SEG5 0 1296 + 1297 + #define SMUIO_BASE__INST0_SEG0 0x00016800 1298 + #define SMUIO_BASE__INST0_SEG1 0x00016A00 1299 + #define SMUIO_BASE__INST0_SEG2 0x02401000 1300 + #define SMUIO_BASE__INST0_SEG3 0x03440000 1301 + #define SMUIO_BASE__INST0_SEG4 0 1302 + #define SMUIO_BASE__INST0_SEG5 0 1303 + 1304 + #define SMUIO_BASE__INST1_SEG0 0 1305 + #define SMUIO_BASE__INST1_SEG1 0 1306 + #define SMUIO_BASE__INST1_SEG2 0 1307 + #define SMUIO_BASE__INST1_SEG3 0 1308 + #define SMUIO_BASE__INST1_SEG4 0 1309 + #define SMUIO_BASE__INST1_SEG5 0 1310 + 1311 + #define SMUIO_BASE__INST2_SEG0 0 1312 + #define SMUIO_BASE__INST2_SEG1 0 1313 + #define SMUIO_BASE__INST2_SEG2 0 1314 + #define SMUIO_BASE__INST2_SEG3 0 1315 + #define SMUIO_BASE__INST2_SEG4 0 1316 + #define SMUIO_BASE__INST2_SEG5 0 1317 + 1318 + #define SMUIO_BASE__INST3_SEG0 0 1319 + #define SMUIO_BASE__INST3_SEG1 0 1320 + #define SMUIO_BASE__INST3_SEG2 0 1321 + #define SMUIO_BASE__INST3_SEG3 0 1322 + #define SMUIO_BASE__INST3_SEG4 0 1323 + #define SMUIO_BASE__INST3_SEG5 0 1324 + 1325 + #define SMUIO_BASE__INST4_SEG0 0 1326 + #define SMUIO_BASE__INST4_SEG1 0 1327 + #define SMUIO_BASE__INST4_SEG2 0 1328 + #define SMUIO_BASE__INST4_SEG3 0 1329 + #define SMUIO_BASE__INST4_SEG4 0 1330 + #define SMUIO_BASE__INST4_SEG5 0 1331 + 1332 + #define SMUIO_BASE__INST5_SEG0 0 1333 + #define SMUIO_BASE__INST5_SEG1 0 1334 + #define SMUIO_BASE__INST5_SEG2 0 1335 + #define SMUIO_BASE__INST5_SEG3 0 1336 + #define SMUIO_BASE__INST5_SEG4 0 1337 + #define SMUIO_BASE__INST5_SEG5 0 1338 + 1339 + #define SMUIO_BASE__INST6_SEG0 0 1340 + #define SMUIO_BASE__INST6_SEG1 0 1341 + #define SMUIO_BASE__INST6_SEG2 0 1342 + #define SMUIO_BASE__INST6_SEG3 0 1343 + #define SMUIO_BASE__INST6_SEG4 0 1344 + #define SMUIO_BASE__INST6_SEG5 0 1345 + 1346 + #define THM_BASE__INST0_SEG0 0x00016600 1347 + #define THM_BASE__INST0_SEG1 0x02400C00 1348 + #define THM_BASE__INST0_SEG2 0 1349 + #define THM_BASE__INST0_SEG3 0 1350 + #define THM_BASE__INST0_SEG4 0 1351 + #define THM_BASE__INST0_SEG5 0 1352 + 1353 + #define THM_BASE__INST1_SEG0 0 1354 + #define THM_BASE__INST1_SEG1 0 1355 + #define THM_BASE__INST1_SEG2 0 1356 + #define THM_BASE__INST1_SEG3 0 1357 + #define THM_BASE__INST1_SEG4 0 1358 + #define THM_BASE__INST1_SEG5 0 1359 + 1360 + #define THM_BASE__INST2_SEG0 0 1361 + #define THM_BASE__INST2_SEG1 0 1362 + #define THM_BASE__INST2_SEG2 0 1363 + #define THM_BASE__INST2_SEG3 0 1364 + #define THM_BASE__INST2_SEG4 0 1365 + #define THM_BASE__INST2_SEG5 0 1366 + 1367 + #define THM_BASE__INST3_SEG0 0 1368 + #define THM_BASE__INST3_SEG1 0 1369 + #define THM_BASE__INST3_SEG2 0 1370 + #define THM_BASE__INST3_SEG3 0 1371 + #define THM_BASE__INST3_SEG4 0 1372 + #define THM_BASE__INST3_SEG5 0 1373 + 1374 + #define THM_BASE__INST4_SEG0 0 1375 + #define THM_BASE__INST4_SEG1 0 1376 + #define THM_BASE__INST4_SEG2 0 1377 + #define THM_BASE__INST4_SEG3 0 1378 + #define THM_BASE__INST4_SEG4 0 1379 + #define THM_BASE__INST4_SEG5 0 1380 + 1381 + #define THM_BASE__INST5_SEG0 0 1382 + #define THM_BASE__INST5_SEG1 0 1383 + #define THM_BASE__INST5_SEG2 0 1384 + #define THM_BASE__INST5_SEG3 0 1385 + #define THM_BASE__INST5_SEG4 0 1386 + #define THM_BASE__INST5_SEG5 0 1387 + 1388 + #define THM_BASE__INST6_SEG0 0 1389 + #define THM_BASE__INST6_SEG1 0 1390 + #define THM_BASE__INST6_SEG2 0 1391 + #define THM_BASE__INST6_SEG3 0 1392 + #define THM_BASE__INST6_SEG4 0 1393 + #define THM_BASE__INST6_SEG5 0 1394 + 1395 + #define UMC_BASE__INST0_SEG0 0x00014000 1396 + #define UMC_BASE__INST0_SEG1 0x00054000 1397 + #define UMC_BASE__INST0_SEG2 0x02425800 1398 + #define UMC_BASE__INST0_SEG3 0 1399 + #define UMC_BASE__INST0_SEG4 0 1400 + #define UMC_BASE__INST0_SEG5 0 1401 + 1402 + #define UMC_BASE__INST1_SEG0 0x00094000 1403 + #define UMC_BASE__INST1_SEG1 0x000D4000 1404 + #define UMC_BASE__INST1_SEG2 0x02425C00 1405 + #define UMC_BASE__INST1_SEG3 0 1406 + #define UMC_BASE__INST1_SEG4 0 1407 + #define UMC_BASE__INST1_SEG5 0 1408 + 1409 + #define UMC_BASE__INST2_SEG0 0x00114000 1410 + #define UMC_BASE__INST2_SEG1 0x00154000 1411 + #define UMC_BASE__INST2_SEG2 0x02426000 1412 + #define UMC_BASE__INST2_SEG3 0 1413 + #define UMC_BASE__INST2_SEG4 0 1414 + #define UMC_BASE__INST2_SEG5 0 1415 + 1416 + #define UMC_BASE__INST3_SEG0 0x00194000 1417 + #define UMC_BASE__INST3_SEG1 0x001D4000 1418 + #define UMC_BASE__INST3_SEG2 0x02426400 1419 + #define UMC_BASE__INST3_SEG3 0 1420 + #define UMC_BASE__INST3_SEG4 0 1421 + #define UMC_BASE__INST3_SEG5 0 1422 + 1423 + #define UMC_BASE__INST4_SEG0 0 1424 + #define UMC_BASE__INST4_SEG1 0 1425 + #define UMC_BASE__INST4_SEG2 0 1426 + #define UMC_BASE__INST4_SEG3 0 1427 + #define UMC_BASE__INST4_SEG4 0 1428 + #define UMC_BASE__INST4_SEG5 0 1429 + 1430 + #define UMC_BASE__INST5_SEG0 0 1431 + #define UMC_BASE__INST5_SEG1 0 1432 + #define UMC_BASE__INST5_SEG2 0 1433 + #define UMC_BASE__INST5_SEG3 0 1434 + #define UMC_BASE__INST5_SEG4 0 1435 + #define UMC_BASE__INST5_SEG5 0 1436 + 1437 + #define UMC_BASE__INST6_SEG0 0 1438 + #define UMC_BASE__INST6_SEG1 0 1439 + #define UMC_BASE__INST6_SEG2 0 1440 + #define UMC_BASE__INST6_SEG3 0 1441 + #define UMC_BASE__INST6_SEG4 0 1442 + #define UMC_BASE__INST6_SEG5 0 1443 + 1444 + #define VCN_BASE__INST0_SEG0 0x00007800 1445 + #define VCN_BASE__INST0_SEG1 0x00007E00 1446 + #define VCN_BASE__INST0_SEG2 0x02403000 1447 + #define VCN_BASE__INST0_SEG3 0 1448 + #define VCN_BASE__INST0_SEG4 0 1449 + #define VCN_BASE__INST0_SEG5 0 1450 + 1451 + #define VCN_BASE__INST1_SEG0 0x00007A00 1452 + #define VCN_BASE__INST1_SEG1 0x00009000 1453 + #define VCN_BASE__INST1_SEG2 0x02445000 1454 + #define VCN_BASE__INST1_SEG3 0 1455 + #define VCN_BASE__INST1_SEG4 0 1456 + #define VCN_BASE__INST1_SEG5 0 1457 + 1458 + #define VCN_BASE__INST2_SEG0 0 1459 + #define VCN_BASE__INST2_SEG1 0 1460 + #define VCN_BASE__INST2_SEG2 0 1461 + #define VCN_BASE__INST2_SEG3 0 1462 + #define VCN_BASE__INST2_SEG4 0 1463 + #define VCN_BASE__INST2_SEG5 0 1464 + 1465 + #define VCN_BASE__INST3_SEG0 0 1466 + #define VCN_BASE__INST3_SEG1 0 1467 + #define VCN_BASE__INST3_SEG2 0 1468 + #define VCN_BASE__INST3_SEG3 0 1469 + #define VCN_BASE__INST3_SEG4 0 1470 + #define VCN_BASE__INST3_SEG5 0 1471 + 1472 + #define VCN_BASE__INST4_SEG0 0 1473 + #define VCN_BASE__INST4_SEG1 0 1474 + #define VCN_BASE__INST4_SEG2 0 1475 + #define VCN_BASE__INST4_SEG3 0 1476 + #define VCN_BASE__INST4_SEG4 0 1477 + #define VCN_BASE__INST4_SEG5 0 1478 + 1479 + #define VCN_BASE__INST5_SEG0 0 1480 + #define VCN_BASE__INST5_SEG1 0 1481 + #define VCN_BASE__INST5_SEG2 0 1482 + #define VCN_BASE__INST5_SEG3 0 1483 + #define VCN_BASE__INST5_SEG4 0 1484 + #define VCN_BASE__INST5_SEG5 0 1485 + 1486 + #define VCN_BASE__INST6_SEG0 0 1487 + #define VCN_BASE__INST6_SEG1 0 1488 + #define VCN_BASE__INST6_SEG2 0 1489 + #define VCN_BASE__INST6_SEG3 0 1490 + #define VCN_BASE__INST6_SEG4 0 1491 + #define VCN_BASE__INST6_SEG5 0 1492 + 1493 + #define WAFL0_BASE__INST0_SEG0 0x02438000 1494 + #define WAFL0_BASE__INST0_SEG1 0x04880000 1495 + #define WAFL0_BASE__INST0_SEG2 0 1496 + #define WAFL0_BASE__INST0_SEG3 0 1497 + #define WAFL0_BASE__INST0_SEG4 0 1498 + #define WAFL0_BASE__INST0_SEG5 0 1499 + 1500 + #define WAFL0_BASE__INST1_SEG0 0 1501 + #define WAFL0_BASE__INST1_SEG1 0 1502 + #define WAFL0_BASE__INST1_SEG2 0 1503 + #define WAFL0_BASE__INST1_SEG3 0 1504 + #define WAFL0_BASE__INST1_SEG4 0 1505 + #define WAFL0_BASE__INST1_SEG5 0 1506 + 1507 + #define WAFL0_BASE__INST2_SEG0 0 1508 + #define WAFL0_BASE__INST2_SEG1 0 1509 + #define WAFL0_BASE__INST2_SEG2 0 1510 + #define WAFL0_BASE__INST2_SEG3 0 1511 + #define WAFL0_BASE__INST2_SEG4 0 1512 + #define WAFL0_BASE__INST2_SEG5 0 1513 + 1514 + #define WAFL0_BASE__INST3_SEG0 0 1515 + #define WAFL0_BASE__INST3_SEG1 0 1516 + #define WAFL0_BASE__INST3_SEG2 0 1517 + #define WAFL0_BASE__INST3_SEG3 0 1518 + #define WAFL0_BASE__INST3_SEG4 0 1519 + #define WAFL0_BASE__INST3_SEG5 0 1520 + 1521 + #define WAFL0_BASE__INST4_SEG0 0 1522 + #define WAFL0_BASE__INST4_SEG1 0 1523 + #define WAFL0_BASE__INST4_SEG2 0 1524 + #define WAFL0_BASE__INST4_SEG3 0 1525 + #define WAFL0_BASE__INST4_SEG4 0 1526 + #define WAFL0_BASE__INST4_SEG5 0 1527 + 1528 + #define WAFL0_BASE__INST5_SEG0 0 1529 + #define WAFL0_BASE__INST5_SEG1 0 1530 + #define WAFL0_BASE__INST5_SEG2 0 1531 + #define WAFL0_BASE__INST5_SEG3 0 1532 + #define WAFL0_BASE__INST5_SEG4 0 1533 + #define WAFL0_BASE__INST5_SEG5 0 1534 + 1535 + #define WAFL0_BASE__INST6_SEG0 0 1536 + #define WAFL0_BASE__INST6_SEG1 0 1537 + #define WAFL0_BASE__INST6_SEG2 0 1538 + #define WAFL0_BASE__INST6_SEG3 0 1539 + #define WAFL0_BASE__INST6_SEG4 0 1540 + #define WAFL0_BASE__INST6_SEG5 0 1541 + 1542 + #define WAFL1_BASE__INST0_SEG0 0 1543 + #define WAFL1_BASE__INST0_SEG1 0x01300000 1544 + #define WAFL1_BASE__INST0_SEG2 0x02410800 1545 + #define WAFL1_BASE__INST0_SEG3 0 1546 + #define WAFL1_BASE__INST0_SEG4 0 1547 + #define WAFL1_BASE__INST0_SEG5 0 1548 + 1549 + #define WAFL1_BASE__INST1_SEG0 0 1550 + #define WAFL1_BASE__INST1_SEG1 0 1551 + #define WAFL1_BASE__INST1_SEG2 0 1552 + #define WAFL1_BASE__INST1_SEG3 0 1553 + #define WAFL1_BASE__INST1_SEG4 0 1554 + #define WAFL1_BASE__INST1_SEG5 0 1555 + 1556 + #define WAFL1_BASE__INST2_SEG0 0 1557 + #define WAFL1_BASE__INST2_SEG1 0 1558 + #define WAFL1_BASE__INST2_SEG2 0 1559 + #define WAFL1_BASE__INST2_SEG3 0 1560 + #define WAFL1_BASE__INST2_SEG4 0 1561 + #define WAFL1_BASE__INST2_SEG5 0 1562 + 1563 + #define WAFL1_BASE__INST3_SEG0 0 1564 + #define WAFL1_BASE__INST3_SEG1 0 1565 + #define WAFL1_BASE__INST3_SEG2 0 1566 + #define WAFL1_BASE__INST3_SEG3 0 1567 + #define WAFL1_BASE__INST3_SEG4 0 1568 + #define WAFL1_BASE__INST3_SEG5 0 1569 + 1570 + #define WAFL1_BASE__INST4_SEG0 0 1571 + #define WAFL1_BASE__INST4_SEG1 0 1572 + #define WAFL1_BASE__INST4_SEG2 0 1573 + #define WAFL1_BASE__INST4_SEG3 0 1574 + #define WAFL1_BASE__INST4_SEG4 0 1575 + #define WAFL1_BASE__INST4_SEG5 0 1576 + 1577 + #define WAFL1_BASE__INST5_SEG0 0 1578 + #define WAFL1_BASE__INST5_SEG1 0 1579 + #define WAFL1_BASE__INST5_SEG2 0 1580 + #define WAFL1_BASE__INST5_SEG3 0 1581 + #define WAFL1_BASE__INST5_SEG4 0 1582 + #define WAFL1_BASE__INST5_SEG5 0 1583 + 1584 + #define WAFL1_BASE__INST6_SEG0 0 1585 + #define WAFL1_BASE__INST6_SEG1 0 1586 + #define WAFL1_BASE__INST6_SEG2 0 1587 + #define WAFL1_BASE__INST6_SEG3 0 1588 + #define WAFL1_BASE__INST6_SEG4 0 1589 + #define WAFL1_BASE__INST6_SEG5 0 1590 + 1591 + #define XGMI0_BASE__INST0_SEG0 0x02438C00 1592 + #define XGMI0_BASE__INST0_SEG1 0x04680000 1593 + #define XGMI0_BASE__INST0_SEG2 0x04940000 1594 + #define XGMI0_BASE__INST0_SEG3 0 1595 + #define XGMI0_BASE__INST0_SEG4 0 1596 + #define XGMI0_BASE__INST0_SEG5 0 1597 + 1598 + #define XGMI0_BASE__INST1_SEG0 0 1599 + #define XGMI0_BASE__INST1_SEG1 0 1600 + #define XGMI0_BASE__INST1_SEG2 0 1601 + #define XGMI0_BASE__INST1_SEG3 0 1602 + #define XGMI0_BASE__INST1_SEG4 0 1603 + #define XGMI0_BASE__INST1_SEG5 0 1604 + 1605 + #define XGMI0_BASE__INST2_SEG0 0 1606 + #define XGMI0_BASE__INST2_SEG1 0 1607 + #define XGMI0_BASE__INST2_SEG2 0 1608 + #define XGMI0_BASE__INST2_SEG3 0 1609 + #define XGMI0_BASE__INST2_SEG4 0 1610 + #define XGMI0_BASE__INST2_SEG5 0 1611 + 1612 + #define XGMI0_BASE__INST3_SEG0 0 1613 + #define XGMI0_BASE__INST3_SEG1 0 1614 + #define XGMI0_BASE__INST3_SEG2 0 1615 + #define XGMI0_BASE__INST3_SEG3 0 1616 + #define XGMI0_BASE__INST3_SEG4 0 1617 + #define XGMI0_BASE__INST3_SEG5 0 1618 + 1619 + #define XGMI0_BASE__INST4_SEG0 0 1620 + #define XGMI0_BASE__INST4_SEG1 0 1621 + #define XGMI0_BASE__INST4_SEG2 0 1622 + #define XGMI0_BASE__INST4_SEG3 0 1623 + #define XGMI0_BASE__INST4_SEG4 0 1624 + #define XGMI0_BASE__INST4_SEG5 0 1625 + 1626 + #define XGMI0_BASE__INST5_SEG0 0 1627 + #define XGMI0_BASE__INST5_SEG1 0 1628 + #define XGMI0_BASE__INST5_SEG2 0 1629 + #define XGMI0_BASE__INST5_SEG3 0 1630 + #define XGMI0_BASE__INST5_SEG4 0 1631 + #define XGMI0_BASE__INST5_SEG5 0 1632 + 1633 + #define XGMI0_BASE__INST6_SEG0 0 1634 + #define XGMI0_BASE__INST6_SEG1 0 1635 + #define XGMI0_BASE__INST6_SEG2 0 1636 + #define XGMI0_BASE__INST6_SEG3 0 1637 + #define XGMI0_BASE__INST6_SEG4 0 1638 + #define XGMI0_BASE__INST6_SEG5 0 1639 + 1640 + #define XGMI1_BASE__INST0_SEG0 0x02439000 1641 + #define XGMI1_BASE__INST0_SEG1 0x046C0000 1642 + #define XGMI1_BASE__INST0_SEG2 0x04980000 1643 + #define XGMI1_BASE__INST0_SEG3 0 1644 + #define XGMI1_BASE__INST0_SEG4 0 1645 + #define XGMI1_BASE__INST0_SEG5 0 1646 + 1647 + #define XGMI1_BASE__INST1_SEG0 0 1648 + #define XGMI1_BASE__INST1_SEG1 0 1649 + #define XGMI1_BASE__INST1_SEG2 0 1650 + #define XGMI1_BASE__INST1_SEG3 0 1651 + #define XGMI1_BASE__INST1_SEG4 0 1652 + #define XGMI1_BASE__INST1_SEG5 0 1653 + 1654 + #define XGMI1_BASE__INST2_SEG0 0 1655 + #define XGMI1_BASE__INST2_SEG1 0 1656 + #define XGMI1_BASE__INST2_SEG2 0 1657 + #define XGMI1_BASE__INST2_SEG3 0 1658 + #define XGMI1_BASE__INST2_SEG4 0 1659 + #define XGMI1_BASE__INST2_SEG5 0 1660 + 1661 + #define XGMI1_BASE__INST3_SEG0 0 1662 + #define XGMI1_BASE__INST3_SEG1 0 1663 + #define XGMI1_BASE__INST3_SEG2 0 1664 + #define XGMI1_BASE__INST3_SEG3 0 1665 + #define XGMI1_BASE__INST3_SEG4 0 1666 + #define XGMI1_BASE__INST3_SEG5 0 1667 + 1668 + #define XGMI1_BASE__INST4_SEG0 0 1669 + #define XGMI1_BASE__INST4_SEG1 0 1670 + #define XGMI1_BASE__INST4_SEG2 0 1671 + #define XGMI1_BASE__INST4_SEG3 0 1672 + #define XGMI1_BASE__INST4_SEG4 0 1673 + #define XGMI1_BASE__INST4_SEG5 0 1674 + 1675 + #define XGMI1_BASE__INST5_SEG0 0 1676 + #define XGMI1_BASE__INST5_SEG1 0 1677 + #define XGMI1_BASE__INST5_SEG2 0 1678 + #define XGMI1_BASE__INST5_SEG3 0 1679 + #define XGMI1_BASE__INST5_SEG4 0 1680 + #define XGMI1_BASE__INST5_SEG5 0 1681 + 1682 + #define XGMI1_BASE__INST6_SEG0 0 1683 + #define XGMI1_BASE__INST6_SEG1 0 1684 + #define XGMI1_BASE__INST6_SEG2 0 1685 + #define XGMI1_BASE__INST6_SEG3 0 1686 + #define XGMI1_BASE__INST6_SEG4 0 1687 + #define XGMI1_BASE__INST6_SEG5 0 1688 + 1689 + #define XGMI2_BASE__INST0_SEG0 0x04700000 1690 + #define XGMI2_BASE__INST0_SEG1 0x049C0000 1691 + #define XGMI2_BASE__INST0_SEG2 0 1692 + #define XGMI2_BASE__INST0_SEG3 0 1693 + #define XGMI2_BASE__INST0_SEG4 0 1694 + #define XGMI2_BASE__INST0_SEG5 0 1695 + 1696 + #define XGMI2_BASE__INST1_SEG0 0x04740000 1697 + #define XGMI2_BASE__INST1_SEG1 0x04A00000 1698 + #define XGMI2_BASE__INST1_SEG2 0 1699 + #define XGMI2_BASE__INST1_SEG3 0 1700 + #define XGMI2_BASE__INST1_SEG4 0 1701 + #define XGMI2_BASE__INST1_SEG5 0 1702 + 1703 + #define XGMI2_BASE__INST2_SEG0 0x04780000 1704 + #define XGMI2_BASE__INST2_SEG1 0x04A40000 1705 + #define XGMI2_BASE__INST2_SEG2 0 1706 + #define XGMI2_BASE__INST2_SEG3 0 1707 + #define XGMI2_BASE__INST2_SEG4 0 1708 + #define XGMI2_BASE__INST2_SEG5 0 1709 + 1710 + #define XGMI2_BASE__INST3_SEG0 0x047C0000 1711 + #define XGMI2_BASE__INST3_SEG1 0x04A80000 1712 + #define XGMI2_BASE__INST3_SEG2 0 1713 + #define XGMI2_BASE__INST3_SEG3 0 1714 + #define XGMI2_BASE__INST3_SEG4 0 1715 + #define XGMI2_BASE__INST3_SEG5 0 1716 + 1717 + #define XGMI2_BASE__INST4_SEG0 0x04800000 1718 + #define XGMI2_BASE__INST4_SEG1 0x04AC0000 1719 + #define XGMI2_BASE__INST4_SEG2 0 1720 + #define XGMI2_BASE__INST4_SEG3 0 1721 + #define XGMI2_BASE__INST4_SEG4 0 1722 + #define XGMI2_BASE__INST4_SEG5 0 1723 + 1724 + #define XGMI2_BASE__INST5_SEG0 0x04840000 1725 + #define XGMI2_BASE__INST5_SEG1 0x04B00000 1726 + #define XGMI2_BASE__INST5_SEG2 0 1727 + #define XGMI2_BASE__INST5_SEG3 0 1728 + #define XGMI2_BASE__INST5_SEG4 0 1729 + #define XGMI2_BASE__INST5_SEG5 0 1730 + 1731 + #define XGMI2_BASE__INST6_SEG0 0 1732 + #define XGMI2_BASE__INST6_SEG1 0 1733 + #define XGMI2_BASE__INST6_SEG2 0 1734 + #define XGMI2_BASE__INST6_SEG3 0 1735 + #define XGMI2_BASE__INST6_SEG4 0 1736 + #define XGMI2_BASE__INST6_SEG5 0 1737 + 1738 + #endif