Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mmc: sdhci-of-aspeed: Configure the SDHCIs as specified by the devicetree.

The hardware provides capability configuration registers for each SDHCI
in the global configuration space for the SD controller. Writes to the
global capability registers are mirrored to the capability registers in
the associated SDHCI. Configuration of the capabilities must be written
through the mirror registers prior to initialisation of the SDHCI.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210524073308.9328-5-steven_lee@aspeedtech.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

authored by

Steven Lee and committed by
Ulf Hansson
dd646d98 7c45b226

+48
+48
drivers/mmc/host/sdhci-of-aspeed.c
··· 31 31 #define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) 32 32 #define ASPEED_SDC_PHASE_MAX 31 33 33 34 + /* SDIO{10,20} */ 35 + #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) 36 + /* SDIO{14,24} */ 37 + #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) 38 + 34 39 struct aspeed_sdc { 35 40 struct clk *clk; 36 41 struct resource *res; ··· 76 71 struct mmc_clk_phase_map phase_map; 77 72 const struct aspeed_sdhci_phase_desc *phase_desc; 78 73 }; 74 + 75 + /* 76 + * The function sets the mirror register for updating 77 + * capbilities of the current slot. 78 + * 79 + * slot | capability | caps_reg | mirror_reg 80 + * -----|-------------|----------|------------ 81 + * 0 | CAP1_1_8V | SDIO140 | SDIO10 82 + * 0 | CAP2_SDR104 | SDIO144 | SDIO14 83 + * 1 | CAP1_1_8V | SDIO240 | SDIO20 84 + * 1 | CAP2_SDR104 | SDIO244 | SDIO24 85 + */ 86 + static void aspeed_sdc_set_slot_capability(struct sdhci_host *host, struct aspeed_sdc *sdc, 87 + int capability, bool enable, u8 slot) 88 + { 89 + u32 mirror_reg_offset; 90 + u32 cap_val; 91 + u8 cap_reg; 92 + 93 + if (slot > 1) 94 + return; 95 + 96 + cap_reg = capability / 32; 97 + cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); 98 + if (enable) 99 + cap_val |= BIT(capability % 32); 100 + else 101 + cap_val &= ~BIT(capability % 32); 102 + mirror_reg_offset = ((slot + 1) * 0x10) + (cap_reg * 4); 103 + writel(cap_val, sdc->regs + mirror_reg_offset); 104 + } 79 105 80 106 static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, 81 107 struct aspeed_sdhci *sdhci, ··· 364 328 static int aspeed_sdhci_probe(struct platform_device *pdev) 365 329 { 366 330 const struct aspeed_sdhci_pdata *aspeed_pdata; 331 + struct device_node *np = pdev->dev.of_node; 367 332 struct sdhci_pltfm_host *pltfm_host; 368 333 struct aspeed_sdhci *dev; 369 334 struct sdhci_host *host; ··· 408 371 dev_info(&pdev->dev, "Configured for slot %d\n", slot); 409 372 410 373 sdhci_get_of_property(pdev); 374 + 375 + if (of_property_read_bool(np, "mmc-hs200-1_8v") || 376 + of_property_read_bool(np, "sd-uhs-sdr104")) { 377 + aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, 378 + true, slot); 379 + } 380 + 381 + if (of_property_read_bool(np, "sd-uhs-sdr104")) { 382 + aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, 383 + true, slot); 384 + } 411 385 412 386 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); 413 387 if (IS_ERR(pltfm_host->clk))