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Merge tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.18, please pull the following:

- Arinc defines the switch ports of the RTL8365MB switch on the Asus
RT-AC88U

- Richard provides cache information for the BCM2835/36/37 and BCM2711
SoCs such that tools like "lscpu -C" can report it when supported

- Stefan adds support for the Raspberry Pi Zero 2 W (wireless)

- Matthew defines the MAC address NVMEM cells for the Cisco Meraki
MX64/MX65 devices, he also fixes the LED for these platforms.

- Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150

* tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul XWR-3150
ARM: dts: NSP: MX6X: correct LED function types
ARM: dts: NSP: MX6X: get mac-address from eeprom
arm64: dts: broadcom: Add reference to RPi Zero 2 W
ARM: dts: Add Raspberry Pi Zero 2 W
dt-bindings: arm: bcm2835: Add Raspberry Pi Zero 2 W
ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
ARM: dts: bcm2711: Add the missing L1/L2 cache information
ARM: dts: bcm2837: Add the missing L1/L2 cache information
ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U

Link: https://lore.kernel.org/r/20220307194817.3754107-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann dd5d787f e8f022f9

+403 -6
+1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
··· 51 51 - raspberrypi,3-model-b-plus 52 52 - raspberrypi,3-compute-module 53 53 - raspberrypi,3-compute-module-lite 54 + - raspberrypi,model-zero-2-w 54 55 - const: brcm,bcm2837 55 56 56 57 additionalProperties: true
+1
arch/arm/boot/dts/Makefile
··· 93 93 bcm2837-rpi-3-b.dtb \ 94 94 bcm2837-rpi-3-b-plus.dtb \ 95 95 bcm2837-rpi-cm3-io3.dtb \ 96 + bcm2837-rpi-zero-2-w.dtb \ 96 97 bcm2711-rpi-400.dtb \ 97 98 bcm2711-rpi-4-b.dtb \ 98 99 bcm2711-rpi-cm4-io.dtb \
+50
arch/arm/boot/dts/bcm2711.dtsi
··· 458 458 #size-cells = <0>; 459 459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 460 460 461 + /* Source for d/i-cache-line-size and d/i-cache-sets 462 + * https://developer.arm.com/documentation/100095/0003 463 + * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 464 + * Source for d/i-cache-size 465 + * https://www.raspberrypi.com/documentation/computers 466 + * /processors.html#bcm2711 467 + */ 461 468 cpu0: cpu@0 { 462 469 device_type = "cpu"; 463 470 compatible = "arm,cortex-a72"; 464 471 reg = <0>; 465 472 enable-method = "spin-table"; 466 473 cpu-release-addr = <0x0 0x000000d8>; 474 + d-cache-size = <0x8000>; 475 + d-cache-line-size = <64>; 476 + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 477 + i-cache-size = <0xc000>; 478 + i-cache-line-size = <64>; 479 + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 480 + next-level-cache = <&l2>; 467 481 }; 468 482 469 483 cpu1: cpu@1 { ··· 486 472 reg = <1>; 487 473 enable-method = "spin-table"; 488 474 cpu-release-addr = <0x0 0x000000e0>; 475 + d-cache-size = <0x8000>; 476 + d-cache-line-size = <64>; 477 + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 478 + i-cache-size = <0xc000>; 479 + i-cache-line-size = <64>; 480 + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 481 + next-level-cache = <&l2>; 489 482 }; 490 483 491 484 cpu2: cpu@2 { ··· 501 480 reg = <2>; 502 481 enable-method = "spin-table"; 503 482 cpu-release-addr = <0x0 0x000000e8>; 483 + d-cache-size = <0x8000>; 484 + d-cache-line-size = <64>; 485 + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 486 + i-cache-size = <0xc000>; 487 + i-cache-line-size = <64>; 488 + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 489 + next-level-cache = <&l2>; 504 490 }; 505 491 506 492 cpu3: cpu@3 { ··· 516 488 reg = <3>; 517 489 enable-method = "spin-table"; 518 490 cpu-release-addr = <0x0 0x000000f0>; 491 + d-cache-size = <0x8000>; 492 + d-cache-line-size = <64>; 493 + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 494 + i-cache-size = <0xc000>; 495 + i-cache-line-size = <64>; 496 + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 497 + next-level-cache = <&l2>; 498 + }; 499 + 500 + /* Source for d/i-cache-line-size and d/i-cache-sets 501 + * https://developer.arm.com/documentation/100095/0003 502 + * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 503 + * Source for d/i-cache-size 504 + * https://www.raspberrypi.com/documentation/computers 505 + * /processors.html#bcm2711 506 + */ 507 + l2: l2-cache0 { 508 + compatible = "cache"; 509 + cache-size = <0x100000>; 510 + cache-line-size = <64>; 511 + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 512 + cache-level = <2>; 519 513 }; 520 514 }; 521 515
+17
arch/arm/boot/dts/bcm2835.dtsi
··· 14 14 device_type = "cpu"; 15 15 compatible = "arm,arm1176jzf-s"; 16 16 reg = <0x0>; 17 + /* Source for d/i-cache-line-size and d/i-cache-sets 18 + * https://developer.arm.com/documentation/ddi0301 19 + * /h/level-one-memory-system/cache-organization?lang=en 20 + * 21 + * Source for d/i-cache-size 22 + * https://forums.raspberrypi.com/viewtopic.php?t=98428 23 + * 24 + * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU 25 + * It can be shared with the CPU through fw settings, 26 + * but this is not recommended. 27 + */ 28 + d-cache-size = <0x4000>; 29 + d-cache-line-size = <16>; 30 + d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set 31 + i-cache-size = <0x4000>; 32 + i-cache-line-size = <16>; 33 + i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set 17 34 }; 18 35 }; 19 36
+50
arch/arm/boot/dts/bcm2836.dtsi
··· 41 41 #size-cells = <0>; 42 42 enable-method = "brcm,bcm2836-smp"; 43 43 44 + /* Source for d/i-cache-line-size and d/i-cache-sets 45 + * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System 46 + * /About-the-L1-memory-system?lang=en 47 + * 48 + * Source for d/i-cache-size 49 + * https://forums.raspberrypi.com/viewtopic.php?t=98428 50 + */ 51 + 44 52 v7_cpu0: cpu@0 { 45 53 device_type = "cpu"; 46 54 compatible = "arm,cortex-a7"; 47 55 reg = <0xf00>; 48 56 clock-frequency = <800000000>; 57 + d-cache-size = <0x8000>; 58 + d-cache-line-size = <64>; 59 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 60 + i-cache-size = <0x8000>; 61 + i-cache-line-size = <32>; 62 + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set 63 + next-level-cache = <&l2>; 49 64 }; 50 65 51 66 v7_cpu1: cpu@1 { ··· 68 53 compatible = "arm,cortex-a7"; 69 54 reg = <0xf01>; 70 55 clock-frequency = <800000000>; 56 + d-cache-size = <0x8000>; 57 + d-cache-line-size = <64>; 58 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 59 + i-cache-size = <0x8000>; 60 + i-cache-line-size = <32>; 61 + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set 62 + next-level-cache = <&l2>; 71 63 }; 72 64 73 65 v7_cpu2: cpu@2 { ··· 82 60 compatible = "arm,cortex-a7"; 83 61 reg = <0xf02>; 84 62 clock-frequency = <800000000>; 63 + d-cache-size = <0x8000>; 64 + d-cache-line-size = <64>; 65 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 66 + i-cache-size = <0x8000>; 67 + i-cache-line-size = <32>; 68 + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set 69 + next-level-cache = <&l2>; 85 70 }; 86 71 87 72 v7_cpu3: cpu@3 { ··· 96 67 compatible = "arm,cortex-a7"; 97 68 reg = <0xf03>; 98 69 clock-frequency = <800000000>; 70 + d-cache-size = <0x8000>; 71 + d-cache-line-size = <64>; 72 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 73 + i-cache-size = <0x8000>; 74 + i-cache-line-size = <32>; 75 + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set 76 + next-level-cache = <&l2>; 77 + }; 78 + 79 + /* Source for cache-line-size + cache-sets 80 + * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System 81 + * /About-the-L2-Memory-system?lang=en 82 + * Source for cache-size 83 + * https://forums.raspberrypi.com/viewtopic.php?t=98428 84 + */ 85 + l2: l2-cache0 { 86 + compatible = "cache"; 87 + cache-size = <0x80000>; 88 + cache-line-size = <64>; 89 + cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set 90 + cache-level = <2>; 99 91 }; 100 92 }; 101 93 };
+136
arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright (C) 2022 Stefan Wahren <stefan.wahren@i2se.com> 4 + */ 5 + 6 + /dts-v1/; 7 + #include "bcm2837.dtsi" 8 + #include "bcm2836-rpi.dtsi" 9 + #include "bcm283x-rpi-usb-otg.dtsi" 10 + #include "bcm283x-rpi-wifi-bt.dtsi" 11 + 12 + / { 13 + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; 14 + model = "Raspberry Pi Zero 2 W"; 15 + 16 + memory@0 { 17 + device_type = "memory"; 18 + reg = <0 0x20000000>; 19 + }; 20 + 21 + chosen { 22 + /* 8250 auxiliary UART instead of pl011 */ 23 + stdout-path = "serial1:115200n8"; 24 + }; 25 + 26 + leds { 27 + led-act { 28 + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; 29 + }; 30 + }; 31 + }; 32 + 33 + &bt { 34 + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; 35 + }; 36 + 37 + &gpio { 38 + /* 39 + * This is based on the official GPU firmware DT blob. 40 + * 41 + * Legend: 42 + * "NC" = not connected (no rail from the SoC) 43 + * "FOO" = GPIO line named "FOO" on the schematic 44 + * "FOO_N" = GPIO line named "FOO" on schematic, active low 45 + */ 46 + gpio-line-names = "ID_SDA", 47 + "ID_SCL", 48 + "SDA1", 49 + "SCL1", 50 + "GPIO_GCLK", 51 + "GPIO5", 52 + "GPIO6", 53 + "SPI_CE1_N", 54 + "SPI_CE0_N", 55 + "SPI_MISO", 56 + "SPI_MOSI", 57 + "SPI_SCLK", 58 + "GPIO12", 59 + "GPIO13", 60 + /* Serial port */ 61 + "TXD0", 62 + "RXD0", 63 + "GPIO16", 64 + "GPIO17", 65 + "GPIO18", 66 + "GPIO19", 67 + "GPIO20", 68 + "GPIO21", 69 + "GPIO22", 70 + "GPIO23", 71 + "GPIO24", 72 + "GPIO25", 73 + "GPIO26", 74 + "GPIO27", 75 + "HDMI_HPD_N", 76 + "STATUS_LED_N", 77 + "NC", /* GPIO30 */ 78 + "NC", /* GPIO31 */ 79 + "NC", /* GPIO32 */ 80 + "NC", /* GPIO33 */ 81 + "NC", /* GPIO34 */ 82 + "NC", /* GPIO35 */ 83 + "NC", /* GPIO36 */ 84 + "NC", /* GPIO37 */ 85 + "NC", /* GPIO38 */ 86 + "NC", /* GPIO39 */ 87 + "CAM_GPIO0", /* GPIO40 */ 88 + "WL_ON", /* GPIO41 */ 89 + "BT_ON", /* GPIO42 */ 90 + "WIFI_CLK", /* GPIO43 */ 91 + "SDA0", /* GPIO44 */ 92 + "SCL0", /* GPIO45 */ 93 + "SMPS_SCL", 94 + "SMPS_SDA", 95 + /* Used by SD Card */ 96 + "SD_CLK_R", 97 + "SD_CMD_R", 98 + "SD_DATA0_R", 99 + "SD_DATA1_R", 100 + "SD_DATA2_R", 101 + "SD_DATA3_R"; 102 + 103 + pinctrl-0 = <&gpioout &alt0>; 104 + }; 105 + 106 + &hdmi { 107 + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; 108 + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; 109 + status = "okay"; 110 + }; 111 + 112 + &sdhci { 113 + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; 114 + }; 115 + 116 + &sdhost { 117 + pinctrl-names = "default"; 118 + pinctrl-0 = <&sdhost_gpio48>; 119 + bus-width = <4>; 120 + status = "okay"; 121 + }; 122 + 123 + &uart0 { 124 + pinctrl-names = "default"; 125 + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; 126 + }; 127 + 128 + &uart1 { 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&uart1_gpio14>; 131 + status = "okay"; 132 + }; 133 + 134 + &wifi_pwrseq { 135 + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; 136 + };
+49
arch/arm/boot/dts/bcm2837.dtsi
··· 40 40 #size-cells = <0>; 41 41 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 42 42 43 + /* Source for d/i-cache-line-size and d/i-cache-sets 44 + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 45 + * /about-the-l1-memory-system?lang=en 46 + * 47 + * Source for d/i-cache-size 48 + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 49 + */ 43 50 cpu0: cpu@0 { 44 51 device_type = "cpu"; 45 52 compatible = "arm,cortex-a53"; 46 53 reg = <0>; 47 54 enable-method = "spin-table"; 48 55 cpu-release-addr = <0x0 0x000000d8>; 56 + d-cache-size = <0x8000>; 57 + d-cache-line-size = <64>; 58 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 59 + i-cache-size = <0x8000>; 60 + i-cache-line-size = <64>; 61 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 62 + next-level-cache = <&l2>; 49 63 }; 50 64 51 65 cpu1: cpu@1 { ··· 68 54 reg = <1>; 69 55 enable-method = "spin-table"; 70 56 cpu-release-addr = <0x0 0x000000e0>; 57 + d-cache-size = <0x8000>; 58 + d-cache-line-size = <64>; 59 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 60 + i-cache-size = <0x8000>; 61 + i-cache-line-size = <64>; 62 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 63 + next-level-cache = <&l2>; 71 64 }; 72 65 73 66 cpu2: cpu@2 { ··· 83 62 reg = <2>; 84 63 enable-method = "spin-table"; 85 64 cpu-release-addr = <0x0 0x000000e8>; 65 + d-cache-size = <0x8000>; 66 + d-cache-line-size = <64>; 67 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 68 + i-cache-size = <0x8000>; 69 + i-cache-line-size = <64>; 70 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 71 + next-level-cache = <&l2>; 86 72 }; 87 73 88 74 cpu3: cpu@3 { ··· 98 70 reg = <3>; 99 71 enable-method = "spin-table"; 100 72 cpu-release-addr = <0x0 0x000000f0>; 73 + d-cache-size = <0x8000>; 74 + d-cache-line-size = <64>; 75 + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 76 + i-cache-size = <0x8000>; 77 + i-cache-line-size = <64>; 78 + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 79 + next-level-cache = <&l2>; 80 + }; 81 + 82 + /* Source for cache-line-size + cache-sets 83 + * https://developer.arm.com/documentation/ddi0500 84 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 85 + * Source for cache-size 86 + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 87 + */ 88 + l2: l2-cache0 { 89 + compatible = "cache"; 90 + cache-size = <0x80000>; 91 + cache-line-size = <64>; 92 + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 93 + cache-level = <2>; 101 94 }; 102 95 }; 103 96 };
+76
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
··· 93 93 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; 94 94 }; 95 95 }; 96 + 97 + switch { 98 + compatible = "realtek,rtl8365mb"; 99 + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ 100 + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; 101 + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; 102 + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; 103 + realtek,disable-leds; 104 + dsa,member = <1 0>; 105 + 106 + ports { 107 + #address-cells = <1>; 108 + #size-cells = <0>; 109 + 110 + port@0 { 111 + reg = <0>; 112 + label = "lan5"; 113 + phy-handle = <&ethphy0>; 114 + }; 115 + 116 + port@1 { 117 + reg = <1>; 118 + label = "lan6"; 119 + phy-handle = <&ethphy1>; 120 + }; 121 + 122 + port@2 { 123 + reg = <2>; 124 + label = "lan7"; 125 + phy-handle = <&ethphy2>; 126 + }; 127 + 128 + port@3 { 129 + reg = <3>; 130 + label = "lan8"; 131 + phy-handle = <&ethphy3>; 132 + }; 133 + 134 + port@6 { 135 + reg = <6>; 136 + label = "cpu"; 137 + ethernet = <&sw0_p5>; 138 + phy-mode = "rgmii"; 139 + tx-internal-delay-ps = <2000>; 140 + rx-internal-delay-ps = <2100>; 141 + 142 + fixed-link { 143 + speed = <1000>; 144 + full-duplex; 145 + pause; 146 + }; 147 + }; 148 + }; 149 + 150 + mdio { 151 + compatible = "realtek,smi-mdio"; 152 + #address-cells = <1>; 153 + #size-cells = <0>; 154 + 155 + ethphy0: ethernet-phy@0 { 156 + reg = <0>; 157 + }; 158 + 159 + ethphy1: ethernet-phy@1 { 160 + reg = <1>; 161 + }; 162 + 163 + ethphy2: ethernet-phy@2 { 164 + reg = <2>; 165 + }; 166 + 167 + ethphy3: ethernet-phy@3 { 168 + reg = <3>; 169 + }; 170 + }; 171 + }; 96 172 }; 97 173 98 174 &srab {
+8
arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
··· 25 25 nvram@1eff0000 { 26 26 compatible = "brcm,nvram"; 27 27 reg = <0x1eff0000 0x10000>; 28 + 29 + et0macaddr: et0macaddr { 30 + }; 28 31 }; 29 32 30 33 leds { ··· 73 70 gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; 74 71 }; 75 72 }; 73 + }; 74 + 75 + &gmac0 { 76 + nvmem-cells = <&et0macaddr>; 77 + nvmem-cell-names = "mac-address"; 76 78 }; 77 79 78 80 &usb3 {
+1 -2
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
··· 57 57 58 58 led-4 { 59 59 /* amber:power */ 60 - function = LED_FUNCTION_POWER; 60 + function = LED_FUNCTION_FAULT; 61 61 color = <LED_COLOR_ID_AMBER>; 62 62 gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; 63 - default-state = "on"; 64 63 }; 65 64 66 65 led-5 {
+1 -2
arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
··· 106 106 107 107 led-a { 108 108 /* amber:power */ 109 - function = LED_FUNCTION_POWER; 109 + function = LED_FUNCTION_FAULT; 110 110 color = <LED_COLOR_ID_AMBER>; 111 111 gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; 112 - default-state = "on"; 113 112 }; 114 113 115 114 led-b {
+9 -1
arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
··· 22 22 }; 23 23 24 24 led-2 { 25 - function = LED_FUNCTION_INDICATOR; 25 + function = LED_FUNCTION_POWER; 26 26 color = <LED_COLOR_ID_GREEN>; 27 27 pwms = <&pwm 2 50000>; 28 28 max-brightness = <255>; ··· 39 39 40 40 &amac2 { 41 41 status = "okay"; 42 + nvmem-cells = <&mac_address>; 43 + nvmem-cell-names = "mac-address"; 42 44 }; 43 45 44 46 &ehci0 { ··· 55 53 reg = <0x50>; 56 54 pagesize = <32>; 57 55 read-only; 56 + #address-cells = <1>; 57 + #size-cells = <1>; 58 + 59 + mac_address: mac-address@66 { 60 + reg = <0x66 0x6>; 61 + }; 58 62 }; 59 63 }; 60 64
+2 -1
arch/arm64/boot/dts/broadcom/Makefile
··· 5 5 bcm2837-rpi-3-a-plus.dtb \ 6 6 bcm2837-rpi-3-b.dtb \ 7 7 bcm2837-rpi-3-b-plus.dtb \ 8 - bcm2837-rpi-cm3-io3.dtb 8 + bcm2837-rpi-cm3-io3.dtb \ 9 + bcm2837-rpi-zero-2-w.dtb 9 10 10 11 subdir-y += bcm4908 11 12 subdir-y += northstar2
+2
arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + #include "arm/bcm2837-rpi-zero-2-w.dts"