tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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tg3: Add TG3_FLG3_USE_PHYLIB

This patch introduces the TG3_FLG3_USE_PHYLIB flag and applies it to
some select places. This work makes later patches a little easier to
read.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Matt Carlson and committed by
David S. Miller dd477003 f51f3562

+53 -34
+52 -34
drivers/net/tg3.c
··· 1605 1605 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); 1606 1606 udelay(40); 1607 1607 return; 1608 - } else { 1608 + } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 1609 1609 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1610 1610 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1611 1611 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); ··· 1687 1687 tw32(TG3PCI_MISC_HOST_CTRL, 1688 1688 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); 1689 1689 1690 - if (tp->link_config.phy_is_low_power == 0) { 1690 + if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 1691 1691 tp->link_config.phy_is_low_power = 1; 1692 - tp->link_config.orig_speed = tp->link_config.speed; 1693 - tp->link_config.orig_duplex = tp->link_config.duplex; 1694 - tp->link_config.orig_autoneg = tp->link_config.autoneg; 1695 - } 1692 + } else { 1693 + if (tp->link_config.phy_is_low_power == 0) { 1694 + tp->link_config.phy_is_low_power = 1; 1695 + tp->link_config.orig_speed = tp->link_config.speed; 1696 + tp->link_config.orig_duplex = tp->link_config.duplex; 1697 + tp->link_config.orig_autoneg = tp->link_config.autoneg; 1698 + } 1696 1699 1697 - if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { 1698 - tp->link_config.speed = SPEED_10; 1699 - tp->link_config.duplex = DUPLEX_HALF; 1700 - tp->link_config.autoneg = AUTONEG_ENABLE; 1701 - tg3_setup_phy(tp, 0); 1700 + if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { 1701 + tp->link_config.speed = SPEED_10; 1702 + tp->link_config.duplex = DUPLEX_HALF; 1703 + tp->link_config.autoneg = AUTONEG_ENABLE; 1704 + tg3_setup_phy(tp, 0); 1705 + } 1702 1706 } 1703 1707 1704 1708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { ··· 1733 1729 u32 mac_mode; 1734 1730 1735 1731 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 1736 - tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); 1737 - udelay(40); 1732 + if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 1733 + tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); 1734 + udelay(40); 1735 + } 1738 1736 1739 1737 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) 1740 1738 mac_mode = MAC_MODE_PORT_MODE_GMII; ··· 3827 3821 sblk->status = SD_STATUS_UPDATED | 3828 3822 (sblk->status & ~SD_STATUS_LINK_CHG); 3829 3823 spin_lock(&tp->lock); 3830 - tg3_setup_phy(tp, 0); 3824 + if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { 3825 + tw32_f(MAC_STATUS, 3826 + (MAC_STATUS_SYNC_CHANGED | 3827 + MAC_STATUS_CFG_CHANGED | 3828 + MAC_STATUS_MI_COMPLETION | 3829 + MAC_STATUS_LNKSTATE_CHANGED)); 3830 + udelay(40); 3831 + } else 3832 + tg3_setup_phy(tp, 0); 3831 3833 spin_unlock(&tp->lock); 3832 3834 } 3833 3835 } ··· 6616 6602 tg3_abort_hw(tp, 1); 6617 6603 } 6618 6604 6619 - if (reset_phy) 6605 + if (reset_phy && 6606 + !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) 6620 6607 tg3_phy_reset(tp); 6621 6608 6622 6609 err = tg3_chip_reset(tp); ··· 7168 7153 tw32_f(MAC_RX_MODE, tp->rx_mode); 7169 7154 udelay(10); 7170 7155 7171 - if (tp->link_config.phy_is_low_power) { 7172 - tp->link_config.phy_is_low_power = 0; 7173 - tp->link_config.speed = tp->link_config.orig_speed; 7174 - tp->link_config.duplex = tp->link_config.orig_duplex; 7175 - tp->link_config.autoneg = tp->link_config.orig_autoneg; 7176 - } 7177 - 7178 7156 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; 7179 7157 tw32_f(MAC_MI_MODE, tp->mi_mode); 7180 7158 udelay(80); ··· 7218 7210 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 7219 7211 } 7220 7212 7221 - err = tg3_setup_phy(tp, 0); 7222 - if (err) 7223 - return err; 7213 + if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 7214 + if (tp->link_config.phy_is_low_power) { 7215 + tp->link_config.phy_is_low_power = 0; 7216 + tp->link_config.speed = tp->link_config.orig_speed; 7217 + tp->link_config.duplex = tp->link_config.orig_duplex; 7218 + tp->link_config.autoneg = tp->link_config.orig_autoneg; 7219 + } 7224 7220 7225 - if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7226 - GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { 7227 - u32 tmp; 7221 + err = tg3_setup_phy(tp, 0); 7222 + if (err) 7223 + return err; 7228 7224 7229 - /* Clear CRC stats. */ 7230 - if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { 7231 - tg3_writephy(tp, MII_TG3_TEST1, 7232 - tmp | MII_TG3_TEST1_CRC_EN); 7233 - tg3_readphy(tp, 0x14, &tmp); 7225 + if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 7226 + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) { 7227 + u32 tmp; 7228 + 7229 + /* Clear CRC stats. */ 7230 + if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { 7231 + tg3_writephy(tp, MII_TG3_TEST1, 7232 + tmp | MII_TG3_TEST1_CRC_EN); 7233 + tg3_readphy(tp, 0x14, &tmp); 7234 + } 7234 7235 } 7235 7236 } 7236 7237 ··· 9661 9644 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); 9662 9645 } 9663 9646 9664 - if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { 9647 + if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 9648 + !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { 9665 9649 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) 9666 9650 err |= TG3_PHY_LOOPBACK_FAILED; 9667 9651 }
+1
drivers/net/tg3.h
··· 2480 2480 #define TG3_FLG3_ENABLE_APE 0x00000002 2481 2481 #define TG3_FLG3_5761_5784_AX_FIXES 0x00000004 2482 2482 #define TG3_FLG3_5701_DMA_BUG 0x00000008 2483 + #define TG3_FLG3_USE_PHYLIB 0x00000010 2483 2484 2484 2485 struct timer_list timer; 2485 2486 u16 timer_counter;