dt-bindings: clock: Add RK3562 cru · tjh.dev/kernel@dd113c4

+55

Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Rockchip rk3562 Clock and Reset Control Module 8 + 9 + maintainers: 10 + - Elaine Zhang <zhangqing@rock-chips.com> 11 + - Heiko Stuebner <heiko@sntech.de> 12 + 13 + description: 14 + The RK3562 clock controller generates the clock and also implements a reset 15 + controller for SoC peripherals. For example it provides SCLK_UART2 and 16 + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART 17 + module. 18 + 19 + properties: 20 + compatible: 21 + const: rockchip,rk3562-cru 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + "#clock-cells": 27 + const: 1 28 + 29 + "#reset-cells": 30 + const: 1 31 + 32 + clocks: 33 + maxItems: 2 34 + 35 + clock-names: 36 + items: 37 + - const: xin24m 38 + - const: xin32k 39 + 40 + required: 41 + - compatible 42 + - reg 43 + - "#clock-cells" 44 + - "#reset-cells" 45 + 46 + additionalProperties: false 47 + 48 + examples: 49 + - | 50 + clock-controller@ff100000 { 51 + compatible = "rockchip,rk3562-cru"; 52 + reg = <0xff100000 0x40000>; 53 + #clock-cells = <1>; 54 + #reset-cells = <1>; 55 + };

+379

include/dt-bindings/clock/rockchip,rk3562-cru.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd. 4 + * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H 8 + #define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H 9 + 10 + /* cru-clocks indices */ 11 + 12 + /* cru plls */ 13 + #define PLL_DMPLL0 0 14 + #define PLL_APLL 1 15 + #define PLL_GPLL 2 16 + #define PLL_VPLL 3 17 + #define PLL_HPLL 4 18 + #define PLL_CPLL 5 19 + #define PLL_DPLL 6 20 + #define PLL_DMPLL1 7 21 + 22 + /* cru clocks */ 23 + #define ARMCLK 8 24 + #define CLK_GPU 9 25 + #define ACLK_RKNN 10 26 + #define CLK_DDR 11 27 + #define CLK_MATRIX_50M_SRC 12 28 + #define CLK_MATRIX_100M_SRC 13 29 + #define CLK_MATRIX_125M_SRC 14 30 + #define CLK_MATRIX_200M_SRC 15 31 + #define CLK_MATRIX_300M_SRC 16 32 + #define ACLK_TOP 17 33 + #define ACLK_TOP_VIO 18 34 + #define CLK_CAM0_OUT2IO 19 35 + #define CLK_CAM1_OUT2IO 20 36 + #define CLK_CAM2_OUT2IO 21 37 + #define CLK_CAM3_OUT2IO 22 38 + #define ACLK_BUS 23 39 + #define HCLK_BUS 24 40 + #define PCLK_BUS 25 41 + #define PCLK_I2C1 26 42 + #define PCLK_I2C2 27 43 + #define PCLK_I2C3 28 44 + #define PCLK_I2C4 29 45 + #define PCLK_I2C5 30 46 + #define CLK_I2C 31 47 + #define CLK_I2C1 32 48 + #define CLK_I2C2 33 49 + #define CLK_I2C3 34 50 + #define CLK_I2C4 35 51 + #define CLK_I2C5 36 52 + #define DCLK_BUS_GPIO 37 53 + #define DCLK_BUS_GPIO3 38 54 + #define DCLK_BUS_GPIO4 39 55 + #define PCLK_TIMER 40 56 + #define CLK_TIMER0 41 57 + #define CLK_TIMER1 42 58 + #define CLK_TIMER2 43 59 + #define CLK_TIMER3 44 60 + #define CLK_TIMER4 45 61 + #define CLK_TIMER5 46 62 + #define PCLK_STIMER 47 63 + #define CLK_STIMER0 48 64 + #define CLK_STIMER1 49 65 + #define PCLK_WDTNS 50 66 + #define CLK_WDTNS 51 67 + #define PCLK_GRF 52 68 + #define PCLK_SGRF 53 69 + #define PCLK_MAILBOX 54 70 + #define PCLK_INTC 55 71 + #define ACLK_BUS_GIC400 56 72 + #define ACLK_BUS_SPINLOCK 57 73 + #define ACLK_DCF 58 74 + #define PCLK_DCF 59 75 + #define FCLK_BUS_CM0_CORE 60 76 + #define CLK_BUS_CM0_RTC 61 77 + #define HCLK_ICACHE 62 78 + #define HCLK_DCACHE 63 79 + #define PCLK_TSADC 64 80 + #define CLK_TSADC 65 81 + #define CLK_TSADC_TSEN 66 82 + #define PCLK_DFT2APB 67 83 + #define CLK_SARADC_VCCIO156 68 84 + #define PCLK_GMAC 69 85 + #define ACLK_GMAC 70 86 + #define CLK_GMAC_125M_CRU_I 71 87 + #define CLK_GMAC_50M_CRU_I 72 88 + #define CLK_GMAC_50M_O 73 89 + #define CLK_GMAC_ETH_OUT2IO 74 90 + #define PCLK_APB2ASB_VCCIO156 75 91 + #define PCLK_TO_VCCIO156 76 92 + #define PCLK_DSIPHY 77 93 + #define PCLK_DSITX 78 94 + #define PCLK_CPU_EMA_DET 79 95 + #define PCLK_HASH 80 96 + #define PCLK_TOPCRU 81 97 + #define PCLK_ASB2APB_VCCIO156 82 98 + #define PCLK_IOC_VCCIO156 83 99 + #define PCLK_GPIO3_VCCIO156 84 100 + #define PCLK_GPIO4_VCCIO156 85 101 + #define PCLK_SARADC_VCCIO156 86 102 + #define PCLK_MAC100 87 103 + #define ACLK_MAC100 89 104 + #define CLK_MAC100_50M_MATRIX 90 105 + #define HCLK_CORE 91 106 + #define PCLK_DDR 92 107 + #define CLK_MSCH_BRG_BIU 93 108 + #define PCLK_DDR_HWLP 94 109 + #define PCLK_DDR_UPCTL 95 110 + #define PCLK_DDR_PHY 96 111 + #define PCLK_DDR_DFICTL 97 112 + #define PCLK_DDR_DMA2DDR 98 113 + #define PCLK_DDR_MON 99 114 + #define TMCLK_DDR_MON 100 115 + #define PCLK_DDR_GRF 101 116 + #define PCLK_DDR_CRU 102 117 + #define PCLK_SUBDDR_CRU 103 118 + #define CLK_GPU_PRE 104 119 + #define ACLK_GPU_PRE 105 120 + #define CLK_GPU_BRG 107 121 + #define CLK_NPU_PRE 108 122 + #define HCLK_NPU_PRE 109 123 + #define HCLK_RKNN 111 124 + #define ACLK_PERI 112 125 + #define HCLK_PERI 113 126 + #define PCLK_PERI 114 127 + #define PCLK_PERICRU 115 128 + #define HCLK_SAI0 116 129 + #define CLK_SAI0_SRC 117 130 + #define CLK_SAI0_FRAC 118 131 + #define CLK_SAI0 119 132 + #define MCLK_SAI0 120 133 + #define MCLK_SAI0_OUT2IO 121 134 + #define HCLK_SAI1 122 135 + #define CLK_SAI1_SRC 123 136 + #define CLK_SAI1_FRAC 124 137 + #define CLK_SAI1 125 138 + #define MCLK_SAI1 126 139 + #define MCLK_SAI1_OUT2IO 127 140 + #define HCLK_SAI2 128 141 + #define CLK_SAI2_SRC 129 142 + #define CLK_SAI2_FRAC 130 143 + #define CLK_SAI2 131 144 + #define MCLK_SAI2 132 145 + #define MCLK_SAI2_OUT2IO 133 146 + #define HCLK_DSM 134 147 + #define CLK_DSM 135 148 + #define HCLK_PDM 136 149 + #define MCLK_PDM 137 150 + #define HCLK_SPDIF 138 151 + #define CLK_SPDIF_SRC 139 152 + #define CLK_SPDIF_FRAC 140 153 + #define CLK_SPDIF 141 154 + #define MCLK_SPDIF 142 155 + #define HCLK_SDMMC0 143 156 + #define CCLK_SDMMC0 144 157 + #define HCLK_SDMMC1 145 158 + #define CCLK_SDMMC1 146 159 + #define SCLK_SDMMC0_DRV 147 160 + #define SCLK_SDMMC0_SAMPLE 148 161 + #define SCLK_SDMMC1_DRV 149 162 + #define SCLK_SDMMC1_SAMPLE 150 163 + #define HCLK_EMMC 151 164 + #define ACLK_EMMC 152 165 + #define CCLK_EMMC 153 166 + #define BCLK_EMMC 154 167 + #define TMCLK_EMMC 155 168 + #define SCLK_SFC 156 169 + #define HCLK_SFC 157 170 + #define HCLK_USB2HOST 158 171 + #define HCLK_USB2HOST_ARB 159 172 + #define PCLK_SPI1 160 173 + #define CLK_SPI1 161 174 + #define SCLK_IN_SPI1 162 175 + #define PCLK_SPI2 163 176 + #define CLK_SPI2 164 177 + #define SCLK_IN_SPI2 165 178 + #define PCLK_UART1 166 179 + #define PCLK_UART2 167 180 + #define PCLK_UART3 168 181 + #define PCLK_UART4 169 182 + #define PCLK_UART5 170 183 + #define PCLK_UART6 171 184 + #define PCLK_UART7 172 185 + #define PCLK_UART8 173 186 + #define PCLK_UART9 174 187 + #define CLK_UART1_SRC 175 188 + #define CLK_UART1_FRAC 176 189 + #define CLK_UART1 177 190 + #define SCLK_UART1 178 191 + #define CLK_UART2_SRC 179 192 + #define CLK_UART2_FRAC 180 193 + #define CLK_UART2 181 194 + #define SCLK_UART2 182 195 + #define CLK_UART3_SRC 183 196 + #define CLK_UART3_FRAC 184 197 + #define CLK_UART3 185 198 + #define SCLK_UART3 186 199 + #define CLK_UART4_SRC 187 200 + #define CLK_UART4_FRAC 188 201 + #define CLK_UART4 189 202 + #define SCLK_UART4 190 203 + #define CLK_UART5_SRC 191 204 + #define CLK_UART5_FRAC 192 205 + #define CLK_UART5 193 206 + #define SCLK_UART5 194 207 + #define CLK_UART6_SRC 195 208 + #define CLK_UART6_FRAC 196 209 + #define CLK_UART6 197 210 + #define SCLK_UART6 198 211 + #define CLK_UART7_SRC 199 212 + #define CLK_UART7_FRAC 200 213 + #define CLK_UART7 201 214 + #define SCLK_UART7 202 215 + #define CLK_UART8_SRC 203 216 + #define CLK_UART8_FRAC 204 217 + #define CLK_UART8 205 218 + #define SCLK_UART8 206 219 + #define CLK_UART9_SRC 207 220 + #define CLK_UART9_FRAC 208 221 + #define CLK_UART9 209 222 + #define SCLK_UART9 210 223 + #define PCLK_PWM1_PERI 211 224 + #define CLK_PWM1_PERI 212 225 + #define CLK_CAPTURE_PWM1_PERI 213 226 + #define PCLK_PWM2_PERI 214 227 + #define CLK_PWM2_PERI 215 228 + #define CLK_CAPTURE_PWM2_PERI 216 229 + #define PCLK_PWM3_PERI 217 230 + #define CLK_PWM3_PERI 218 231 + #define CLK_CAPTURE_PWM3_PERI 219 232 + #define PCLK_CAN0 220 233 + #define CLK_CAN0 221 234 + #define PCLK_CAN1 222 235 + #define CLK_CAN1 223 236 + #define ACLK_CRYPTO 224 237 + #define HCLK_CRYPTO 225 238 + #define PCLK_CRYPTO 226 239 + #define CLK_CORE_CRYPTO 227 240 + #define CLK_PKA_CRYPTO 228 241 + #define HCLK_KLAD 229 242 + #define PCLK_KEY_READER 230 243 + #define HCLK_RK_RNG_NS 231 244 + #define HCLK_RK_RNG_S 232 245 + #define HCLK_TRNG_NS 233 246 + #define HCLK_TRNG_S 234 247 + #define HCLK_CRYPTO_S 235 248 + #define PCLK_PERI_WDT 236 249 + #define TCLK_PERI_WDT 237 250 + #define ACLK_SYSMEM 238 251 + #define HCLK_BOOTROM 239 252 + #define PCLK_PERI_GRF 240 253 + #define ACLK_DMAC 241 254 + #define ACLK_RKDMAC 242 255 + #define PCLK_OTPC_NS 243 256 + #define CLK_SBPI_OTPC_NS 244 257 + #define CLK_USER_OTPC_NS 245 258 + #define PCLK_OTPC_S 246 259 + #define CLK_SBPI_OTPC_S 247 260 + #define CLK_USER_OTPC_S 248 261 + #define CLK_OTPC_ARB 249 262 + #define PCLK_OTPPHY 250 263 + #define PCLK_USB2PHY 251 264 + #define PCLK_PIPEPHY 252 265 + #define PCLK_SARADC 253 266 + #define CLK_SARADC 254 267 + #define PCLK_IOC_VCCIO234 255 268 + #define PCLK_PERI_GPIO1 256 269 + #define PCLK_PERI_GPIO2 257 270 + #define DCLK_PERI_GPIO 258 271 + #define DCLK_PERI_GPIO1 259 272 + #define DCLK_PERI_GPIO2 260 273 + #define ACLK_PHP 261 274 + #define PCLK_PHP 262 275 + #define ACLK_PCIE20_MST 263 276 + #define ACLK_PCIE20_SLV 264 277 + #define ACLK_PCIE20_DBI 265 278 + #define PCLK_PCIE20 266 279 + #define CLK_PCIE20_AUX 267 280 + #define ACLK_USB3OTG 268 281 + #define CLK_USB3OTG_SUSPEND 269 282 + #define CLK_USB3OTG_REF 270 283 + #define CLK_PIPEPHY_REF_FUNC 271 284 + #define CLK_200M_PMU 272 285 + #define CLK_RTC_32K 273 286 + #define CLK_RTC32K_FRAC 274 287 + #define BUSCLK_PDPMU0 275 288 + #define PCLK_PMU0_CRU 276 289 + #define PCLK_PMU0_PMU 277 290 + #define CLK_PMU0_PMU 278 291 + #define PCLK_PMU0_HP_TIMER 279 292 + #define CLK_PMU0_HP_TIMER 280 293 + #define CLK_PMU0_32K_HP_TIMER 281 294 + #define PCLK_PMU0_PVTM 282 295 + #define CLK_PMU0_PVTM 283 296 + #define PCLK_IOC_PMUIO 284 297 + #define PCLK_PMU0_GPIO0 285 298 + #define DBCLK_PMU0_GPIO0 286 299 + #define PCLK_PMU0_GRF 287 300 + #define PCLK_PMU0_SGRF 288 301 + #define CLK_DDR_FAIL_SAFE 289 302 + #define PCLK_PMU0_SCRKEYGEN 290 303 + #define PCLK_PMU1_CRU 291 304 + #define HCLK_PMU1_MEM 292 305 + #define PCLK_PMU0_I2C0 293 306 + #define CLK_PMU0_I2C0 294 307 + #define PCLK_PMU1_UART0 295 308 + #define CLK_PMU1_UART0_SRC 296 309 + #define CLK_PMU1_UART0_FRAC 297 310 + #define CLK_PMU1_UART0 298 311 + #define SCLK_PMU1_UART0 299 312 + #define PCLK_PMU1_SPI0 300 313 + #define CLK_PMU1_SPI0 301 314 + #define SCLK_IN_PMU1_SPI0 302 315 + #define PCLK_PMU1_PWM0 303 316 + #define CLK_PMU1_PWM0 304 317 + #define CLK_CAPTURE_PMU1_PWM0 305 318 + #define CLK_PMU1_WIFI 306 319 + #define FCLK_PMU1_CM0_CORE 307 320 + #define CLK_PMU1_CM0_RTC 308 321 + #define PCLK_PMU1_WDTNS 309 322 + #define CLK_PMU1_WDTNS 310 323 + #define PCLK_PMU1_MAILBOX 311 324 + #define CLK_PIPEPHY_DIV 312 325 + #define CLK_PIPEPHY_XIN24M 313 326 + #define CLK_PIPEPHY_REF 314 327 + #define CLK_24M_SSCSRC 315 328 + #define CLK_USB2PHY_XIN24M 316 329 + #define CLK_USB2PHY_REF 317 330 + #define CLK_MIPIDSIPHY_XIN24M 318 331 + #define CLK_MIPIDSIPHY_REF 319 332 + #define ACLK_RGA_PRE 320 333 + #define HCLK_RGA_PRE 321 334 + #define ACLK_RGA 322 335 + #define HCLK_RGA 323 336 + #define CLK_RGA_CORE 324 337 + #define ACLK_JDEC 325 338 + #define HCLK_JDEC 326 339 + #define ACLK_VDPU_PRE 327 340 + #define CLK_RKVDEC_HEVC_CA 328 341 + #define HCLK_VDPU_PRE 329 342 + #define ACLK_RKVDEC 330 343 + #define HCLK_RKVDEC 331 344 + #define CLK_RKVENC_CORE 332 345 + #define ACLK_VEPU_PRE 333 346 + #define HCLK_VEPU_PRE 334 347 + #define ACLK_RKVENC 335 348 + #define HCLK_RKVENC 336 349 + #define ACLK_VI 337 350 + #define HCLK_VI 338 351 + #define PCLK_VI 339 352 + #define ACLK_ISP 340 353 + #define HCLK_ISP 341 354 + #define CLK_ISP 342 355 + #define ACLK_VICAP 343 356 + #define HCLK_VICAP 344 357 + #define DCLK_VICAP 345 358 + #define CSIRX0_CLK_DATA 346 359 + #define CSIRX1_CLK_DATA 347 360 + #define CSIRX2_CLK_DATA 348 361 + #define CSIRX3_CLK_DATA 349 362 + #define PCLK_CSIHOST0 350 363 + #define PCLK_CSIHOST1 351 364 + #define PCLK_CSIHOST2 352 365 + #define PCLK_CSIHOST3 353 366 + #define PCLK_CSIPHY0 354 367 + #define PCLK_CSIPHY1 355 368 + #define ACLK_VO_PRE 356 369 + #define HCLK_VO_PRE 357 370 + #define ACLK_VOP 358 371 + #define HCLK_VOP 359 372 + #define DCLK_VOP 360 373 + #define DCLK_VOP1 361 374 + #define ACLK_CRYPTO_S 362 375 + #define PCLK_CRYPTO_S 363 376 + #define CLK_CORE_CRYPTO_S 364 377 + #define CLK_PKA_CRYPTO_S 365 378 + 379 + #endif

+358

include/dt-bindings/reset/rockchip,rk3562-cru.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd. 4 + * 5 + * Author: Elaine Zhang <zhangqing@rock-chips.com> 6 + */ 7 + 8 + #ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H 9 + #define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H 10 + 11 + /********Name=SOFTRST_CON01,Offset=0x404********/ 12 + #define SRST_A_TOP_BIU 0 13 + #define SRST_A_TOP_VIO_BIU 1 14 + #define SRST_REF_PVTPLL_LOGIC 2 15 + /********Name=SOFTRST_CON03,Offset=0x40C********/ 16 + #define SRST_NCOREPORESET0 3 17 + #define SRST_NCOREPORESET1 4 18 + #define SRST_NCOREPORESET2 5 19 + #define SRST_NCOREPORESET3 6 20 + #define SRST_NCORESET0 7 21 + #define SRST_NCORESET1 8 22 + #define SRST_NCORESET2 9 23 + #define SRST_NCORESET3 10 24 + #define SRST_NL2RESET 11 25 + /********Name=SOFTRST_CON04,Offset=0x410********/ 26 + #define SRST_DAP 12 27 + #define SRST_P_DBG_DAPLITE 13 28 + #define SRST_REF_PVTPLL_CORE 14 29 + /********Name=SOFTRST_CON05,Offset=0x414********/ 30 + #define SRST_A_CORE_BIU 15 31 + #define SRST_P_CORE_BIU 16 32 + #define SRST_H_CORE_BIU 17 33 + /********Name=SOFTRST_CON06,Offset=0x418********/ 34 + #define SRST_A_NPU_BIU 18 35 + #define SRST_H_NPU_BIU 19 36 + #define SRST_A_RKNN 20 37 + #define SRST_H_RKNN 21 38 + #define SRST_REF_PVTPLL_NPU 22 39 + /********Name=SOFTRST_CON08,Offset=0x420********/ 40 + #define SRST_A_GPU_BIU 23 41 + #define SRST_GPU 24 42 + #define SRST_REF_PVTPLL_GPU 25 43 + #define SRST_GPU_BRG_BIU 26 44 + /********Name=SOFTRST_CON09,Offset=0x424********/ 45 + #define SRST_RKVENC_CORE 27 46 + #define SRST_A_VEPU_BIU 28 47 + #define SRST_H_VEPU_BIU 29 48 + #define SRST_A_RKVENC 30 49 + #define SRST_H_RKVENC 31 50 + /********Name=SOFTRST_CON10,Offset=0x428********/ 51 + #define SRST_RKVDEC_HEVC_CA 32 52 + #define SRST_A_VDPU_BIU 33 53 + #define SRST_H_VDPU_BIU 34 54 + #define SRST_A_RKVDEC 35 55 + #define SRST_H_RKVDEC 36 56 + /********Name=SOFTRST_CON11,Offset=0x42C********/ 57 + #define SRST_A_VI_BIU 37 58 + #define SRST_H_VI_BIU 38 59 + #define SRST_P_VI_BIU 39 60 + #define SRST_ISP 40 61 + #define SRST_A_VICAP 41 62 + #define SRST_H_VICAP 42 63 + #define SRST_D_VICAP 43 64 + #define SRST_I0_VICAP 44 65 + #define SRST_I1_VICAP 45 66 + #define SRST_I2_VICAP 46 67 + #define SRST_I3_VICAP 47 68 + /********Name=SOFTRST_CON12,Offset=0x430********/ 69 + #define SRST_P_CSIHOST0 48 70 + #define SRST_P_CSIHOST1 49 71 + #define SRST_P_CSIHOST2 50 72 + #define SRST_P_CSIHOST3 51 73 + #define SRST_P_CSIPHY0 52 74 + #define SRST_P_CSIPHY1 53 75 + /********Name=SOFTRST_CON13,Offset=0x434********/ 76 + #define SRST_A_VO_BIU 54 77 + #define SRST_H_VO_BIU 55 78 + #define SRST_A_VOP 56 79 + #define SRST_H_VOP 57 80 + #define SRST_D_VOP 58 81 + #define SRST_D_VOP1 59 82 + /********Name=SOFTRST_CON14,Offset=0x438********/ 83 + #define SRST_A_RGA_BIU 60 84 + #define SRST_H_RGA_BIU 61 85 + #define SRST_A_RGA 62 86 + #define SRST_H_RGA 63 87 + #define SRST_RGA_CORE 64 88 + #define SRST_A_JDEC 65 89 + #define SRST_H_JDEC 66 90 + /********Name=SOFTRST_CON15,Offset=0x43C********/ 91 + #define SRST_B_EBK_BIU 67 92 + #define SRST_P_EBK_BIU 68 93 + #define SRST_AHB2AXI_EBC 69 94 + #define SRST_H_EBC 70 95 + #define SRST_D_EBC 71 96 + #define SRST_H_EINK 72 97 + #define SRST_P_EINK 73 98 + /********Name=SOFTRST_CON16,Offset=0x440********/ 99 + #define SRST_P_PHP_BIU 74 100 + #define SRST_A_PHP_BIU 75 101 + #define SRST_P_PCIE20 76 102 + #define SRST_PCIE20_POWERUP 77 103 + #define SRST_USB3OTG 78 104 + /********Name=SOFTRST_CON17,Offset=0x444********/ 105 + #define SRST_PIPEPHY 79 106 + /********Name=SOFTRST_CON18,Offset=0x448********/ 107 + #define SRST_A_BUS_BIU 80 108 + #define SRST_H_BUS_BIU 81 109 + #define SRST_P_BUS_BIU 82 110 + /********Name=SOFTRST_CON19,Offset=0x44C********/ 111 + #define SRST_P_I2C1 83 112 + #define SRST_P_I2C2 84 113 + #define SRST_P_I2C3 85 114 + #define SRST_P_I2C4 86 115 + #define SRST_P_I2C5 87 116 + #define SRST_I2C1 88 117 + #define SRST_I2C2 89 118 + #define SRST_I2C3 90 119 + #define SRST_I2C4 91 120 + #define SRST_I2C5 92 121 + /********Name=SOFTRST_CON20,Offset=0x450********/ 122 + #define SRST_BUS_GPIO3 93 123 + #define SRST_BUS_GPIO4 94 124 + /********Name=SOFTRST_CON21,Offset=0x454********/ 125 + #define SRST_P_TIMER 95 126 + #define SRST_TIMER0 96 127 + #define SRST_TIMER1 97 128 + #define SRST_TIMER2 98 129 + #define SRST_TIMER3 99 130 + #define SRST_TIMER4 100 131 + #define SRST_TIMER5 101 132 + #define SRST_P_STIMER 102 133 + #define SRST_STIMER0 103 134 + #define SRST_STIMER1 104 135 + /********Name=SOFTRST_CON22,Offset=0x458********/ 136 + #define SRST_P_WDTNS 105 137 + #define SRST_WDTNS 106 138 + #define SRST_P_GRF 107 139 + #define SRST_P_SGRF 108 140 + #define SRST_P_MAILBOX 109 141 + #define SRST_P_INTC 110 142 + #define SRST_A_BUS_GIC400 111 143 + #define SRST_A_BUS_GIC400_DEBUG 112 144 + /********Name=SOFTRST_CON23,Offset=0x45C********/ 145 + #define SRST_A_BUS_SPINLOCK 113 146 + #define SRST_A_DCF 114 147 + #define SRST_P_DCF 115 148 + #define SRST_F_BUS_CM0_CORE 116 149 + #define SRST_T_BUS_CM0_JTAG 117 150 + #define SRST_H_ICACHE 118 151 + #define SRST_H_DCACHE 119 152 + /********Name=SOFTRST_CON24,Offset=0x460********/ 153 + #define SRST_P_TSADC 120 154 + #define SRST_TSADC 121 155 + #define SRST_TSADCPHY 122 156 + #define SRST_P_DFT2APB 123 157 + /********Name=SOFTRST_CON25,Offset=0x464********/ 158 + #define SRST_A_GMAC 124 159 + #define SRST_P_APB2ASB_VCCIO156 125 160 + #define SRST_P_DSIPHY 126 161 + #define SRST_P_DSITX 127 162 + #define SRST_P_CPU_EMA_DET 128 163 + #define SRST_P_HASH 129 164 + #define SRST_P_TOPCRU 130 165 + /********Name=SOFTRST_CON26,Offset=0x468********/ 166 + #define SRST_P_ASB2APB_VCCIO156 131 167 + #define SRST_P_IOC_VCCIO156 132 168 + #define SRST_P_GPIO3_VCCIO156 133 169 + #define SRST_P_GPIO4_VCCIO156 134 170 + #define SRST_P_SARADC_VCCIO156 135 171 + #define SRST_SARADC_VCCIO156 136 172 + #define SRST_SARADC_VCCIO156_PHY 137 173 + /********Name=SOFTRST_CON27,Offset=0x46c********/ 174 + #define SRST_A_MAC100 138 175 + 176 + /********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ 177 + #define SRST_P_PMU0_CRU 139 178 + #define SRST_P_PMU0_PMU 140 179 + #define SRST_PMU0_PMU 141 180 + #define SRST_P_PMU0_HP_TIMER 142 181 + #define SRST_PMU0_HP_TIMER 143 182 + #define SRST_PMU0_32K_HP_TIMER 144 183 + #define SRST_P_PMU0_PVTM 145 184 + #define SRST_PMU0_PVTM 146 185 + #define SRST_P_IOC_PMUIO 147 186 + #define SRST_P_PMU0_GPIO0 148 187 + #define SRST_PMU0_GPIO0 149 188 + #define SRST_P_PMU0_GRF 150 189 + #define SRST_P_PMU0_SGRF 151 190 + /********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ 191 + #define SRST_DDR_FAIL_SAFE 152 192 + #define SRST_P_PMU0_SCRKEYGEN 153 193 + /********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ 194 + #define SRST_P_PMU0_I2C0 154 195 + #define SRST_PMU0_I2C0 155 196 + 197 + /********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ 198 + #define SRST_P_PMU1_CRU 156 199 + #define SRST_H_PMU1_MEM 157 200 + #define SRST_H_PMU1_BIU 158 201 + #define SRST_P_PMU1_BIU 159 202 + #define SRST_P_PMU1_UART0 160 203 + #define SRST_S_PMU1_UART0 161 204 + /********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ 205 + #define SRST_P_PMU1_SPI0 162 206 + #define SRST_PMU1_SPI0 163 207 + #define SRST_P_PMU1_PWM0 164 208 + #define SRST_PMU1_PWM0 165 209 + /********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ 210 + #define SRST_F_PMU1_CM0_CORE 166 211 + #define SRST_T_PMU1_CM0_JTAG 167 212 + #define SRST_P_PMU1_WDTNS 168 213 + #define SRST_PMU1_WDTNS 169 214 + #define SRST_PMU1_MAILBOX 170 215 + 216 + /********Name=DDRSOFTRST_CON00,Offset=0x20200********/ 217 + #define SRST_MSCH_BRG_BIU 171 218 + #define SRST_P_MSCH_BIU 172 219 + #define SRST_P_DDR_HWLP 173 220 + #define SRST_P_DDR_PHY 173 221 + #define SRST_P_DDR_DFICTL 174 222 + #define SRST_P_DDR_DMA2DDR 175 223 + /********Name=DDRSOFTRST_CON01,Offset=0x20204********/ 224 + #define SRST_P_DDR_MON 176 225 + #define SRST_TM_DDR_MON 177 226 + #define SRST_P_DDR_GRF 178 227 + #define SRST_P_DDR_CRU 179 228 + #define SRST_P_SUBDDR_CRU 180 229 + 230 + /********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ 231 + #define SRST_MSCH_BIU 181 232 + #define SRST_DDR_PHY 182 233 + #define SRST_DDR_DFICTL 183 234 + #define SRST_DDR_SCRAMBLE 184 235 + #define SRST_DDR_MON 185 236 + #define SRST_A_DDR_SPLIT 186 237 + #define SRST_DDR_DMA2DDR 187 238 + 239 + /********Name=PERISOFTRST_CON01,Offset=0x30404********/ 240 + #define SRST_A_PERI_BIU 188 241 + #define SRST_H_PERI_BIU 189 242 + #define SRST_P_PERI_BIU 190 243 + #define SRST_P_PERICRU 191 244 + /********Name=PERISOFTRST_CON02,Offset=0x30408********/ 245 + #define SRST_H_SAI0_8CH 192 246 + #define SRST_M_SAI0_8CH 193 247 + #define SRST_H_SAI1_8CH 194 248 + #define SRST_M_SAI1_8CH 195 249 + #define SRST_H_SAI2_2CH 196 250 + #define SRST_M_SAI2_2CH 197 251 + /********Name=PERISOFTRST_CON03,Offset=0x3040C********/ 252 + #define SRST_H_DSM 198 253 + #define SRST_DSM 199 254 + #define SRST_H_PDM 200 255 + #define SRST_M_PDM 201 256 + #define SRST_H_SPDIF 202 257 + #define SRST_M_SPDIF 203 258 + /********Name=PERISOFTRST_CON04,Offset=0x30410********/ 259 + #define SRST_H_SDMMC0 204 260 + #define SRST_H_SDMMC1 205 261 + #define SRST_H_EMMC 206 262 + #define SRST_A_EMMC 207 263 + #define SRST_C_EMMC 208 264 + #define SRST_B_EMMC 209 265 + #define SRST_T_EMMC 210 266 + #define SRST_S_SFC 211 267 + #define SRST_H_SFC 212 268 + /********Name=PERISOFTRST_CON05,Offset=0x30414********/ 269 + #define SRST_H_USB2HOST 213 270 + #define SRST_H_USB2HOST_ARB 214 271 + #define SRST_USB2HOST_UTMI 215 272 + /********Name=PERISOFTRST_CON06,Offset=0x30418********/ 273 + #define SRST_P_SPI1 216 274 + #define SRST_SPI1 217 275 + #define SRST_P_SPI2 218 276 + #define SRST_SPI2 219 277 + /********Name=PERISOFTRST_CON07,Offset=0x3041C********/ 278 + #define SRST_P_UART1 220 279 + #define SRST_P_UART2 221 280 + #define SRST_P_UART3 222 281 + #define SRST_P_UART4 223 282 + #define SRST_P_UART5 224 283 + #define SRST_P_UART6 225 284 + #define SRST_P_UART7 226 285 + #define SRST_P_UART8 227 286 + #define SRST_P_UART9 228 287 + #define SRST_S_UART1 229 288 + #define SRST_S_UART2 230 289 + /********Name=PERISOFTRST_CON08,Offset=0x30420********/ 290 + #define SRST_S_UART3 231 291 + #define SRST_S_UART4 232 292 + #define SRST_S_UART5 233 293 + #define SRST_S_UART6 234 294 + #define SRST_S_UART7 235 295 + /********Name=PERISOFTRST_CON09,Offset=0x30424********/ 296 + #define SRST_S_UART8 236 297 + #define SRST_S_UART9 237 298 + /********Name=PERISOFTRST_CON10,Offset=0x30428********/ 299 + #define SRST_P_PWM1_PERI 238 300 + #define SRST_PWM1_PERI 239 301 + #define SRST_P_PWM2_PERI 240 302 + #define SRST_PWM2_PERI 241 303 + #define SRST_P_PWM3_PERI 242 304 + #define SRST_PWM3_PERI 243 305 + /********Name=PERISOFTRST_CON11,Offset=0x3042C********/ 306 + #define SRST_P_CAN0 244 307 + #define SRST_CAN0 245 308 + #define SRST_P_CAN1 246 309 + #define SRST_CAN1 247 310 + /********Name=PERISOFTRST_CON12,Offset=0x30430********/ 311 + #define SRST_A_CRYPTO 248 312 + #define SRST_H_CRYPTO 249 313 + #define SRST_P_CRYPTO 250 314 + #define SRST_CORE_CRYPTO 251 315 + #define SRST_PKA_CRYPTO 252 316 + #define SRST_H_KLAD 253 317 + #define SRST_P_KEY_READER 254 318 + #define SRST_H_RK_RNG_NS 255 319 + #define SRST_H_RK_RNG_S 256 320 + #define SRST_H_TRNG_NS 257 321 + #define SRST_H_TRNG_S 258 322 + #define SRST_H_CRYPTO_S 259 323 + /********Name=PERISOFTRST_CON13,Offset=0x30434********/ 324 + #define SRST_P_PERI_WDT 260 325 + #define SRST_T_PERI_WDT 261 326 + #define SRST_A_SYSMEM 262 327 + #define SRST_H_BOOTROM 263 328 + #define SRST_P_PERI_GRF 264 329 + #define SRST_A_DMAC 265 330 + #define SRST_A_RKDMAC 267 331 + /********Name=PERISOFTRST_CON14,Offset=0x30438********/ 332 + #define SRST_P_OTPC_NS 268 333 + #define SRST_SBPI_OTPC_NS 269 334 + #define SRST_USER_OTPC_NS 270 335 + #define SRST_P_OTPC_S 271 336 + #define SRST_SBPI_OTPC_S 272 337 + #define SRST_USER_OTPC_S 273 338 + #define SRST_OTPC_ARB 274 339 + #define SRST_P_OTPPHY 275 340 + #define SRST_OTP_NPOR 276 341 + /********Name=PERISOFTRST_CON15,Offset=0x3043C********/ 342 + #define SRST_P_USB2PHY 277 343 + #define SRST_USB2PHY_POR 278 344 + #define SRST_USB2PHY_OTG 279 345 + #define SRST_USB2PHY_HOST 280 346 + #define SRST_P_PIPEPHY 281 347 + /********Name=PERISOFTRST_CON16,Offset=0x30440********/ 348 + #define SRST_P_SARADC 282 349 + #define SRST_SARADC 283 350 + #define SRST_SARADC_PHY 284 351 + #define SRST_P_IOC_VCCIO234 285 352 + /********Name=PERISOFTRST_CON17,Offset=0x30444********/ 353 + #define SRST_P_PERI_GPIO1 286 354 + #define SRST_P_PERI_GPIO2 287 355 + #define SRST_PERI_GPIO1 288 356 + #define SRST_PERI_GPIO2 289 357 + 358 + #endif