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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: LPAE: Introduce the 3-level page table format definitions
This patch introduces the pgtable-3level*.h files with definitions
specific to the LPAE page table format (3 levels of page tables).
Each table is 4KB and has 512 64-bit entries. An entry can point to a
40-bit physical address. The young, write and exec software bits share
the corresponding hardware bits (negated). Other software bits use spare
bits in the PTE.
The patch also changes some variable types from unsigned long or int to
pteval_t or pgprot_t.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+261
+4
arch/arm/include/asm/page.h
+4
arch/arm/include/asm/page.h
···
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#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
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extern void copy_page(void *to, const void *from);
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+
#ifdef CONFIG_ARM_LPAE
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#include <asm/pgtable-3level-types.h>
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#else
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#include <asm/pgtable-2level-types.h>
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#endif
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#endif /* CONFIG_MMU */
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+77
arch/arm/include/asm/pgtable-3level-hwdef.h
+77
arch/arm/include/asm/pgtable-3level-hwdef.h
···
1
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/*
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+
* arch/arm/include/asm/pgtable-3level-hwdef.h
3
+
*
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* Copyright (C) 2011 ARM Ltd.
5
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
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+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*
16
+
* You should have received a copy of the GNU General Public License
17
+
* along with this program; if not, write to the Free Software
18
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19
+
*/
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+
#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
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#define _ASM_PGTABLE_3LEVEL_HWDEF_H
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+
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/*
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* Hardware page table definitions.
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*
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* + Level 1/2 descriptor
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* - common
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*/
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#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
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#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
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#define PMD_BIT4 (_AT(pmdval_t, 0))
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#define PMD_DOMAIN(x) (_AT(pmdval_t, 0))
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+
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/*
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* - section
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*/
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#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2)
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#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3)
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#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
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#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
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#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11)
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#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54)
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#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0))
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#define PMD_SECT_AP_READ (_AT(pmdval_t, 0))
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#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0))
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+
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */
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#define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
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#define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
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#define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
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#define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
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/*
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* + Level 3 descriptor (PTE)
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*/
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#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
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#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
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#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
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#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
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#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
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#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
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#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */
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#define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */
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+
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/*
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* 40-bit physical address supported.
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*/
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#define PHYS_MASK_SHIFT (40)
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#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1)
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+
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#endif
+70
arch/arm/include/asm/pgtable-3level-types.h
+70
arch/arm/include/asm/pgtable-3level-types.h
···
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/*
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* arch/arm/include/asm/pgtable-3level-types.h
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*
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*
16
+
* You should have received a copy of the GNU General Public License
17
+
* along with this program; if not, write to the Free Software
18
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+
*/
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#ifndef _ASM_PGTABLE_3LEVEL_TYPES_H
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#define _ASM_PGTABLE_3LEVEL_TYPES_H
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#include <asm/types.h>
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+
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typedef u64 pteval_t;
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typedef u64 pmdval_t;
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typedef u64 pgdval_t;
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#undef STRICT_MM_TYPECHECKS
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#ifdef STRICT_MM_TYPECHECKS
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/*
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* These are used to make use of C type-checking..
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*/
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typedef struct { pteval_t pte; } pte_t;
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typedef struct { pmdval_t pmd; } pmd_t;
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typedef struct { pgdval_t pgd; } pgd_t;
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typedef struct { pteval_t pgprot; } pgprot_t;
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#define pte_val(x) ((x).pte)
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#define pmd_val(x) ((x).pmd)
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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+
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#define __pte(x) ((pte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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#else /* !STRICT_MM_TYPECHECKS */
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typedef pteval_t pte_t;
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typedef pmdval_t pmd_t;
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typedef pgdval_t pgd_t;
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typedef pteval_t pgprot_t;
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#define pte_val(x) (x)
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#define pmd_val(x) (x)
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#define pgd_val(x) (x)
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#define pgprot_val(x) (x)
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#define __pte(x) (x)
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#define __pmd(x) (x)
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#define __pgd(x) (x)
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#define __pgprot(x) (x)
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#endif /* STRICT_MM_TYPECHECKS */
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#endif /* _ASM_PGTABLE_3LEVEL_TYPES_H */
+102
arch/arm/include/asm/pgtable-3level.h
+102
arch/arm/include/asm/pgtable-3level.h
···
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/*
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* arch/arm/include/asm/pgtable-3level.h
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*
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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+
*
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* This program is free software; you can redistribute it and/or modify
8
+
* it under the terms of the GNU General Public License version 2 as
9
+
* published by the Free Software Foundation.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*
16
+
* You should have received a copy of the GNU General Public License
17
+
* along with this program; if not, write to the Free Software
18
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19
+
*/
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#ifndef _ASM_PGTABLE_3LEVEL_H
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#define _ASM_PGTABLE_3LEVEL_H
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+
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/*
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* With LPAE, there are 3 levels of page tables. Each level has 512 entries of
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* 8 bytes each, occupying a 4K page. The first level table covers a range of
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* 512GB, each entry representing 1GB. Since we are limited to 4GB input
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* address range, only 4 entries in the PGD are used.
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*
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* There are enough spare bits in a page table entry for the kernel specific
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* state.
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*/
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#define PTRS_PER_PTE 512
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#define PTRS_PER_PMD 512
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#define PTRS_PER_PGD 4
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#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
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#define PTE_HWTABLE_OFF (0)
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#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map.
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*/
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#define PGDIR_SHIFT 30
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+
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/*
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* PMD_SHIFT determines the size a middle-level page table entry can map.
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*/
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#define PMD_SHIFT 21
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+
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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+
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 21
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#define SECTION_SIZE (1UL << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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+
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#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
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+
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/*
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* "Linux" PTE definitions for LPAE.
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*
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* These bits overlap with the hardware bits but the naming is preserved for
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* consistency with the classic page table format.
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*/
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#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */
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#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
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#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
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#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
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#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
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#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
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#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */
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#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
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+
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/*
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* To be used in assembly code with the upper page attributes.
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*/
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#define L_PTE_XN_HIGH (1 << (54 - 32))
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#define L_PTE_DIRTY_HIGH (1 << (55 - 32))
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+
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
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#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
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#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
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#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
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+
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#endif /* _ASM_PGTABLE_3LEVEL_H */
+4
arch/arm/include/asm/pgtable-hwdef.h
+4
arch/arm/include/asm/pgtable-hwdef.h
+4
arch/arm/include/asm/pgtable.h
+4
arch/arm/include/asm/pgtable.h