Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

soc: mediatek: mtk-infracfg: Disable ACP on MT8192

MT8192 contains an experimental Accelerator Coherency Port
implementation, which does not work correctly but was unintentionally
enabled by default. For correct operation of the GPU, we must set a
chicken bit disabling ACP on MT8192.

Adapted from the following downstream change to the out-of-tree, legacy
Mali GPU driver:

https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5

Note this change is required for both Panfrost and the legacy kernel
driver.

Co-developed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Nick Fan <Nick.Fan@mediatek.com>
Cc: Nicolas Boichat <drinkcat@chromium.org>
Cc: Chen-Yu Tsai <wenst@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220215184651.12168-1-alyssa.rosenzweig@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

authored by

Alyssa Rosenzweig and committed by
Matthias Brugger
dcfd5192 15f17683

+22
+19
drivers/soc/mediatek/mtk-infracfg.c
··· 6 6 #include <linux/export.h> 7 7 #include <linux/jiffies.h> 8 8 #include <linux/regmap.h> 9 + #include <linux/mfd/syscon.h> 9 10 #include <linux/soc/mediatek/infracfg.h> 10 11 #include <asm/processor.h> 11 12 ··· 73 72 74 73 return ret; 75 74 } 75 + 76 + static int __init mtk_infracfg_init(void) 77 + { 78 + struct regmap *infracfg; 79 + 80 + /* 81 + * MT8192 has an experimental path to route GPU traffic to the DSU's 82 + * Accelerator Coherency Port, which is inadvertently enabled by 83 + * default. It turns out not to work, so disable it to prevent spurious 84 + * GPU faults. 85 + */ 86 + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); 87 + if (!IS_ERR(infracfg)) 88 + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, 89 + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); 90 + return 0; 91 + } 92 + postcore_initcall(mtk_infracfg_init);
+3
include/linux/soc/mediatek/infracfg.h
··· 277 277 #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 278 278 #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 279 279 280 + #define MT8192_INFRA_CTRL 0x290 281 + #define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) 282 + 280 283 #define REG_INFRA_MISC 0xf00 281 284 #define F_DDR_4GB_SUPPORT_EN BIT(13) 282 285