commit dce32c781b1c026863a254fe8123dd78c59ad984 · tjh.dev/kernel

-56

arch/sparc/Kconfig

··· 25 25 26 26 menu "General machine setup" 27 27 28 - config VT 29 - bool 30 - select INPUT 31 - default y 32 - ---help--- 33 - If you say Y here, you will get support for terminal devices with 34 - display and keyboard devices. These are called "virtual" because you 35 - can run several virtual terminals (also called virtual consoles) on 36 - one physical terminal. This is rather useful, for example one 37 - virtual terminal can collect system messages and warnings, another 38 - one can be used for a text-mode user session, and a third could run 39 - an X session, all in parallel. Switching between virtual terminals 40 - is done with certain key combinations, usually Alt-<function key>. 41 - 42 - The setterm command ("man setterm") can be used to change the 43 - properties (such as colors or beeping) of a virtual terminal. The 44 - man page console_codes(4) ("man console_codes") contains the special 45 - character sequences that can be used to change those properties 46 - directly. The fonts used on virtual terminals can be changed with 47 - the setfont ("man setfont") command and the key bindings are defined 48 - with the loadkeys ("man loadkeys") command. 49 - 50 - You need at least one virtual terminal device in order to make use 51 - of your keyboard and monitor. Therefore, only people configuring an 52 - embedded system would want to say N here in order to save some 53 - memory; the only way to log into such a system is then via a serial 54 - or network connection. 55 - 56 - If unsure, say Y, or else you won't be able to do much with your new 57 - shiny Linux system :-) 58 - 59 - config VT_CONSOLE 60 - bool 61 - default y 62 - ---help--- 63 - The system console is the device which receives all kernel messages 64 - and warnings and which allows logins in single user mode. If you 65 - answer Y here, a virtual terminal (the device used to interact with 66 - a physical terminal) can be used as system console. This is the most 67 - common mode of operations, so you should say Y here unless you want 68 - the kernel messages be output only to a serial port (in which case 69 - you should say Y to "Console on serial port", below). 70 - 71 - If you do say Y here, by default the currently visible virtual 72 - terminal (/dev/tty0) will be used as system console. You can change 73 - that with a kernel command line option such as "console=tty3" which 74 - would use the third virtual terminal as system console. (Try "man 75 - bootparam" or see the documentation of your boot loader (lilo or 76 - loadlin) about how to pass options to the kernel at boot time.) 77 - 78 - If unsure, say Y. 79 - 80 - config HW_CONSOLE 81 - bool 82 - default y 83 - 84 28 config SMP 85 29 bool "Symmetric multi-processing support (does not work on sun4/sun4c)" 86 30 depends on BROKEN

+8 -35

arch/sparc64/kernel/entry.S

··· 97 97 faddd %f0, %f2, %f4 98 98 fmuld %f0, %f2, %f6 99 99 ldxa [%g3] ASI_DMMU, %g5 100 - cplus_fptrap_insn_1: 101 - sethi %hi(0), %g2 100 + sethi %hi(sparc64_kern_sec_context), %g2 101 + ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 102 102 stxa %g2, [%g3] ASI_DMMU 103 103 membar #Sync 104 104 add %g6, TI_FPREGS + 0xc0, %g2 ··· 126 126 fzero %f34 127 127 ldxa [%g3] ASI_DMMU, %g5 128 128 add %g6, TI_FPREGS, %g1 129 - cplus_fptrap_insn_2: 130 - sethi %hi(0), %g2 129 + sethi %hi(sparc64_kern_sec_context), %g2 130 + ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 131 131 stxa %g2, [%g3] ASI_DMMU 132 132 membar #Sync 133 133 add %g6, TI_FPREGS + 0x40, %g2 ··· 153 153 3: mov SECONDARY_CONTEXT, %g3 154 154 add %g6, TI_FPREGS, %g1 155 155 ldxa [%g3] ASI_DMMU, %g5 156 - cplus_fptrap_insn_3: 157 - sethi %hi(0), %g2 156 + sethi %hi(sparc64_kern_sec_context), %g2 157 + ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 158 158 stxa %g2, [%g3] ASI_DMMU 159 159 membar #Sync 160 160 mov 0x40, %g2 ··· 319 319 stx %g3, [%g6 + TI_GSR] 320 320 mov SECONDARY_CONTEXT, %g3 321 321 ldxa [%g3] ASI_DMMU, %g5 322 - cplus_fptrap_insn_4: 323 - sethi %hi(0), %g2 322 + sethi %hi(sparc64_kern_sec_context), %g2 323 + ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 324 324 stxa %g2, [%g3] ASI_DMMU 325 325 membar #Sync 326 326 add %g6, TI_FPREGS, %g2 ··· 340 340 membar #Sync 341 341 ba,pt %xcc, etrap 342 342 wr %g0, 0, %fprs 343 - 344 - cplus_fptrap_1: 345 - sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 346 - 347 - .globl cheetah_plus_patch_fpdis 348 - cheetah_plus_patch_fpdis: 349 - /* We configure the dTLB512_0 for 4MB pages and the 350 - * dTLB512_1 for 8K pages when in context zero. 351 - */ 352 - sethi %hi(cplus_fptrap_1), %o0 353 - lduw [%o0 + %lo(cplus_fptrap_1)], %o1 354 - 355 - set cplus_fptrap_insn_1, %o2 356 - stw %o1, [%o2] 357 - flush %o2 358 - set cplus_fptrap_insn_2, %o2 359 - stw %o1, [%o2] 360 - flush %o2 361 - set cplus_fptrap_insn_3, %o2 362 - stw %o1, [%o2] 363 - flush %o2 364 - set cplus_fptrap_insn_4, %o2 365 - stw %o1, [%o2] 366 - flush %o2 367 - 368 - retl 369 - nop 370 343 371 344 /* The registers for cross calls will be: 372 345 *

+4 -47

arch/sparc64/kernel/etrap.S

··· 68 68 69 69 wrpr %g3, 0, %otherwin 70 70 wrpr %g2, 0, %wstate 71 - cplus_etrap_insn_1: 72 - sethi %hi(0), %g3 73 - sllx %g3, 32, %g3 74 - cplus_etrap_insn_2: 75 - sethi %hi(0), %g2 76 - or %g3, %g2, %g3 71 + sethi %hi(sparc64_kern_pri_context), %g2 72 + ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 77 73 stxa %g3, [%l4] ASI_DMMU 78 74 flush %l6 79 75 wr %g0, ASI_AIUS, %asi ··· 211 215 mov PRIMARY_CONTEXT, %l4 212 216 wrpr %g3, 0, %otherwin 213 217 wrpr %g2, 0, %wstate 214 - cplus_etrap_insn_3: 215 - sethi %hi(0), %g3 216 - sllx %g3, 32, %g3 217 - cplus_etrap_insn_4: 218 - sethi %hi(0), %g2 219 - or %g3, %g2, %g3 218 + sethi %hi(sparc64_kern_pri_context), %g2 219 + ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3 220 220 stxa %g3, [%l4] ASI_DMMU 221 221 flush %l6 222 222 ··· 256 264 257 265 #undef TASK_REGOFF 258 266 #undef ETRAP_PSTATE1 259 - 260 - cplus_einsn_1: 261 - sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 262 - cplus_einsn_2: 263 - sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 264 - 265 - .globl cheetah_plus_patch_etrap 266 - cheetah_plus_patch_etrap: 267 - /* We configure the dTLB512_0 for 4MB pages and the 268 - * dTLB512_1 for 8K pages when in context zero. 269 - */ 270 - sethi %hi(cplus_einsn_1), %o0 271 - sethi %hi(cplus_etrap_insn_1), %o2 272 - lduw [%o0 + %lo(cplus_einsn_1)], %o1 273 - or %o2, %lo(cplus_etrap_insn_1), %o2 274 - stw %o1, [%o2] 275 - flush %o2 276 - sethi %hi(cplus_etrap_insn_3), %o2 277 - or %o2, %lo(cplus_etrap_insn_3), %o2 278 - stw %o1, [%o2] 279 - flush %o2 280 - 281 - sethi %hi(cplus_einsn_2), %o0 282 - sethi %hi(cplus_etrap_insn_2), %o2 283 - lduw [%o0 + %lo(cplus_einsn_2)], %o1 284 - or %o2, %lo(cplus_etrap_insn_2), %o2 285 - stw %o1, [%o2] 286 - flush %o2 287 - sethi %hi(cplus_etrap_insn_4), %o2 288 - or %o2, %lo(cplus_etrap_insn_4), %o2 289 - stw %o1, [%o2] 290 - flush %o2 291 - 292 - retl 293 - nop

+5 -28

arch/sparc64/kernel/head.S

··· 325 325 1: sethi %hi(tlb_type), %g1 326 326 stw %g2, [%g1 + %lo(tlb_type)] 327 327 328 - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) 329 - ba,pt %xcc, 2f 330 - nop 331 - 332 - 1: /* Patch context register writes to support nucleus page 333 - * size correctly. 334 - */ 335 - call cheetah_plus_patch_etrap 336 - nop 337 - call cheetah_plus_patch_rtrap 338 - nop 339 - call cheetah_plus_patch_fpdis 340 - nop 341 - call cheetah_plus_patch_winfixup 342 - nop 343 - 344 - 2: /* Patch copy/page operations to cheetah optimized versions. */ 328 + /* Patch copy/page operations to cheetah optimized versions. */ 345 329 call cheetah_patch_copyops 346 330 nop 347 331 call cheetah_patch_copy_page ··· 468 484 call prom_set_trap_table 469 485 sethi %hi(sparc64_ttable_tl0), %o0 470 486 471 - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f) 472 - ba,pt %xcc, 2f 473 - nop 474 - 475 - 1: /* Start using proper page size encodings in ctx register. */ 476 - sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 487 + /* Start using proper page size encodings in ctx register. */ 488 + sethi %hi(sparc64_kern_pri_context), %g3 489 + ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 477 490 mov PRIMARY_CONTEXT, %g1 478 - sllx %g3, 32, %g3 479 - sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 480 - or %g3, %g2, %g3 481 - stxa %g3, [%g1] ASI_DMMU 491 + stxa %g2, [%g1] ASI_DMMU 482 492 membar #Sync 483 493 484 - 2: 485 494 rdpr %pstate, %o1 486 495 or %o1, PSTATE_IE, %o1 487 496 wrpr %o1, 0, %pstate

+2 -21

arch/sparc64/kernel/rtrap.S

··· 256 256 brnz,pn %l3, kern_rtt 257 257 mov PRIMARY_CONTEXT, %l7 258 258 ldxa [%l7 + %l7] ASI_DMMU, %l0 259 - cplus_rtrap_insn_1: 260 - sethi %hi(0), %l1 261 - sllx %l1, 32, %l1 259 + sethi %hi(sparc64_kern_pri_nuc_bits), %l1 260 + ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1 262 261 or %l0, %l1, %l0 263 262 stxa %l0, [%l7] ASI_DMMU 264 263 flush %g6 ··· 344 345 wr %g0, FPRS_DU, %fprs 345 346 ba,pt %xcc, rt_continue 346 347 stb %l5, [%g6 + TI_FPDEPTH] 347 - 348 - cplus_rinsn_1: 349 - sethi %uhi(CTX_CHEETAH_PLUS_NUC), %l1 350 - 351 - .globl cheetah_plus_patch_rtrap 352 - cheetah_plus_patch_rtrap: 353 - /* We configure the dTLB512_0 for 4MB pages and the 354 - * dTLB512_1 for 8K pages when in context zero. 355 - */ 356 - sethi %hi(cplus_rinsn_1), %o0 357 - sethi %hi(cplus_rtrap_insn_1), %o2 358 - lduw [%o0 + %lo(cplus_rinsn_1)], %o1 359 - or %o2, %lo(cplus_rtrap_insn_1), %o2 360 - stw %o1, [%o2] 361 - flush %o2 362 - 363 - retl 364 - nop

+2 -6

arch/sparc64/kernel/setup.c

··· 187 187 } 188 188 189 189 if ((va >= KERNBASE) && (va < (KERNBASE + (4 * 1024 * 1024)))) { 190 - unsigned long kernel_pctx = 0; 191 - 192 - if (tlb_type == cheetah_plus) 193 - kernel_pctx |= (CTX_CHEETAH_PLUS_NUC | 194 - CTX_CHEETAH_PLUS_CTX0); 190 + extern unsigned long sparc64_kern_pri_context; 195 191 196 192 /* Spitfire Errata #32 workaround */ 197 193 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 198 194 "flush %%g6" 199 195 : /* No outputs */ 200 - : "r" (kernel_pctx), 196 + : "r" (sparc64_kern_pri_context), 201 197 "r" (PRIMARY_CONTEXT), 202 198 "i" (ASI_DMMU)); 203 199

+4 -11

arch/sparc64/kernel/trampoline.S

··· 336 336 call init_irqwork_curcpu 337 337 nop 338 338 339 - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f) 340 - ba,pt %xcc, 2f 341 - nop 342 - 343 - 1: /* Start using proper page size encodings in ctx register. */ 344 - sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 339 + /* Start using proper page size encodings in ctx register. */ 340 + sethi %hi(sparc64_kern_pri_context), %g3 341 + ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 345 342 mov PRIMARY_CONTEXT, %g1 346 - sllx %g3, 32, %g3 347 - sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 348 - or %g3, %g2, %g3 349 - stxa %g3, [%g1] ASI_DMMU 343 + stxa %g2, [%g1] ASI_DMMU 350 344 membar #Sync 351 345 352 - 2: 353 346 rdpr %pstate, %o1 354 347 or %o1, PSTATE_IE, %o1 355 348 wrpr %o1, 0, %pstate

+2 -31

arch/sparc64/kernel/winfixup.S

··· 16 16 .text 17 17 18 18 set_pcontext: 19 - cplus_winfixup_insn_1: 20 - sethi %hi(0), %l1 19 + sethi %hi(sparc64_kern_pri_context), %l1 20 + ldx [%l1 + %lo(sparc64_kern_pri_context)], %l1 21 21 mov PRIMARY_CONTEXT, %g1 22 - sllx %l1, 32, %l1 23 - cplus_winfixup_insn_2: 24 - sethi %hi(0), %g2 25 - or %l1, %g2, %l1 26 22 stxa %l1, [%g1] ASI_DMMU 27 23 flush %g6 28 24 retl 29 25 nop 30 - 31 - cplus_wfinsn_1: 32 - sethi %uhi(CTX_CHEETAH_PLUS_NUC), %l1 33 - cplus_wfinsn_2: 34 - sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 35 26 36 27 .align 32 37 28 ··· 386 395 add %sp, PTREGS_OFF, %o0 387 396 ba,pt %xcc, rtrap 388 397 clr %l6 389 - 390 - 391 - .globl cheetah_plus_patch_winfixup 392 - cheetah_plus_patch_winfixup: 393 - sethi %hi(cplus_wfinsn_1), %o0 394 - sethi %hi(cplus_winfixup_insn_1), %o2 395 - lduw [%o0 + %lo(cplus_wfinsn_1)], %o1 396 - or %o2, %lo(cplus_winfixup_insn_1), %o2 397 - stw %o1, [%o2] 398 - flush %o2 399 - 400 - sethi %hi(cplus_wfinsn_2), %o0 401 - sethi %hi(cplus_winfixup_insn_2), %o2 402 - lduw [%o0 + %lo(cplus_wfinsn_2)], %o1 403 - or %o2, %lo(cplus_winfixup_insn_2), %o2 404 - stw %o1, [%o2] 405 - flush %o2 406 - 407 - retl 408 - nop

+76 -106

arch/sparc64/mm/init.c

··· 133 133 134 134 struct page *mem_map_zero __read_mostly; 135 135 136 + unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 137 + 138 + unsigned long sparc64_kern_pri_context __read_mostly; 139 + unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 140 + unsigned long sparc64_kern_sec_context __read_mostly; 141 + 136 142 int bigkernel = 0; 137 143 138 144 /* XXX Tune this... */ ··· 368 362 unsigned long data; 369 363 }; 370 364 static struct linux_prom_translation prom_trans[512] __initdata; 365 + static unsigned int prom_trans_ents __initdata; 371 366 372 367 extern unsigned long prom_boot_page; 373 368 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle); ··· 382 375 unsigned long prom_pmd_phys __read_mostly; 383 376 unsigned int swapper_pgd_zero __read_mostly; 384 377 385 - /* Allocate power-of-2 aligned chunks from the end of the 386 - * kernel image. Return physical address. 387 - */ 388 - static inline unsigned long early_alloc_phys(unsigned long size) 389 - { 390 - unsigned long base; 391 - 392 - BUILD_BUG_ON(size & (size - 1)); 393 - 394 - kern_size = (kern_size + (size - 1)) & ~(size - 1); 395 - base = kern_base + kern_size; 396 - kern_size += size; 397 - 398 - return base; 399 - } 400 - 401 - static inline unsigned long load_phys32(unsigned long pa) 402 - { 403 - unsigned long val; 404 - 405 - __asm__ __volatile__("lduwa [%1] %2, %0" 406 - : "=&r" (val) 407 - : "r" (pa), "i" (ASI_PHYS_USE_EC)); 408 - 409 - return val; 410 - } 411 - 412 - static inline unsigned long load_phys64(unsigned long pa) 413 - { 414 - unsigned long val; 415 - 416 - __asm__ __volatile__("ldxa [%1] %2, %0" 417 - : "=&r" (val) 418 - : "r" (pa), "i" (ASI_PHYS_USE_EC)); 419 - 420 - return val; 421 - } 422 - 423 - static inline void store_phys32(unsigned long pa, unsigned long val) 424 - { 425 - __asm__ __volatile__("stwa %0, [%1] %2" 426 - : /* no outputs */ 427 - : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC)); 428 - } 429 - 430 - static inline void store_phys64(unsigned long pa, unsigned long val) 431 - { 432 - __asm__ __volatile__("stxa %0, [%1] %2" 433 - : /* no outputs */ 434 - : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC)); 435 - } 378 + static pmd_t *prompmd __read_mostly; 436 379 437 380 #define BASE_PAGE_SIZE 8192 438 381 ··· 392 435 */ 393 436 unsigned long prom_virt_to_phys(unsigned long promva, int *error) 394 437 { 395 - unsigned long pmd_phys = (prom_pmd_phys + 396 - ((promva >> 23) & 0x7ff) * sizeof(pmd_t)); 397 - unsigned long pte_phys; 398 - pmd_t pmd_ent; 399 - pte_t pte_ent; 438 + pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff); 439 + pte_t *ptep; 400 440 unsigned long base; 401 441 402 - pmd_val(pmd_ent) = load_phys32(pmd_phys); 403 - if (pmd_none(pmd_ent)) { 442 + if (pmd_none(*pmdp)) { 404 443 if (error) 405 444 *error = 1; 406 445 return 0; 407 446 } 408 - 409 - pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL; 410 - pte_phys += ((promva >> 13) & 0x3ff) * sizeof(pte_t); 411 - pte_val(pte_ent) = load_phys64(pte_phys); 412 - if (!pte_present(pte_ent)) { 447 + ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff); 448 + if (!pte_present(*ptep)) { 413 449 if (error) 414 450 *error = 1; 415 451 return 0; 416 452 } 417 453 if (error) { 418 454 *error = 0; 419 - return pte_val(pte_ent); 455 + return pte_val(*ptep); 420 456 } 421 - base = pte_val(pte_ent) & _PAGE_PADDR; 422 - return (base + (promva & (BASE_PAGE_SIZE - 1))); 457 + base = pte_val(*ptep) & _PAGE_PADDR; 458 + 459 + return base + (promva & (BASE_PAGE_SIZE - 1)); 423 460 } 424 461 425 462 /* The obp translations are saved based on 8k pagesize, since obp can ··· 426 475 unsigned long vaddr; 427 476 428 477 for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) { 429 - unsigned long val, pte_phys, pmd_phys; 430 - pmd_t pmd_ent; 431 - int i; 478 + unsigned long val; 479 + pmd_t *pmd; 480 + pte_t *pte; 432 481 433 - pmd_phys = (prom_pmd_phys + 434 - (((vaddr >> 23) & 0x7ff) * sizeof(pmd_t))); 435 - pmd_val(pmd_ent) = load_phys32(pmd_phys); 436 - if (pmd_none(pmd_ent)) { 437 - pte_phys = early_alloc_phys(BASE_PAGE_SIZE); 438 - 439 - for (i = 0; i < BASE_PAGE_SIZE / sizeof(pte_t); i++) 440 - store_phys64(pte_phys+i*sizeof(pte_t),0); 441 - 442 - pmd_val(pmd_ent) = pte_phys >> 11UL; 443 - store_phys32(pmd_phys, pmd_val(pmd_ent)); 482 + pmd = prompmd + ((vaddr >> 23) & 0x7ff); 483 + if (pmd_none(*pmd)) { 484 + pte = __alloc_bootmem(BASE_PAGE_SIZE, BASE_PAGE_SIZE, 485 + PAGE_SIZE); 486 + if (!pte) 487 + prom_halt(); 488 + memset(pte, 0, BASE_PAGE_SIZE); 489 + pmd_set(pmd, pte); 444 490 } 445 - 446 - pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL; 447 - pte_phys += (((vaddr >> 13) & 0x3ff) * sizeof(pte_t)); 491 + pte = (pte_t *) __pmd_page(*pmd) + ((vaddr >> 13) & 0x3ff); 448 492 449 493 val = data; 450 494 ··· 447 501 if (tlb_type == spitfire) 448 502 val &= ~0x0003fe0000000000UL; 449 503 450 - store_phys64(pte_phys, val | _PAGE_MODIFIED); 504 + set_pte_at(&init_mm, vaddr, pte, 505 + __pte(val | _PAGE_MODIFIED)); 451 506 452 507 data += BASE_PAGE_SIZE; 453 508 } ··· 461 514 } 462 515 463 516 #define OBP_PMD_SIZE 2048 464 - static void __init build_obp_pgtable(int prom_trans_ents) 517 + static void __init build_obp_pgtable(void) 465 518 { 466 519 unsigned long i; 467 520 468 - prom_pmd_phys = early_alloc_phys(OBP_PMD_SIZE); 469 - for (i = 0; i < OBP_PMD_SIZE; i += 4) 470 - store_phys32(prom_pmd_phys + i, 0); 521 + prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, PAGE_SIZE); 522 + if (!prompmd) 523 + prom_halt(); 524 + 525 + memset(prompmd, 0, OBP_PMD_SIZE); 526 + 527 + prom_pmd_phys = __pa(prompmd); 471 528 472 529 for (i = 0; i < prom_trans_ents; i++) { 473 530 unsigned long start, end; ··· 491 540 /* Read OBP translations property into 'prom_trans[]'. 492 541 * Return the number of entries. 493 542 */ 494 - static int __init read_obp_translations(void) 543 + static void __init read_obp_translations(void) 495 544 { 496 545 int n, node; 497 546 ··· 512 561 prom_printf("prom_mappings: Couldn't get property.\n"); 513 562 prom_halt(); 514 563 } 564 + 515 565 n = n / sizeof(struct linux_prom_translation); 516 - return n; 566 + 567 + prom_trans_ents = n; 517 568 } 518 569 519 570 static void __init remap_kernel(void) ··· 535 582 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr); 536 583 prom_itlb_load(tlb_ent, tte_data, tte_vaddr); 537 584 if (bigkernel) { 538 - prom_dtlb_load(tlb_ent - 1, 585 + tlb_ent -= 1; 586 + prom_dtlb_load(tlb_ent, 539 587 tte_data + 0x400000, 540 588 tte_vaddr + 0x400000); 541 - prom_itlb_load(tlb_ent - 1, 589 + prom_itlb_load(tlb_ent, 542 590 tte_data + 0x400000, 543 591 tte_vaddr + 0x400000); 544 592 } 593 + sparc64_highest_unlocked_tlb_ent = tlb_ent - 1; 594 + if (tlb_type == cheetah_plus) { 595 + sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 596 + CTX_CHEETAH_PLUS_NUC); 597 + sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 598 + sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 599 + } 545 600 } 546 601 547 - static void __init inherit_prom_mappings(void) 548 - { 549 - int n; 550 602 551 - n = read_obp_translations(); 552 - build_obp_pgtable(n); 603 + static void __init inherit_prom_mappings_pre(void) 604 + { 605 + read_obp_translations(); 553 606 554 607 /* Now fixup OBP's idea about where we really are mapped. */ 555 608 prom_printf("Remapping the kernel... "); 556 609 remap_kernel(); 557 610 558 611 prom_printf("done.\n"); 612 + } 559 613 614 + static void __init inherit_prom_mappings_post(void) 615 + { 616 + build_obp_pgtable(); 560 617 register_prom_callbacks(); 561 618 } 562 619 ··· 751 788 } 752 789 } 753 790 if (tlb_type == spitfire) { 754 - int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel; 755 - for (i = 0; i < high; i++) { 791 + int high = sparc64_highest_unlocked_tlb_ent; 792 + for (i = 0; i <= high; i++) { 756 793 unsigned long data; 757 794 758 795 /* Spitfire Errata #32 workaround */ ··· 840 877 } 841 878 } 842 879 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 843 - int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel; 880 + int high = sparc64_highest_unlocked_tlb_ent; 844 881 845 - for (i = 0; i < high; i++) { 882 + for (i = 0; i <= high; i++) { 846 883 unsigned long data; 847 884 848 885 data = cheetah_get_ldtlb_data(i); ··· 1519 1556 1520 1557 swapper_pgd_zero = pgd_val(swapper_pg_dir[0]); 1521 1558 1522 - /* Inherit non-locked OBP mappings. */ 1523 - inherit_prom_mappings(); 1559 + inherit_prom_mappings_pre(); 1524 1560 1525 1561 /* Ok, we can use our TLB miss and window trap handlers safely. 1526 1562 * We need to do a quick peek here to see if we are on StarFire ··· 1530 1568 extern void setup_tba(int); 1531 1569 setup_tba(this_is_starfire); 1532 1570 } 1533 - 1534 - inherit_locked_prom_mappings(1); 1535 - 1536 1571 __flush_tlb_all(); 1572 + 1573 + /* Everything from this point forward, until we are done with 1574 + * inherit_prom_mappings_post(), must complete successfully 1575 + * without calling into the firmware. The firwmare page tables 1576 + * have not been built, but we are running on the Linux kernel's 1577 + * trap table. 1578 + */ 1537 1579 1538 1580 /* Setup bootmem... */ 1539 1581 pages_avail = 0; 1540 1582 last_valid_pfn = end_pfn = bootmem_init(&pages_avail); 1583 + 1584 + inherit_prom_mappings_post(); 1585 + 1586 + inherit_locked_prom_mappings(1); 1541 1587 1542 1588 #ifdef CONFIG_DEBUG_PAGEALLOC 1543 1589 kernel_physical_mapping_init();