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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
Blackfin: add support for the DBG (debug output) pseudo insn
Another pseudo insn used by Blackfin simulators. Also factor some now
common register lookup code out of the DBGA handlers.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
authored by Robin Getz and committed by Mike Frysinger dc89d97f 6a4110c2
+1
arch/blackfin/include/asm/pseudo_instructions.h
+1
arch/blackfin/include/asm/pseudo_instructions.h
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-18
arch/blackfin/kernel/pseudodbg.c
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-18
arch/blackfin/kernel/pseudodbg.c
···
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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/*
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* Unfortunately, the pt_regs structure is not laid out the same way as the
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* hardware register file, so we need to do some fix ups.
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*/
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static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
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{
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long *val = &fp->r0;
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/* Only do Dregs and Pregs for now */
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if (grp > 1)
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return false;
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if (grp == 0 || (grp == 1 && reg < 6))
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val -= (reg + 8 * grp);
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else if (grp == 1 && reg == 6)
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val = &fp->usp;
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else if (grp == 1 && reg == 7)
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val = &fp->fp;
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*value = *val;
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return true;
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}
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#define PseudoDbg_Assert_opcode 0xf0000000
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#define PseudoDbg_Assert_expected_bits 0
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#define PseudoDbg_Assert_expected_mask 0xffff
···
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#define PseudoDbg_Assert_code_bits 27
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#define PseudoDbg_Assert_code_mask 0x1f
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/*
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* DBGA - debug assert
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*/
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bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
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{
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int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
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int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
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int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
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int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
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long *value = &fp->r0;
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long value;
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if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
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return false;
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/* Only do Dregs and Pregs for now */
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if (grp > 1)
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if (!fix_up_reg(fp, &value, grp, regtest))
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return false;
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/*
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* Unfortunately, the pt_regs structure is not laid out the same way as the
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* hardware register file, so we need to do some fix ups.
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*/
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if (grp == 0 || (grp == 1 && regtest < 6))
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value -= (regtest + 8 * grp);
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else if (grp == 1 && regtest == 6)
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value = &fp->usp;
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else if (grp == 1 && regtest == 7)
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value = &fp->fp;
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if (dbgop == 0 || dbgop == 2) {
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/* DBGA ( regs_lo , uimm16 ) */
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/* DBGAL ( regs , uimm16 ) */
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if (expected != (*value & 0xFFFF)) {
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if (expected != (value & 0xFFFF)) {
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pr_notice("DBGA (%s%i.L,0x%x) failure, got 0x%x\n", grp ? "P" : "R",
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regtest, expected, (unsigned int)(*value & 0xFFFF));
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regtest, expected, (unsigned int)(value & 0xFFFF));
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return false;
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}
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} else if (dbgop == 1 || dbgop == 3) {
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/* DBGA ( regs_hi , uimm16 ) */
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/* DBGAH ( regs , uimm16 ) */
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if (expected != ((*value >> 16) & 0xFFFF)) {
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if (expected != ((value >> 16) & 0xFFFF)) {
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pr_notice("DBGA (%s%i.H,0x%x) failure, got 0x%x\n", grp ? "P" : "R",
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regtest, expected, (unsigned int)((*value >> 16) & 0xFFFF));
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regtest, expected, (unsigned int)((value >> 16) & 0xFFFF));
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return false;
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}
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}
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fp->pc += 4;
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return true;
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}
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#define PseudoDbg_opcode 0xf8000000
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#define PseudoDbg_reg_bits 0
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#define PseudoDbg_reg_mask 0x7
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#define PseudoDbg_grp_bits 3
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#define PseudoDbg_grp_mask 0x7
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#define PseudoDbg_fn_bits 6
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#define PseudoDbg_fn_mask 0x3
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#define PseudoDbg_code_bits 8
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#define PseudoDbg_code_mask 0xff
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/*
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* DBG - debug (dump a register value out)
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*/
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bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
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{
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int grp, fn, reg;
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long value;
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if ((opcode & 0xFF000000) != PseudoDbg_opcode)
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return false;
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opcode >>= 16;
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grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
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fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
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reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
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if (!fix_up_reg(fp, &value, grp, reg))
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return false;
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pr_notice("DBG %s%d = %08lx\n", grp ? "P" : "R", reg, value);
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fp->pc += 2;
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return true;
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}
+2
arch/blackfin/kernel/traps.c
+2
arch/blackfin/kernel/traps.c