tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: STi: DT: STiH41x: Convert all uppercase non-defines to lowercase

Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

authored by

Lee Jones and committed by
Maxime Coquelin dc62bfdf c759e5f7

+329 -329
+160 -160
arch/arm/boot/dts/stih415-pinctrl.dtsi
··· 11 11 / { 12 12 13 13 aliases { 14 - gpio0 = &PIO0; 15 - gpio1 = &PIO1; 16 - gpio2 = &PIO2; 17 - gpio3 = &PIO3; 18 - gpio4 = &PIO4; 19 - gpio5 = &PIO5; 20 - gpio6 = &PIO6; 21 - gpio7 = &PIO7; 22 - gpio8 = &PIO8; 23 - gpio9 = &PIO9; 24 - gpio10 = &PIO10; 25 - gpio11 = &PIO11; 26 - gpio12 = &PIO12; 27 - gpio13 = &PIO13; 28 - gpio14 = &PIO14; 29 - gpio15 = &PIO15; 30 - gpio16 = &PIO16; 31 - gpio17 = &PIO17; 32 - gpio18 = &PIO18; 33 - gpio19 = &PIO100; 34 - gpio20 = &PIO101; 35 - gpio21 = &PIO102; 36 - gpio22 = &PIO103; 37 - gpio23 = &PIO104; 38 - gpio24 = &PIO105; 39 - gpio25 = &PIO106; 40 - gpio26 = &PIO107; 14 + gpio0 = &pio0; 15 + gpio1 = &pio1; 16 + gpio2 = &pio2; 17 + gpio3 = &pio3; 18 + gpio4 = &pio4; 19 + gpio5 = &pio5; 20 + gpio6 = &pio6; 21 + gpio7 = &pio7; 22 + gpio8 = &pio8; 23 + gpio9 = &pio9; 24 + gpio10 = &pio10; 25 + gpio11 = &pio11; 26 + gpio12 = &pio12; 27 + gpio13 = &pio13; 28 + gpio14 = &pio14; 29 + gpio15 = &pio15; 30 + gpio16 = &pio16; 31 + gpio17 = &pio17; 32 + gpio18 = &pio18; 33 + gpio19 = &pio100; 34 + gpio20 = &pio101; 35 + gpio21 = &pio102; 36 + gpio22 = &pio103; 37 + gpio23 = &pio104; 38 + gpio24 = &pio105; 39 + gpio25 = &pio106; 40 + gpio26 = &pio107; 41 41 }; 42 42 43 43 soc { ··· 52 52 interrupt-names = "irqmux"; 53 53 ranges = <0 0xfe610000 0x5000>; 54 54 55 - PIO0: gpio@fe610000 { 55 + pio0: gpio@fe610000 { 56 56 gpio-controller; 57 57 #gpio-cells = <1>; 58 58 interrupt-controller; ··· 60 60 reg = <0 0x100>; 61 61 st,bank-name = "PIO0"; 62 62 }; 63 - PIO1: gpio@fe611000 { 63 + pio1: gpio@fe611000 { 64 64 gpio-controller; 65 65 #gpio-cells = <1>; 66 66 interrupt-controller; ··· 68 68 reg = <0x1000 0x100>; 69 69 st,bank-name = "PIO1"; 70 70 }; 71 - PIO2: gpio@fe612000 { 71 + pio2: gpio@fe612000 { 72 72 gpio-controller; 73 73 #gpio-cells = <1>; 74 74 interrupt-controller; ··· 76 76 reg = <0x2000 0x100>; 77 77 st,bank-name = "PIO2"; 78 78 }; 79 - PIO3: gpio@fe613000 { 79 + pio3: gpio@fe613000 { 80 80 gpio-controller; 81 81 #gpio-cells = <1>; 82 82 interrupt-controller; ··· 84 84 reg = <0x3000 0x100>; 85 85 st,bank-name = "PIO3"; 86 86 }; 87 - PIO4: gpio@fe614000 { 87 + pio4: gpio@fe614000 { 88 88 gpio-controller; 89 89 #gpio-cells = <1>; 90 90 interrupt-controller; ··· 96 96 sbc_serial1 { 97 97 pinctrl_sbc_serial1:sbc_serial1 { 98 98 st,pins { 99 - tx = <&PIO2 6 ALT3 OUT>; 100 - rx = <&PIO2 7 ALT3 IN>; 99 + tx = <&pio2 6 ALT3 OUT>; 100 + rx = <&pio2 7 ALT3 IN>; 101 101 }; 102 102 }; 103 103 }; ··· 105 105 keyscan { 106 106 pinctrl_keyscan: keyscan { 107 107 st,pins { 108 - keyin0 = <&PIO0 2 ALT2 IN>; 109 - keyin1 = <&PIO0 3 ALT2 IN>; 110 - keyin2 = <&PIO0 4 ALT2 IN>; 111 - keyin3 = <&PIO2 6 ALT2 IN>; 108 + keyin0 = <&pio0 2 ALT2 IN>; 109 + keyin1 = <&pio0 3 ALT2 IN>; 110 + keyin2 = <&pio0 4 ALT2 IN>; 111 + keyin3 = <&pio2 6 ALT2 IN>; 112 112 113 - keyout0 = <&PIO1 6 ALT2 OUT>; 114 - keyout1 = <&PIO1 7 ALT2 OUT>; 115 - keyout2 = <&PIO0 6 ALT2 OUT>; 116 - keyout3 = <&PIO2 7 ALT2 OUT>; 113 + keyout0 = <&pio1 6 ALT2 OUT>; 114 + keyout1 = <&pio1 7 ALT2 OUT>; 115 + keyout2 = <&pio0 6 ALT2 OUT>; 116 + keyout3 = <&pio2 7 ALT2 OUT>; 117 117 }; 118 118 }; 119 119 }; ··· 121 121 sbc_i2c0 { 122 122 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 123 123 st,pins { 124 - sda = <&PIO4 6 ALT1 BIDIR>; 125 - scl = <&PIO4 5 ALT1 BIDIR>; 124 + sda = <&pio4 6 ALT1 BIDIR>; 125 + scl = <&pio4 5 ALT1 BIDIR>; 126 126 }; 127 127 }; 128 128 }; ··· 130 130 sbc_i2c1 { 131 131 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 132 132 st,pins { 133 - sda = <&PIO3 2 ALT2 BIDIR>; 134 - scl = <&PIO3 1 ALT2 BIDIR>; 133 + sda = <&pio3 2 ALT2 BIDIR>; 134 + scl = <&pio3 1 ALT2 BIDIR>; 135 135 }; 136 136 }; 137 137 }; ··· 139 139 rc{ 140 140 pinctrl_ir: ir0 { 141 141 st,pins { 142 - ir = <&PIO4 0 ALT2 IN>; 142 + ir = <&pio4 0 ALT2 IN>; 143 143 }; 144 144 }; 145 145 }; ··· 147 147 gmac1 { 148 148 pinctrl_mii1: mii1 { 149 149 st,pins { 150 - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 151 - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 152 - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 153 - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 154 - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 155 - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 156 - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 157 - col = <&PIO0 7 ALT1 IN BYPASS 1000>; 158 - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 159 - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 160 - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 161 - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 162 - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 163 - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 164 - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 165 - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 166 - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 167 - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 168 - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 169 - phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; 150 + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 151 + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 152 + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 153 + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 154 + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 155 + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 156 + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 157 + col = <&pio0 7 ALT1 IN BYPASS 1000>; 158 + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 159 + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 160 + crs = <&pio1 2 ALT1 IN BYPASS 1000>; 161 + mdint = <&pio1 3 ALT1 IN BYPASS 0>; 162 + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 163 + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 164 + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 165 + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 166 + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 167 + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 168 + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 169 + phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; 170 170 }; 171 171 }; 172 172 173 173 pinctrl_rgmii1: rgmii1-0 { 174 174 st,pins { 175 - txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; 176 - txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; 177 - txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; 178 - txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; 179 - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 180 - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 181 - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 182 - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 183 - rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; 184 - rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; 185 - rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; 186 - rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; 175 + txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; 176 + txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; 177 + txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; 178 + txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; 179 + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; 180 + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 181 + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 182 + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 183 + rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; 184 + rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; 185 + rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; 186 + rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; 187 187 188 - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 189 - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 190 - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 188 + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; 189 + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 190 + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; 191 191 192 - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 192 + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; 193 193 }; 194 194 }; 195 195 }; ··· 206 206 interrupt-names = "irqmux"; 207 207 ranges = <0 0xfee00000 0x8000>; 208 208 209 - PIO5: gpio@fee00000 { 209 + pio5: gpio@fee00000 { 210 210 gpio-controller; 211 211 #gpio-cells = <1>; 212 212 interrupt-controller; ··· 214 214 reg = <0 0x100>; 215 215 st,bank-name = "PIO5"; 216 216 }; 217 - PIO6: gpio@fee01000 { 217 + pio6: gpio@fee01000 { 218 218 gpio-controller; 219 219 #gpio-cells = <1>; 220 220 interrupt-controller; ··· 222 222 reg = <0x1000 0x100>; 223 223 st,bank-name = "PIO6"; 224 224 }; 225 - PIO7: gpio@fee02000 { 225 + pio7: gpio@fee02000 { 226 226 gpio-controller; 227 227 #gpio-cells = <1>; 228 228 interrupt-controller; ··· 230 230 reg = <0x2000 0x100>; 231 231 st,bank-name = "PIO7"; 232 232 }; 233 - PIO8: gpio@fee03000 { 233 + pio8: gpio@fee03000 { 234 234 gpio-controller; 235 235 #gpio-cells = <1>; 236 236 interrupt-controller; ··· 238 238 reg = <0x3000 0x100>; 239 239 st,bank-name = "PIO8"; 240 240 }; 241 - PIO9: gpio@fee04000 { 241 + pio9: gpio@fee04000 { 242 242 gpio-controller; 243 243 #gpio-cells = <1>; 244 244 interrupt-controller; ··· 246 246 reg = <0x4000 0x100>; 247 247 st,bank-name = "PIO9"; 248 248 }; 249 - PIO10: gpio@fee05000 { 249 + pio10: gpio@fee05000 { 250 250 gpio-controller; 251 251 #gpio-cells = <1>; 252 252 interrupt-controller; ··· 254 254 reg = <0x5000 0x100>; 255 255 st,bank-name = "PIO10"; 256 256 }; 257 - PIO11: gpio@fee06000 { 257 + pio11: gpio@fee06000 { 258 258 gpio-controller; 259 259 #gpio-cells = <1>; 260 260 interrupt-controller; ··· 262 262 reg = <0x6000 0x100>; 263 263 st,bank-name = "PIO11"; 264 264 }; 265 - PIO12: gpio@fee07000 { 265 + pio12: gpio@fee07000 { 266 266 gpio-controller; 267 267 #gpio-cells = <1>; 268 268 interrupt-controller; ··· 274 274 i2c0 { 275 275 pinctrl_i2c0_default: i2c0-default { 276 276 st,pins { 277 - sda = <&PIO9 3 ALT1 BIDIR>; 278 - scl = <&PIO9 2 ALT1 BIDIR>; 277 + sda = <&pio9 3 ALT1 BIDIR>; 278 + scl = <&pio9 2 ALT1 BIDIR>; 279 279 }; 280 280 }; 281 281 }; ··· 283 283 i2c1 { 284 284 pinctrl_i2c1_default: i2c1-default { 285 285 st,pins { 286 - sda = <&PIO12 1 ALT1 BIDIR>; 287 - scl = <&PIO12 0 ALT1 BIDIR>; 286 + sda = <&pio12 1 ALT1 BIDIR>; 287 + scl = <&pio12 0 ALT1 BIDIR>; 288 288 }; 289 289 }; 290 290 }; ··· 301 301 interrupt-names = "irqmux"; 302 302 ranges = <0 0xfe820000 0x8000>; 303 303 304 - PIO13: gpio@fe820000 { 304 + pio13: gpio@fe820000 { 305 305 gpio-controller; 306 306 #gpio-cells = <1>; 307 307 interrupt-controller; ··· 309 309 reg = <0 0x100>; 310 310 st,bank-name = "PIO13"; 311 311 }; 312 - PIO14: gpio@fe821000 { 312 + pio14: gpio@fe821000 { 313 313 gpio-controller; 314 314 #gpio-cells = <1>; 315 315 interrupt-controller; ··· 317 317 reg = <0x1000 0x100>; 318 318 st,bank-name = "PIO14"; 319 319 }; 320 - PIO15: gpio@fe822000 { 320 + pio15: gpio@fe822000 { 321 321 gpio-controller; 322 322 #gpio-cells = <1>; 323 323 interrupt-controller; ··· 325 325 reg = <0x2000 0x100>; 326 326 st,bank-name = "PIO15"; 327 327 }; 328 - PIO16: gpio@fe823000 { 328 + pio16: gpio@fe823000 { 329 329 gpio-controller; 330 330 #gpio-cells = <1>; 331 331 interrupt-controller; ··· 333 333 reg = <0x3000 0x100>; 334 334 st,bank-name = "PIO16"; 335 335 }; 336 - PIO17: gpio@fe824000 { 336 + pio17: gpio@fe824000 { 337 337 gpio-controller; 338 338 #gpio-cells = <1>; 339 339 interrupt-controller; ··· 341 341 reg = <0x4000 0x100>; 342 342 st,bank-name = "PIO17"; 343 343 }; 344 - PIO18: gpio@fe825000 { 344 + pio18: gpio@fe825000 { 345 345 gpio-controller; 346 346 #gpio-cells = <1>; 347 347 interrupt-controller; ··· 353 353 serial2 { 354 354 pinctrl_serial2: serial2-0 { 355 355 st,pins { 356 - tx = <&PIO17 4 ALT2 OUT>; 357 - rx = <&PIO17 5 ALT2 IN>; 356 + tx = <&pio17 4 ALT2 OUT>; 357 + rx = <&pio17 5 ALT2 IN>; 358 358 }; 359 359 }; 360 360 }; ··· 362 362 gmac0{ 363 363 pinctrl_mii0: mii0 { 364 364 st,pins { 365 - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 366 - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 365 + mdint = <&pio13 6 ALT2 IN BYPASS 0>; 366 + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 367 367 368 - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 369 - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 370 - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 371 - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 368 + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 369 + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 370 + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 371 + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 372 372 373 - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 374 - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 375 - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 376 - col = <&PIO15 3 ALT2 IN BYPASS 1000>; 377 - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 378 - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 373 + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; 374 + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 375 + crs = <&pio15 2 ALT2 IN BYPASS 1000>; 376 + col = <&pio15 3 ALT2 IN BYPASS 1000>; 377 + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; 378 + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; 379 379 380 - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 381 - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 382 - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 383 - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 384 - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 385 - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 386 - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 387 - phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; 380 + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 381 + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 382 + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 383 + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 384 + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 385 + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 386 + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; 387 + phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; 388 388 389 389 }; 390 390 }; 391 391 392 392 pinctrl_gmii0: gmii0 { 393 393 st,pins { 394 - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 395 - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 396 - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 397 - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 394 + mdint = <&pio13 6 ALT2 IN BYPASS 0>; 395 + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; 396 + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; 397 + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 398 398 399 - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 400 - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 401 - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 402 - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 403 - txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 404 - txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 405 - txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 406 - txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 399 + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 400 + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 401 + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 402 + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 403 + txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 404 + txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 405 + txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 406 + txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 407 407 408 - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 409 - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 410 - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 411 - col = <&PIO15 3 ALT2 IN BYPASS 1000>; 412 - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 413 - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 408 + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; 409 + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 410 + crs = <&pio15 2 ALT2 IN BYPASS 1000>; 411 + col = <&pio15 3 ALT2 IN BYPASS 1000>; 412 + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 413 + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 414 414 415 - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 416 - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 417 - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 418 - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 419 - rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 420 - rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 421 - rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 422 - rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 415 + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 416 + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 417 + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 418 + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 419 + rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 420 + rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 421 + rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 422 + rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 423 423 424 - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 425 - clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 426 - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 424 + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; 425 + clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; 426 + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; 427 427 428 428 429 429 }; ··· 442 442 interrupt-names = "irqmux"; 443 443 ranges = <0 0xfd6b0000 0x3000>; 444 444 445 - PIO100: gpio@fd6b0000 { 445 + pio100: gpio@fd6b0000 { 446 446 gpio-controller; 447 447 #gpio-cells = <1>; 448 448 interrupt-controller; ··· 450 450 reg = <0 0x100>; 451 451 st,bank-name = "PIO100"; 452 452 }; 453 - PIO101: gpio@fd6b1000 { 453 + pio101: gpio@fd6b1000 { 454 454 gpio-controller; 455 455 #gpio-cells = <1>; 456 456 interrupt-controller; ··· 458 458 reg = <0x1000 0x100>; 459 459 st,bank-name = "PIO101"; 460 460 }; 461 - PIO102: gpio@fd6b2000 { 461 + pio102: gpio@fd6b2000 { 462 462 gpio-controller; 463 463 #gpio-cells = <1>; 464 464 interrupt-controller; ··· 479 479 interrupt-names = "irqmux"; 480 480 ranges = <0 0xfd330000 0x5000>; 481 481 482 - PIO103: gpio@fd330000 { 482 + pio103: gpio@fd330000 { 483 483 gpio-controller; 484 484 #gpio-cells = <1>; 485 485 interrupt-controller; ··· 487 487 reg = <0 0x100>; 488 488 st,bank-name = "PIO103"; 489 489 }; 490 - PIO104: gpio@fd331000 { 490 + pio104: gpio@fd331000 { 491 491 gpio-controller; 492 492 #gpio-cells = <1>; 493 493 interrupt-controller; ··· 495 495 reg = <0x1000 0x100>; 496 496 st,bank-name = "PIO104"; 497 497 }; 498 - PIO105: gpio@fd332000 { 498 + pio105: gpio@fd332000 { 499 499 gpio-controller; 500 500 #gpio-cells = <1>; 501 501 interrupt-controller; ··· 503 503 reg = <0x2000 0x100>; 504 504 st,bank-name = "PIO105"; 505 505 }; 506 - PIO106: gpio@fd333000 { 506 + pio106: gpio@fd333000 { 507 507 gpio-controller; 508 508 #gpio-cells = <1>; 509 509 interrupt-controller; ··· 511 511 reg = <0x3000 0x100>; 512 512 st,bank-name = "PIO106"; 513 513 }; 514 - PIO107: gpio@fd334000 { 514 + pio107: gpio@fd334000 { 515 515 gpio-controller; 516 516 #gpio-cells = <1>; 517 517 interrupt-controller;
+3 -3
arch/arm/boot/dts/stih416-b2020e.dts
··· 19 19 red { 20 20 #gpio-cells = <1>; 21 21 label = "Front Panel LED"; 22 - gpios = <&PIO4 1>; 22 + gpios = <&pio4 1>; 23 23 linux,default-trigger = "heartbeat"; 24 24 }; 25 25 green { 26 - gpios = <&PIO1 3>; 26 + gpios = <&pio1 3>; 27 27 default-state = "off"; 28 28 }; 29 29 }; 30 30 31 31 ethernet1: dwmac@fef08000 { 32 - snps,reset-gpio = <&PIO0 7>; 32 + snps,reset-gpio = <&pio0 7>; 33 33 }; 34 34 }; 35 35 };
+160 -160
arch/arm/boot/dts/stih416-pinctrl.dtsi
··· 12 12 / { 13 13 14 14 aliases { 15 - gpio0 = &PIO0; 16 - gpio1 = &PIO1; 17 - gpio2 = &PIO2; 18 - gpio3 = &PIO3; 19 - gpio4 = &PIO4; 20 - gpio5 = &PIO40; 21 - gpio6 = &PIO5; 22 - gpio7 = &PIO6; 23 - gpio8 = &PIO7; 24 - gpio9 = &PIO8; 25 - gpio10 = &PIO9; 26 - gpio11 = &PIO10; 27 - gpio12 = &PIO11; 28 - gpio13 = &PIO12; 29 - gpio14 = &PIO30; 30 - gpio15 = &PIO31; 31 - gpio16 = &PIO13; 32 - gpio17 = &PIO14; 33 - gpio18 = &PIO15; 34 - gpio19 = &PIO16; 35 - gpio20 = &PIO17; 36 - gpio21 = &PIO18; 37 - gpio22 = &PIO100; 38 - gpio23 = &PIO101; 39 - gpio24 = &PIO102; 40 - gpio25 = &PIO103; 41 - gpio26 = &PIO104; 42 - gpio27 = &PIO105; 43 - gpio28 = &PIO106; 44 - gpio29 = &PIO107; 15 + gpio0 = &pio0; 16 + gpio1 = &pio1; 17 + gpio2 = &pio2; 18 + gpio3 = &pio3; 19 + gpio4 = &pio4; 20 + gpio5 = &pio40; 21 + gpio6 = &pio5; 22 + gpio7 = &pio6; 23 + gpio8 = &pio7; 24 + gpio9 = &pio8; 25 + gpio10 = &pio9; 26 + gpio11 = &pio10; 27 + gpio12 = &pio11; 28 + gpio13 = &pio12; 29 + gpio14 = &pio30; 30 + gpio15 = &pio31; 31 + gpio16 = &pio13; 32 + gpio17 = &pio14; 33 + gpio18 = &pio15; 34 + gpio19 = &pio16; 35 + gpio20 = &pio17; 36 + gpio21 = &pio18; 37 + gpio22 = &pio100; 38 + gpio23 = &pio101; 39 + gpio24 = &pio102; 40 + gpio25 = &pio103; 41 + gpio26 = &pio104; 42 + gpio27 = &pio105; 43 + gpio28 = &pio106; 44 + gpio29 = &pio107; 45 45 }; 46 46 47 47 soc { ··· 56 56 interrupt-names = "irqmux"; 57 57 ranges = <0 0xfe610000 0x6000>; 58 58 59 - PIO0: gpio@fe610000 { 59 + pio0: gpio@fe610000 { 60 60 gpio-controller; 61 61 #gpio-cells = <1>; 62 62 interrupt-controller; ··· 64 64 reg = <0 0x100>; 65 65 st,bank-name = "PIO0"; 66 66 }; 67 - PIO1: gpio@fe611000 { 67 + pio1: gpio@fe611000 { 68 68 gpio-controller; 69 69 #gpio-cells = <1>; 70 70 interrupt-controller; ··· 72 72 reg = <0x1000 0x100>; 73 73 st,bank-name = "PIO1"; 74 74 }; 75 - PIO2: gpio@fe612000 { 75 + pio2: gpio@fe612000 { 76 76 gpio-controller; 77 77 #gpio-cells = <1>; 78 78 interrupt-controller; ··· 80 80 reg = <0x2000 0x100>; 81 81 st,bank-name = "PIO2"; 82 82 }; 83 - PIO3: gpio@fe613000 { 83 + pio3: gpio@fe613000 { 84 84 gpio-controller; 85 85 #gpio-cells = <1>; 86 86 interrupt-controller; ··· 88 88 reg = <0x3000 0x100>; 89 89 st,bank-name = "PIO3"; 90 90 }; 91 - PIO4: gpio@fe614000 { 91 + pio4: gpio@fe614000 { 92 92 gpio-controller; 93 93 #gpio-cells = <1>; 94 94 interrupt-controller; ··· 96 96 reg = <0x4000 0x100>; 97 97 st,bank-name = "PIO4"; 98 98 }; 99 - PIO40: gpio@fe615000 { 99 + pio40: gpio@fe615000 { 100 100 gpio-controller; 101 101 #gpio-cells = <1>; 102 102 interrupt-controller; ··· 109 109 rc{ 110 110 pinctrl_ir: ir0 { 111 111 st,pins { 112 - ir = <&PIO4 0 ALT2 IN>; 112 + ir = <&pio4 0 ALT2 IN>; 113 113 }; 114 114 }; 115 115 }; 116 116 sbc_serial1 { 117 117 pinctrl_sbc_serial1: sbc_serial1 { 118 118 st,pins { 119 - tx = <&PIO2 6 ALT3 OUT>; 120 - rx = <&PIO2 7 ALT3 IN>; 119 + tx = <&pio2 6 ALT3 OUT>; 120 + rx = <&pio2 7 ALT3 IN>; 121 121 }; 122 122 }; 123 123 }; ··· 125 125 keyscan { 126 126 pinctrl_keyscan: keyscan { 127 127 st,pins { 128 - keyin0 = <&PIO0 2 ALT2 IN>; 129 - keyin1 = <&PIO0 3 ALT2 IN>; 130 - keyin2 = <&PIO0 4 ALT2 IN>; 131 - keyin3 = <&PIO2 6 ALT2 IN>; 128 + keyin0 = <&pio0 2 ALT2 IN>; 129 + keyin1 = <&pio0 3 ALT2 IN>; 130 + keyin2 = <&pio0 4 ALT2 IN>; 131 + keyin3 = <&pio2 6 ALT2 IN>; 132 132 133 - keyout0 = <&PIO1 6 ALT2 OUT>; 134 - keyout1 = <&PIO1 7 ALT2 OUT>; 135 - keyout2 = <&PIO0 6 ALT2 OUT>; 136 - keyout3 = <&PIO2 7 ALT2 OUT>; 133 + keyout0 = <&pio1 6 ALT2 OUT>; 134 + keyout1 = <&pio1 7 ALT2 OUT>; 135 + keyout2 = <&pio0 6 ALT2 OUT>; 136 + keyout3 = <&pio2 7 ALT2 OUT>; 137 137 }; 138 138 }; 139 139 }; ··· 141 141 sbc_i2c0 { 142 142 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 143 143 st,pins { 144 - sda = <&PIO4 6 ALT1 BIDIR>; 145 - scl = <&PIO4 5 ALT1 BIDIR>; 144 + sda = <&pio4 6 ALT1 BIDIR>; 145 + scl = <&pio4 5 ALT1 BIDIR>; 146 146 }; 147 147 }; 148 148 }; ··· 150 150 sbc_i2c1 { 151 151 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 152 152 st,pins { 153 - sda = <&PIO3 2 ALT2 BIDIR>; 154 - scl = <&PIO3 1 ALT2 BIDIR>; 153 + sda = <&pio3 2 ALT2 BIDIR>; 154 + scl = <&pio3 1 ALT2 BIDIR>; 155 155 }; 156 156 }; 157 157 }; ··· 159 159 gmac1 { 160 160 pinctrl_mii1: mii1 { 161 161 st,pins { 162 - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 163 - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 164 - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 165 - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 166 - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 167 - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 168 - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 169 - col = <&PIO0 7 ALT1 IN BYPASS 1000>; 162 + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 163 + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 164 + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 165 + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 166 + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 167 + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 168 + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 169 + col = <&pio0 7 ALT1 IN BYPASS 1000>; 170 170 171 - mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; 172 - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 173 - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 174 - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 175 - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 176 - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 177 - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 178 - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 171 + mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; 172 + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 173 + crs = <&pio1 2 ALT1 IN BYPASS 1000>; 174 + mdint = <&pio1 3 ALT1 IN BYPASS 0>; 175 + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 176 + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 177 + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 178 + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 179 179 180 - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 181 - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 182 - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 183 - phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; 180 + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 181 + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 182 + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 183 + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; 184 184 }; 185 185 }; 186 186 pinctrl_rgmii1: rgmii1-0 { 187 187 st,pins { 188 - txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; 189 - txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; 190 - txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; 191 - txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; 192 - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 193 - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 188 + txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; 189 + txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; 190 + txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; 191 + txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; 192 + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; 193 + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; 194 194 195 - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 196 - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 197 - rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; 198 - rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; 199 - rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; 200 - rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; 195 + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; 196 + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; 197 + rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; 198 + rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; 199 + rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; 200 + rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; 201 201 202 - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 203 - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 204 - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 202 + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; 203 + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 204 + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; 205 205 206 - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 206 + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; 207 207 }; 208 208 }; 209 209 }; ··· 220 220 interrupt-names = "irqmux"; 221 221 ranges = <0 0xfee00000 0x10000>; 222 222 223 - PIO5: gpio@fee00000 { 223 + pio5: gpio@fee00000 { 224 224 gpio-controller; 225 225 #gpio-cells = <1>; 226 226 interrupt-controller; ··· 228 228 reg = <0 0x100>; 229 229 st,bank-name = "PIO5"; 230 230 }; 231 - PIO6: gpio@fee01000 { 231 + pio6: gpio@fee01000 { 232 232 gpio-controller; 233 233 #gpio-cells = <1>; 234 234 interrupt-controller; ··· 236 236 reg = <0x1000 0x100>; 237 237 st,bank-name = "PIO6"; 238 238 }; 239 - PIO7: gpio@fee02000 { 239 + pio7: gpio@fee02000 { 240 240 gpio-controller; 241 241 #gpio-cells = <1>; 242 242 interrupt-controller; ··· 244 244 reg = <0x2000 0x100>; 245 245 st,bank-name = "PIO7"; 246 246 }; 247 - PIO8: gpio@fee03000 { 247 + pio8: gpio@fee03000 { 248 248 gpio-controller; 249 249 #gpio-cells = <1>; 250 250 interrupt-controller; ··· 252 252 reg = <0x3000 0x100>; 253 253 st,bank-name = "PIO8"; 254 254 }; 255 - PIO9: gpio@fee04000 { 255 + pio9: gpio@fee04000 { 256 256 gpio-controller; 257 257 #gpio-cells = <1>; 258 258 interrupt-controller; ··· 260 260 reg = <0x4000 0x100>; 261 261 st,bank-name = "PIO9"; 262 262 }; 263 - PIO10: gpio@fee05000 { 263 + pio10: gpio@fee05000 { 264 264 gpio-controller; 265 265 #gpio-cells = <1>; 266 266 interrupt-controller; ··· 268 268 reg = <0x5000 0x100>; 269 269 st,bank-name = "PIO10"; 270 270 }; 271 - PIO11: gpio@fee06000 { 271 + pio11: gpio@fee06000 { 272 272 gpio-controller; 273 273 #gpio-cells = <1>; 274 274 interrupt-controller; ··· 276 276 reg = <0x6000 0x100>; 277 277 st,bank-name = "PIO11"; 278 278 }; 279 - PIO12: gpio@fee07000 { 279 + pio12: gpio@fee07000 { 280 280 gpio-controller; 281 281 #gpio-cells = <1>; 282 282 interrupt-controller; ··· 284 284 reg = <0x7000 0x100>; 285 285 st,bank-name = "PIO12"; 286 286 }; 287 - PIO30: gpio@fee08000 { 287 + pio30: gpio@fee08000 { 288 288 gpio-controller; 289 289 #gpio-cells = <1>; 290 290 interrupt-controller; ··· 292 292 reg = <0x8000 0x100>; 293 293 st,bank-name = "PIO30"; 294 294 }; 295 - PIO31: gpio@fee09000 { 295 + pio31: gpio@fee09000 { 296 296 gpio-controller; 297 297 #gpio-cells = <1>; 298 298 interrupt-controller; ··· 304 304 serial2-oe { 305 305 pinctrl_serial2_oe: serial2-1 { 306 306 st,pins { 307 - output-enable = <&PIO11 3 ALT2 OUT>; 307 + output-enable = <&pio11 3 ALT2 OUT>; 308 308 }; 309 309 }; 310 310 }; ··· 312 312 i2c0 { 313 313 pinctrl_i2c0_default: i2c0-default { 314 314 st,pins { 315 - sda = <&PIO9 3 ALT1 BIDIR>; 316 - scl = <&PIO9 2 ALT1 BIDIR>; 315 + sda = <&pio9 3 ALT1 BIDIR>; 316 + scl = <&pio9 2 ALT1 BIDIR>; 317 317 }; 318 318 }; 319 319 }; ··· 321 321 i2c1 { 322 322 pinctrl_i2c1_default: i2c1-default { 323 323 st,pins { 324 - sda = <&PIO12 1 ALT1 BIDIR>; 325 - scl = <&PIO12 0 ALT1 BIDIR>; 324 + sda = <&pio12 1 ALT1 BIDIR>; 325 + scl = <&pio12 0 ALT1 BIDIR>; 326 326 }; 327 327 }; 328 328 }; ··· 330 330 fsm { 331 331 pinctrl_fsm: fsm { 332 332 st,pins { 333 - spi-fsm-clk = <&PIO12 2 ALT1 OUT>; 334 - spi-fsm-cs = <&PIO12 3 ALT1 OUT>; 335 - spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; 336 - spi-fsm-miso = <&PIO12 5 ALT1 IN>; 337 - spi-fsm-hol = <&PIO12 6 ALT1 OUT>; 338 - spi-fsm-wp = <&PIO12 7 ALT1 OUT>; 333 + spi-fsm-clk = <&pio12 2 ALT1 OUT>; 334 + spi-fsm-cs = <&pio12 3 ALT1 OUT>; 335 + spi-fsm-mosi = <&pio12 4 ALT1 OUT>; 336 + spi-fsm-miso = <&pio12 5 ALT1 IN>; 337 + spi-fsm-hol = <&pio12 6 ALT1 OUT>; 338 + spi-fsm-wp = <&pio12 7 ALT1 OUT>; 339 339 }; 340 340 }; 341 341 }; ··· 352 352 interrupt-names = "irqmux"; 353 353 ranges = <0 0xfe820000 0x6000>; 354 354 355 - PIO13: gpio@fe820000 { 355 + pio13: gpio@fe820000 { 356 356 gpio-controller; 357 357 #gpio-cells = <1>; 358 358 interrupt-controller; ··· 360 360 reg = <0 0x100>; 361 361 st,bank-name = "PIO13"; 362 362 }; 363 - PIO14: gpio@fe821000 { 363 + pio14: gpio@fe821000 { 364 364 gpio-controller; 365 365 #gpio-cells = <1>; 366 366 interrupt-controller; ··· 368 368 reg = <0x1000 0x100>; 369 369 st,bank-name = "PIO14"; 370 370 }; 371 - PIO15: gpio@fe822000 { 371 + pio15: gpio@fe822000 { 372 372 gpio-controller; 373 373 #gpio-cells = <1>; 374 374 interrupt-controller; ··· 376 376 reg = <0x2000 0x100>; 377 377 st,bank-name = "PIO15"; 378 378 }; 379 - PIO16: gpio@fe823000 { 379 + pio16: gpio@fe823000 { 380 380 gpio-controller; 381 381 #gpio-cells = <1>; 382 382 interrupt-controller; ··· 384 384 reg = <0x3000 0x100>; 385 385 st,bank-name = "PIO16"; 386 386 }; 387 - PIO17: gpio@fe824000 { 387 + pio17: gpio@fe824000 { 388 388 gpio-controller; 389 389 #gpio-cells = <1>; 390 390 interrupt-controller; ··· 392 392 reg = <0x4000 0x100>; 393 393 st,bank-name = "PIO17"; 394 394 }; 395 - PIO18: gpio@fe825000 { 395 + pio18: gpio@fe825000 { 396 396 gpio-controller; 397 397 #gpio-cells = <1>; 398 398 interrupt-controller; ··· 405 405 serial2 { 406 406 pinctrl_serial2: serial2-0 { 407 407 st,pins { 408 - tx = <&PIO17 4 ALT2 OUT>; 409 - rx = <&PIO17 5 ALT2 IN>; 408 + tx = <&pio17 4 ALT2 OUT>; 409 + rx = <&pio17 5 ALT2 IN>; 410 410 }; 411 411 }; 412 412 }; ··· 414 414 gmac0 { 415 415 pinctrl_mii0: mii0 { 416 416 st,pins { 417 - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 418 - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 419 - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 420 - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 421 - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 422 - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 417 + mdint = <&pio13 6 ALT2 IN BYPASS 0>; 418 + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 419 + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 420 + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 421 + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 422 + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 423 423 424 - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 425 - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 426 - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 427 - col = <&PIO15 3 ALT2 IN BYPASS 1000>; 428 - mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; 429 - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 424 + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; 425 + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 426 + crs = <&pio15 2 ALT2 IN BYPASS 1000>; 427 + col = <&pio15 3 ALT2 IN BYPASS 1000>; 428 + mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; 429 + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; 430 430 431 - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 432 - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 433 - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 434 - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 435 - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 436 - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 437 - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 438 - phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; 431 + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 432 + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 433 + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 434 + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 435 + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 436 + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 437 + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; 438 + phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; 439 439 }; 440 440 }; 441 441 ··· 445 445 }; 446 446 pinctrl_rgmii0: rgmii0 { 447 447 st,pins { 448 - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 449 - txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; 450 - txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; 451 - txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; 452 - txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; 453 - txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; 454 - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 448 + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; 449 + txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; 450 + txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; 451 + txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; 452 + txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; 453 + txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; 454 + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; 455 455 456 - mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; 457 - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 456 + mdio = <&pio15 4 ALT2 OUT BYPASS 0>; 457 + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; 458 458 459 - rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; 460 - rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; 461 - rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; 462 - rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; 463 - rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; 464 - rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 459 + rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; 460 + rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; 461 + rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; 462 + rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; 463 + rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; 464 + rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; 465 465 466 - clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 466 + clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; 467 467 }; 468 468 }; 469 469 }; ··· 480 480 interrupt-names = "irqmux"; 481 481 ranges = <0 0xfd6b0000 0x3000>; 482 482 483 - PIO100: gpio@fd6b0000 { 483 + pio100: gpio@fd6b0000 { 484 484 gpio-controller; 485 485 #gpio-cells = <1>; 486 486 interrupt-controller; ··· 488 488 reg = <0 0x100>; 489 489 st,bank-name = "PIO100"; 490 490 }; 491 - PIO101: gpio@fd6b1000 { 491 + pio101: gpio@fd6b1000 { 492 492 gpio-controller; 493 493 #gpio-cells = <1>; 494 494 interrupt-controller; ··· 496 496 reg = <0x1000 0x100>; 497 497 st,bank-name = "PIO101"; 498 498 }; 499 - PIO102: gpio@fd6b2000 { 499 + pio102: gpio@fd6b2000 { 500 500 gpio-controller; 501 501 #gpio-cells = <1>; 502 502 interrupt-controller; ··· 517 517 interrupt-names = "irqmux"; 518 518 ranges = <0 0xfd330000 0x5000>; 519 519 520 - PIO103: gpio@fd330000 { 520 + pio103: gpio@fd330000 { 521 521 gpio-controller; 522 522 #gpio-cells = <1>; 523 523 interrupt-controller; ··· 525 525 reg = <0 0x100>; 526 526 st,bank-name = "PIO103"; 527 527 }; 528 - PIO104: gpio@fd331000 { 528 + pio104: gpio@fd331000 { 529 529 gpio-controller; 530 530 #gpio-cells = <1>; 531 531 interrupt-controller; ··· 533 533 reg = <0x1000 0x100>; 534 534 st,bank-name = "PIO104"; 535 535 }; 536 - PIO105: gpio@fd332000 { 536 + pio105: gpio@fd332000 { 537 537 gpio-controller; 538 538 #gpio-cells = <1>; 539 539 interrupt-controller; ··· 541 541 reg = <0x2000 0x100>; 542 542 st,bank-name = "PIO105"; 543 543 }; 544 - PIO106: gpio@fd333000 { 544 + pio106: gpio@fd333000 { 545 545 gpio-controller; 546 546 #gpio-cells = <1>; 547 547 interrupt-controller; ··· 550 550 st,bank-name = "PIO106"; 551 551 }; 552 552 553 - PIO107: gpio@fd334000 { 553 + pio107: gpio@fd334000 { 554 554 gpio-controller; 555 555 #gpio-cells = <1>; 556 556 interrupt-controller;
+3 -3
arch/arm/boot/dts/stih41x-b2000.dtsi
··· 35 35 fp_led { 36 36 #gpio-cells = <1>; 37 37 label = "Front Panel LED"; 38 - gpios = <&PIO105 7>; 38 + gpios = <&pio105 7>; 39 39 linux,default-trigger = "heartbeat"; 40 40 }; 41 41 }; ··· 55 55 phy-mode = "mii"; 56 56 pinctrl-0 = <&pinctrl_mii0>; 57 57 58 - snps,reset-gpio = <&PIO106 2>; 58 + snps,reset-gpio = <&pio106 2>; 59 59 snps,reset-active-low; 60 60 snps,reset-delays-us = <0 10000 10000>; 61 61 }; ··· 65 65 phy-mode = "mii"; 66 66 st,tx-retime-src = "txclk"; 67 67 68 - snps,reset-gpio = <&PIO4 7>; 68 + snps,reset-gpio = <&pio4 7>; 69 69 snps,reset-active-low; 70 70 snps,reset-delays-us = <0 10000 10000>; 71 71 };
+3 -3
arch/arm/boot/dts/stih41x-b2020.dtsi
··· 32 32 red { 33 33 #gpio-cells = <1>; 34 34 label = "Front Panel LED"; 35 - gpios = <&PIO4 1>; 35 + gpios = <&pio4 1>; 36 36 linux,default-trigger = "heartbeat"; 37 37 }; 38 38 green { 39 - gpios = <&PIO4 7>; 39 + gpios = <&pio4 7>; 40 40 default-state = "off"; 41 41 }; 42 42 }; ··· 68 68 phy-mode = "rgmii-id"; 69 69 max-speed = <1000>; 70 70 st,tx-retime-src = "clk_125"; 71 - snps,reset-gpio = <&PIO3 0>; 71 + snps,reset-gpio = <&pio3 0>; 72 72 snps,reset-active-low; 73 73 snps,reset-delays-us = <0 10000 10000>; 74 74