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docs: Debugging390.txt: convert table to ascii artwork
The first bit/value table inside the document is very
hard to read and won't fit ReST format. Also, some columns aren't
properly aligned.
Convert it to a nice ascii artwork table with makes it easier to
read as plain text and is compatible with ReST format parser
on Sphinx.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
authored by
Mauro Carvalho Chehab
and committed by
Heiko Carstens
dc3988f4
04310324
+120
-90
+120
-90
Documentation/s390/Debugging390.txt
+120
-90
Documentation/s390/Debugging390.txt
···
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have a logical=physical mapping for the address you are
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currently running at.
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Bit Value
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s/390 z/Architecture
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0 0 Reserved ( must be 0 ) otherwise specification exception occurs.
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-
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1 1 Program Event Recording 1 PER enabled,
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PER is used to facilitate debugging e.g. single stepping.
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-
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2-4 2-4 Reserved ( must be 0 ).
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-
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5 5 Dynamic address translation 1=DAT on.
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6 6 Input/Output interrupt Mask
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7 7 External interrupt Mask used primarily for interprocessor
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signalling and clock interrupts.
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8-11 8-11 PSW Key used for complex memory protection mechanism
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(not used under linux)
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12 12 1 on s/390 0 on z/Architecture
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13 13 Machine Check Mask 1=enable machine check interrupts
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14 14 Wait State. Set this to 1 to stop the processor except for
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interrupts and give time to other LPARS. Used in CPU idle in
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the kernel to increase overall usage of processor resources.
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-
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15 15 Problem state ( if set to 1 certain instructions are disabled )
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all linux user programs run with this bit 1
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( useful info for debugging under VM ).
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16-17 16-17 Address Space Control
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00 Primary Space Mode:
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The register CR1 contains the primary address-space control ele-
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ment (PASCE), which points to the primary space region/segment
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table origin.
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01 Access register mode
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10 Secondary Space Mode:
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The register CR7 contains the secondary address-space control
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element (SASCE), which points to the secondary space region or
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segment table origin.
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11 Home Space Mode:
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The register CR13 contains the home space address-space control
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element (HASCE), which points to the home space region/segment
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table origin.
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See "Address Spaces on Linux for s/390 & z/Architecture" below
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for more information about address space usage in Linux.
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18-19 18-19 Condition codes (CC)
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20 20 Fixed point overflow mask if 1=FPU exceptions for this event
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occur ( normally 0 )
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21 21 Decimal overflow mask if 1=FPU exceptions for this event occur
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( normally 0 )
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22 22 Exponent underflow mask if 1=FPU exceptions for this event occur
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( normally 0 )
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-
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23 23 Significance Mask if 1=FPU exceptions for this event occur
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( normally 0 )
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24-31 24-30 Reserved Must be 0.
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31 Extended Addressing Mode
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32 Basic Addressing Mode
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Used to set addressing mode
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PSW 31 PSW 32
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0 0 24 bit
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0 1 31 bit
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1 1 64 bit
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32 1=31 bit addressing mode 0=24 bit addressing mode (for backward
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compatibility), linux always runs with this bit set to 1
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33-64 Instruction address.
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33-63 Reserved must be 0
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64-127 Address
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In 24 bits mode bits 64-103=0 bits 104-127 Address
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In 31 bits mode bits 64-96=0 bits 97-127 Address
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Note: unlike 31 bit mode on s/390 bit 96 must be zero
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when loading the address with LPSWE otherwise a
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specification exception occurs, LPSW is fully backward
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compatible.
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+
+-------------------------+-------------------------------------------------+
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+
| Bit | |
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+--------+----------------+ Value |
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| s/390 | z/Architecture | |
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+========+================+=================================================+
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| 0 | 0 | Reserved (must be 0) otherwise specification |
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| | | exception occurs. |
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+--------+----------------+-------------------------------------------------+
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| 1 | 1 | Program Event Recording 1 PER enabled, |
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| | | PER is used to facilitate debugging e.g. |
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| | | single stepping. |
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+--------+----------------+-------------------------------------------------+
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| 2-4 | 2-4 | Reserved (must be 0). |
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+
+--------+----------------+-------------------------------------------------+
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| 5 | 5 | Dynamic address translation 1=DAT on. |
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+
+--------+----------------+-------------------------------------------------+
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+
| 6 | 6 | Input/Output interrupt Mask |
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+
+--------+----------------+-------------------------------------------------+
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+
| 7 | 7 | External interrupt Mask used primarily for |
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| | | interprocessor signalling and clock interrupts. |
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+
+--------+----------------+-------------------------------------------------+
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| 8-11 | 8-11 | PSW Key used for complex memory protection |
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| | | mechanism (not used under linux) |
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+--------+----------------+-------------------------------------------------+
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| 12 | 12 | 1 on s/390 0 on z/Architecture |
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+--------+----------------+-------------------------------------------------+
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| 13 | 13 | Machine Check Mask 1=enable machine check |
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| | | interrupts |
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+--------+----------------+-------------------------------------------------+
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| 14 | 14 | Wait State. Set this to 1 to stop the processor |
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| | | except for interrupts and give time to other |
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+
| | | LPARS. Used in CPU idle in the kernel to |
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| | | increase overall usage of processor resources. |
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+
+--------+----------------+-------------------------------------------------+
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+
| 15 | 15 | Problem state (if set to 1 certain instructions |
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+
| | | are disabled). All linux user programs run with |
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| | | this bit 1 (useful info for debugging under VM).|
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+--------+----------------+-------------------------------------------------+
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+
| 16-17 | 16-17 | Address Space Control |
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| | | |
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| | | 00 Primary Space Mode: |
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| | | |
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| | | The register CR1 contains the primary |
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+
| | | address-space control element (PASCE), which |
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+
| | | points to the primary space region/segment |
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+
| | | table origin. |
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+
| | | |
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| | | 01 Access register mode |
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+
| | | |
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+
| | | 10 Secondary Space Mode: |
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| | | |
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| | | The register CR7 contains the secondary |
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| | | address-space control element (SASCE), which |
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+
| | | points to the secondary space region or |
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+
| | | segment table origin. |
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+
| | | |
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+
| | | 11 Home Space Mode: |
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| | | |
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| | | The register CR13 contains the home space |
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+
| | | address-space control element (HASCE), which |
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| | | points to the home space region/segment |
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+
| | | table origin. |
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+
| | | |
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| | | See "Address Spaces on Linux for s/390 & |
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| | | z/Architecture" below for more information |
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| | | about address space usage in Linux. |
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+
+--------+----------------+-------------------------------------------------+
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+
| 18-19 | 18-19 | Condition codes (CC) |
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+--------+----------------+-------------------------------------------------+
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+
| 20 | 20 | Fixed point overflow mask if 1=FPU exceptions |
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+
| | | for this event occur (normally 0) |
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+
+--------+----------------+-------------------------------------------------+
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+
| 21 | 21 | Decimal overflow mask if 1=FPU exceptions for |
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+
| | | this event occur (normally 0) |
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+
+--------+----------------+-------------------------------------------------+
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+
| 22 | 22 | Exponent underflow mask if 1=FPU exceptions |
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+
| | | for this event occur (normally 0) |
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+
+--------+----------------+-------------------------------------------------+
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+
| 23 | 23 | Significance Mask if 1=FPU exceptions for this |
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+
| | | event occur (normally 0) |
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+
+--------+----------------+-------------------------------------------------+
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| 24-31 | 24-30 | Reserved Must be 0. |
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| +----------------+-------------------------------------------------+
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| | 31 | Extended Addressing Mode |
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| +----------------+-------------------------------------------------+
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| | 32 | Basic Addressing Mode |
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| | | |
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| | | Used to set addressing mode |
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| | | |
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| | | +---------+----------+----------+ |
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| | | | PSW 31 | PSW 32 | | |
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| | | +---------+----------+----------+ |
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| | | | 0 | 0 | 24 bit | |
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| | | +---------+----------+----------+ |
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| | | | 0 | 1 | 31 bit | |
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| | | +---------+----------+----------+ |
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| | | | 1 | 1 | 64 bit | |
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| | | +---------+----------+----------+ |
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+--------+----------------+-------------------------------------------------+
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| 32 | | 1=31 bit addressing mode 0=24 bit addressing |
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| | | mode (for backward compatibility), linux |
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| | | always runs with this bit set to 1 |
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+--------+----------------+-------------------------------------------------+
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| 33-64 | | Instruction address. |
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| +----------------+-------------------------------------------------+
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| | 33-63 | Reserved must be 0 |
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| +----------------+-------------------------------------------------+
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| | 64-127 | Address |
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| | | |
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| | | - In 24 bits mode bits 64-103=0 bits 104-127 |
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| | | Address |
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| | | - In 31 bits mode bits 64-96=0 bits 97-127 |
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| | | Address |
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| | | |
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| | | Note: |
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| | | unlike 31 bit mode on s/390 bit 96 must be |
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| | | zero when loading the address with LPSWE |
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+
| | | otherwise a specification exception occurs, |
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+
| | | LPSW is fully backward compatible. |
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+
+--------+----------------+-------------------------------------------------+
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Prefix Page(s)
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