Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

powerpc: implement GPIO LIB API on CPM1 Freescale SoC.

This patch implement GPIO LIB support for the CPM1 GPIOs.

Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

authored by

Jochen Friedrich and committed by
Kumar Gala
dc2380ec e193325e

+272 -5
+10
arch/powerpc/platforms/8xx/Kconfig
··· 105 105 106 106 If in doubt, say Y here. 107 107 108 + config 8xx_GPIO 109 + bool "GPIO API Support" 110 + select GENERIC_GPIO 111 + select ARCH_REQUIRE_GPIOLIB 112 + help 113 + Saying Y here will cause the ports on an MPC8xx processor to be used 114 + with the GPIO API. If you say N here, the kernel needs less memory. 115 + 116 + If in doubt, say Y here. 117 + 108 118 config 8xx_CPU6 109 119 bool "CPU6 Silicon Errata (860 Pre Rev. C)" 110 120 help
+262 -5
arch/powerpc/sysdev/cpm1.c
··· 30 30 #include <linux/interrupt.h> 31 31 #include <linux/irq.h> 32 32 #include <linux/module.h> 33 + #include <linux/spinlock.h> 33 34 #include <asm/page.h> 34 35 #include <asm/pgtable.h> 35 36 #include <asm/8xx_immap.h> ··· 42 41 #include <asm/cpm.h> 43 42 44 43 #include <asm/fs_pd.h> 44 + 45 + #ifdef CONFIG_8xx_GPIO 46 + #include <linux/of_gpio.h> 47 + #endif 45 48 46 49 #define CPM_MAP_SIZE (0x4000) 47 50 ··· 295 290 __be16 res[3]; 296 291 }; 297 292 298 - struct cpm_ioport32 { 299 - __be32 dir, par, sor; 293 + struct cpm_ioport32b { 294 + __be32 dir, par, odr, dat; 295 + }; 296 + 297 + struct cpm_ioport32e { 298 + __be32 dir, par, sor, odr, dat; 300 299 }; 301 300 302 301 static void cpm1_set_pin32(int port, int pin, int flags) 303 302 { 304 - struct cpm_ioport32 __iomem *iop; 303 + struct cpm_ioport32e __iomem *iop; 305 304 pin = 1 << (31 - pin); 306 305 307 306 if (port == CPM_PORTB) 308 - iop = (struct cpm_ioport32 __iomem *) 307 + iop = (struct cpm_ioport32e __iomem *) 309 308 &mpc8xx_immr->im_cpm.cp_pbdir; 310 309 else 311 - iop = (struct cpm_ioport32 __iomem *) 310 + iop = (struct cpm_ioport32e __iomem *) 312 311 &mpc8xx_immr->im_cpm.cp_pedir; 313 312 314 313 if (flags & CPM_PIN_OUTPUT) ··· 507 498 508 499 return 0; 509 500 } 501 + 502 + /* 503 + * GPIO LIB API implementation 504 + */ 505 + #ifdef CONFIG_8xx_GPIO 506 + 507 + struct cpm1_gpio16_chip { 508 + struct of_mm_gpio_chip mm_gc; 509 + spinlock_t lock; 510 + 511 + /* shadowed data register to clear/set bits safely */ 512 + u16 cpdata; 513 + }; 514 + 515 + static inline struct cpm1_gpio16_chip * 516 + to_cpm1_gpio16_chip(struct of_mm_gpio_chip *mm_gc) 517 + { 518 + return container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); 519 + } 520 + 521 + static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) 522 + { 523 + struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); 524 + struct cpm_ioport16 __iomem *iop = mm_gc->regs; 525 + 526 + cpm1_gc->cpdata = in_be16(&iop->dat); 527 + } 528 + 529 + static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) 530 + { 531 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 532 + struct cpm_ioport16 __iomem *iop = mm_gc->regs; 533 + u16 pin_mask; 534 + 535 + pin_mask = 1 << (15 - gpio); 536 + 537 + return !!(in_be16(&iop->dat) & pin_mask); 538 + } 539 + 540 + static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) 541 + { 542 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 543 + struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc); 544 + struct cpm_ioport16 __iomem *iop = mm_gc->regs; 545 + unsigned long flags; 546 + u16 pin_mask = 1 << (15 - gpio); 547 + 548 + spin_lock_irqsave(&cpm1_gc->lock, flags); 549 + 550 + if (value) 551 + cpm1_gc->cpdata |= pin_mask; 552 + else 553 + cpm1_gc->cpdata &= ~pin_mask; 554 + 555 + out_be16(&iop->dat, cpm1_gc->cpdata); 556 + 557 + spin_unlock_irqrestore(&cpm1_gc->lock, flags); 558 + } 559 + 560 + static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 561 + { 562 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 563 + struct cpm_ioport16 __iomem *iop = mm_gc->regs; 564 + u16 pin_mask; 565 + 566 + pin_mask = 1 << (15 - gpio); 567 + 568 + setbits16(&iop->dir, pin_mask); 569 + 570 + cpm1_gpio16_set(gc, gpio, val); 571 + 572 + return 0; 573 + } 574 + 575 + static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) 576 + { 577 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 578 + struct cpm_ioport16 __iomem *iop = mm_gc->regs; 579 + u16 pin_mask; 580 + 581 + pin_mask = 1 << (15 - gpio); 582 + 583 + clrbits16(&iop->dir, pin_mask); 584 + 585 + return 0; 586 + } 587 + 588 + int cpm1_gpiochip_add16(struct device_node *np) 589 + { 590 + struct cpm1_gpio16_chip *cpm1_gc; 591 + struct of_mm_gpio_chip *mm_gc; 592 + struct of_gpio_chip *of_gc; 593 + struct gpio_chip *gc; 594 + 595 + cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 596 + if (!cpm1_gc) 597 + return -ENOMEM; 598 + 599 + spin_lock_init(&cpm1_gc->lock); 600 + 601 + mm_gc = &cpm1_gc->mm_gc; 602 + of_gc = &mm_gc->of_gc; 603 + gc = &of_gc->gc; 604 + 605 + mm_gc->save_regs = cpm1_gpio16_save_regs; 606 + of_gc->gpio_cells = 2; 607 + gc->ngpio = 16; 608 + gc->direction_input = cpm1_gpio16_dir_in; 609 + gc->direction_output = cpm1_gpio16_dir_out; 610 + gc->get = cpm1_gpio16_get; 611 + gc->set = cpm1_gpio16_set; 612 + 613 + return of_mm_gpiochip_add(np, mm_gc); 614 + } 615 + 616 + struct cpm1_gpio32_chip { 617 + struct of_mm_gpio_chip mm_gc; 618 + spinlock_t lock; 619 + 620 + /* shadowed data register to clear/set bits safely */ 621 + u32 cpdata; 622 + }; 623 + 624 + static inline struct cpm1_gpio32_chip * 625 + to_cpm1_gpio32_chip(struct of_mm_gpio_chip *mm_gc) 626 + { 627 + return container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); 628 + } 629 + 630 + static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 631 + { 632 + struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); 633 + struct cpm_ioport32b __iomem *iop = mm_gc->regs; 634 + 635 + cpm1_gc->cpdata = in_be32(&iop->dat); 636 + } 637 + 638 + static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 639 + { 640 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 641 + struct cpm_ioport32b __iomem *iop = mm_gc->regs; 642 + u32 pin_mask; 643 + 644 + pin_mask = 1 << (31 - gpio); 645 + 646 + return !!(in_be32(&iop->dat) & pin_mask); 647 + } 648 + 649 + static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 650 + { 651 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 652 + struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc); 653 + struct cpm_ioport32b __iomem *iop = mm_gc->regs; 654 + unsigned long flags; 655 + u32 pin_mask = 1 << (31 - gpio); 656 + 657 + spin_lock_irqsave(&cpm1_gc->lock, flags); 658 + 659 + if (value) 660 + cpm1_gc->cpdata |= pin_mask; 661 + else 662 + cpm1_gc->cpdata &= ~pin_mask; 663 + 664 + out_be32(&iop->dat, cpm1_gc->cpdata); 665 + 666 + spin_unlock_irqrestore(&cpm1_gc->lock, flags); 667 + } 668 + 669 + static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 670 + { 671 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 672 + struct cpm_ioport32b __iomem *iop = mm_gc->regs; 673 + u32 pin_mask; 674 + 675 + pin_mask = 1 << (31 - gpio); 676 + 677 + setbits32(&iop->dir, pin_mask); 678 + 679 + cpm1_gpio32_set(gc, gpio, val); 680 + 681 + return 0; 682 + } 683 + 684 + static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 685 + { 686 + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 687 + struct cpm_ioport32b __iomem *iop = mm_gc->regs; 688 + u32 pin_mask; 689 + 690 + pin_mask = 1 << (31 - gpio); 691 + 692 + clrbits32(&iop->dir, pin_mask); 693 + 694 + return 0; 695 + } 696 + 697 + int cpm1_gpiochip_add32(struct device_node *np) 698 + { 699 + struct cpm1_gpio32_chip *cpm1_gc; 700 + struct of_mm_gpio_chip *mm_gc; 701 + struct of_gpio_chip *of_gc; 702 + struct gpio_chip *gc; 703 + 704 + cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 705 + if (!cpm1_gc) 706 + return -ENOMEM; 707 + 708 + spin_lock_init(&cpm1_gc->lock); 709 + 710 + mm_gc = &cpm1_gc->mm_gc; 711 + of_gc = &mm_gc->of_gc; 712 + gc = &of_gc->gc; 713 + 714 + mm_gc->save_regs = cpm1_gpio32_save_regs; 715 + of_gc->gpio_cells = 2; 716 + gc->ngpio = 32; 717 + gc->direction_input = cpm1_gpio32_dir_in; 718 + gc->direction_output = cpm1_gpio32_dir_out; 719 + gc->get = cpm1_gpio32_get; 720 + gc->set = cpm1_gpio32_set; 721 + 722 + return of_mm_gpiochip_add(np, mm_gc); 723 + } 724 + 725 + static int cpm_init_par_io(void) 726 + { 727 + struct device_node *np; 728 + 729 + for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a") 730 + cpm1_gpiochip_add16(np); 731 + 732 + for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b") 733 + cpm1_gpiochip_add32(np); 734 + 735 + for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c") 736 + cpm1_gpiochip_add16(np); 737 + 738 + for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d") 739 + cpm1_gpiochip_add16(np); 740 + 741 + /* Port E uses CPM2 layout */ 742 + for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e") 743 + cpm2_gpiochip_add32(np); 744 + return 0; 745 + } 746 + arch_initcall(cpm_init_par_io); 747 + 748 + #endif /* CONFIG_8xx_GPIO */