tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mISDN: Add XHFC support for embedded Speech-Design board to hfcmulti
New version without emulating arch specific stuff for the other
architectures, the special IO and init functions for the 8xx
microcontroller are in a separate include file.
Signed-off-by: Andreas Eversberg <andreas@eversberg.eu>
Signed-off-by: Karsten Keil <keil@b1-systems.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by
Karsten Keil
and committed by
David S. Miller
db9bb63a
5df3b8bc
+499
-143
+10
-1
drivers/isdn/hardware/mISDN/Kconfig
+10
-1
drivers/isdn/hardware/mISDN/Kconfig
···
13
13
14
14
config MISDN_HFCMULTI
15
15
tristate "Support for HFC multiport cards (HFC-4S/8S/E1)"
16
-
depends on PCI
16
+
depends on PCI || 8xx
17
17
depends on MISDN
18
18
help
19
19
Enable support for cards with Cologne Chip AG's HFC multiport
···
22
22
* HFC-4S (4 S/T interfaces on one chip)
23
23
* HFC-8S (8 S/T interfaces on one chip)
24
24
* HFC-E1 (E1 interface for 2Mbit ISDN)
25
+
26
+
config MISDN_HFCMULTI_8xx
27
+
boolean "Support for XHFC embedded board in HFC multiport driver"
28
+
depends on MISDN
29
+
depends on MISDN_HFCMULTI
30
+
depends on 8xx
31
+
default 8xx
32
+
help
33
+
Enable support for the XHFC embedded solution from Speech Design.
25
34
26
35
config MISDN_HFCUSB
27
36
tristate "Support for HFC-S USB based TAs"
+35
-10
drivers/isdn/hardware/mISDN/hfc_multi.h
+35
-10
drivers/isdn/hardware/mISDN/hfc_multi.h
···
17
17
#define PCI_ENA_REGIO 0x01
18
18
#define PCI_ENA_MEMIO 0x02
19
19
20
+
#define XHFC_IRQ 4 /* SIU_IRQ2 */
21
+
#define XHFC_MEMBASE 0xFE000000
22
+
#define XHFC_MEMSIZE 0x00001000
23
+
#define XHFC_OFFSET 0x00001000
24
+
#define PA_XHFC_A0 0x0020 /* PA10 */
25
+
#define PB_XHFC_IRQ1 0x00000100 /* PB23 */
26
+
#define PB_XHFC_IRQ2 0x00000200 /* PB22 */
27
+
#define PB_XHFC_IRQ3 0x00000400 /* PB21 */
28
+
#define PB_XHFC_IRQ4 0x00000800 /* PB20 */
29
+
20
30
/*
21
31
* NOTE: some registers are assigned multiple times due to different modes
22
32
* also registers are assigned differen for HFC-4s/8s and HFC-E1
···
91
81
#define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */
92
82
/* use double frame instead. */
93
83
84
+
#define HFC_TYPE_E1 1 /* controller is HFC-E1 */
85
+
#define HFC_TYPE_4S 4 /* controller is HFC-4S */
86
+
#define HFC_TYPE_8S 8 /* controller is HFC-8S */
87
+
#define HFC_TYPE_XHFC 5 /* controller is XHFC */
88
+
94
89
#define HFC_CHIP_EXRAM_128 0 /* external ram 128k */
95
90
#define HFC_CHIP_EXRAM_512 1 /* external ram 256k */
96
91
#define HFC_CHIP_REVISION0 2 /* old fifo handling */
···
103
88
#define HFC_CHIP_PCM_MASTER 4 /* PCM is master */
104
89
#define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */
105
90
#define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */
106
-
#define HFC_CHIP_ULAW 7 /* ULAW mode */
107
-
#define HFC_CHIP_CLOCK2 8 /* double clock mode */
108
-
#define HFC_CHIP_E1CLOCK_GET 9 /* always get clock from E1 interface */
109
-
#define HFC_CHIP_E1CLOCK_PUT 10 /* always put clock from E1 interface */
110
-
#define HFC_CHIP_WATCHDOG 11 /* whether we should send signals */
91
+
#define HFC_CHIP_CONF 7 /* conference handling is enabled */
92
+
#define HFC_CHIP_ULAW 8 /* ULAW mode */
93
+
#define HFC_CHIP_CLOCK2 9 /* double clock mode */
94
+
#define HFC_CHIP_E1CLOCK_GET 10 /* always get clock from E1 interface */
95
+
#define HFC_CHIP_E1CLOCK_PUT 11 /* always put clock from E1 interface */
96
+
#define HFC_CHIP_WATCHDOG 12 /* whether we should send signals */
111
97
/* to the watchdog */
112
-
#define HFC_CHIP_B410P 12 /* whether we have a b410p with echocan in */
98
+
#define HFC_CHIP_B410P 13 /* whether we have a b410p with echocan in */
113
99
/* hw */
114
-
#define HFC_CHIP_PLXSD 13 /* whether we have a Speech-Design PLX */
100
+
#define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */
101
+
#define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */
115
102
116
103
#define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
117
104
#define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
118
105
#define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */
106
+
#define HFC_IO_MODE_EMBSD 0x03 /* direct access */
119
107
120
108
/* table entry in the PCI devices list */
121
109
struct hm_map {
···
131
113
int opticalsupport;
132
114
int dip_type;
133
115
int io_mode;
116
+
int irq;
134
117
};
135
118
136
119
struct hfc_multi {
···
139
120
struct hm_map *mtyp;
140
121
int id;
141
122
int pcm; /* id of pcm bus */
142
-
int type;
123
+
int ctype; /* controller type */
143
124
int ports;
144
125
145
126
u_int irq; /* irq used by card */
···
179
160
int len);
180
161
void (*write_fifo)(struct hfc_multi *hc, u_char *data,
181
162
int len);
182
-
u_long pci_origmembase, plx_origmembase, dsp_origmembase;
163
+
u_long pci_origmembase, plx_origmembase;
183
164
void __iomem *pci_membase; /* PCI memory */
184
165
void __iomem *plx_membase; /* PLX memory */
185
-
u_char *dsp_membase; /* DSP on PLX */
166
+
u_long xhfc_origmembase;
167
+
u_char *xhfc_membase;
168
+
u_long *xhfc_memaddr, *xhfc_memdata;
169
+
#ifdef CONFIG_MISDN_HFCMULTI_8xx
170
+
struct immap *immap;
171
+
#endif
172
+
u_long pb_irqmsk; /* Portbit mask to check the IRQ line */
186
173
u_long pci_iobase; /* PCI IO */
187
174
struct hfcm_hw hw; /* remember data of write-only-registers */
188
175
+167
drivers/isdn/hardware/mISDN/hfc_multi_8xx.h
+167
drivers/isdn/hardware/mISDN/hfc_multi_8xx.h
···
1
+
/*
2
+
* For License see notice in hfc_multi.c
3
+
*
4
+
* special IO and init functions for the embedded XHFC board
5
+
* from Speech Design
6
+
*
7
+
*/
8
+
9
+
#include <asm/8xx_immap.h>
10
+
11
+
/* Change this to the value used by your board */
12
+
#ifndef IMAP_ADDR
13
+
#define IMAP_ADDR 0xFFF00000
14
+
#endif
15
+
16
+
static void
17
+
#ifdef HFC_REGISTER_DEBUG
18
+
HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val,
19
+
const char *function, int line)
20
+
#else
21
+
HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val)
22
+
#endif
23
+
{
24
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
25
+
writeb(reg, hc->xhfc_memaddr);
26
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
27
+
writeb(val, hc->xhfc_memdata);
28
+
}
29
+
static u_char
30
+
#ifdef HFC_REGISTER_DEBUG
31
+
HFC_inb_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line)
32
+
#else
33
+
HFC_inb_embsd(struct hfc_multi *hc, u_char reg)
34
+
#endif
35
+
{
36
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
37
+
writeb(reg, hc->xhfc_memaddr);
38
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
39
+
return readb(hc->xhfc_memdata);
40
+
}
41
+
static u_short
42
+
#ifdef HFC_REGISTER_DEBUG
43
+
HFC_inw_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line)
44
+
#else
45
+
HFC_inw_embsd(struct hfc_multi *hc, u_char reg)
46
+
#endif
47
+
{
48
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
49
+
writeb(reg, hc->xhfc_memaddr);
50
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
51
+
return readb(hc->xhfc_memdata);
52
+
}
53
+
static void
54
+
#ifdef HFC_REGISTER_DEBUG
55
+
HFC_wait_embsd(struct hfc_multi *hc, const char *function, int line)
56
+
#else
57
+
HFC_wait_embsd(struct hfc_multi *hc)
58
+
#endif
59
+
{
60
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
61
+
writeb(R_STATUS, hc->xhfc_memaddr);
62
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
63
+
while (readb(hc->xhfc_memdata) & V_BUSY)
64
+
cpu_relax();
65
+
}
66
+
67
+
/* write fifo data (EMBSD) */
68
+
void
69
+
write_fifo_embsd(struct hfc_multi *hc, u_char *data, int len)
70
+
{
71
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
72
+
*hc->xhfc_memaddr = A_FIFO_DATA0;
73
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
74
+
while (len) {
75
+
*hc->xhfc_memdata = *data;
76
+
data++;
77
+
len--;
78
+
}
79
+
}
80
+
81
+
/* read fifo data (EMBSD) */
82
+
void
83
+
read_fifo_embsd(struct hfc_multi *hc, u_char *data, int len)
84
+
{
85
+
hc->immap->im_ioport.iop_padat |= PA_XHFC_A0;
86
+
*hc->xhfc_memaddr = A_FIFO_DATA0;
87
+
hc->immap->im_ioport.iop_padat &= ~(PA_XHFC_A0);
88
+
while (len) {
89
+
*data = (u_char)(*hc->xhfc_memdata);
90
+
data++;
91
+
len--;
92
+
}
93
+
}
94
+
95
+
static int
96
+
setup_embedded(struct hfc_multi *hc, struct hm_map *m)
97
+
{
98
+
printk(KERN_INFO
99
+
"HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
100
+
m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
101
+
102
+
hc->pci_dev = NULL;
103
+
if (m->clock2)
104
+
test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
105
+
106
+
hc->leds = m->leds;
107
+
hc->ledstate = 0xAFFEAFFE;
108
+
hc->opticalsupport = m->opticalsupport;
109
+
110
+
hc->pci_iobase = 0;
111
+
hc->pci_membase = 0;
112
+
hc->xhfc_membase = NULL;
113
+
hc->xhfc_memaddr = NULL;
114
+
hc->xhfc_memdata = NULL;
115
+
116
+
/* set memory access methods */
117
+
if (m->io_mode) /* use mode from card config */
118
+
hc->io_mode = m->io_mode;
119
+
switch (hc->io_mode) {
120
+
case HFC_IO_MODE_EMBSD:
121
+
test_and_set_bit(HFC_CHIP_EMBSD, &hc->chip);
122
+
hc->slots = 128; /* required */
123
+
/* fall through */
124
+
hc->HFC_outb = HFC_outb_embsd;
125
+
hc->HFC_inb = HFC_inb_embsd;
126
+
hc->HFC_inw = HFC_inw_embsd;
127
+
hc->HFC_wait = HFC_wait_embsd;
128
+
hc->read_fifo = read_fifo_embsd;
129
+
hc->write_fifo = write_fifo_embsd;
130
+
hc->xhfc_origmembase = XHFC_MEMBASE + XHFC_OFFSET * hc->id;
131
+
hc->xhfc_membase = (u_char *)ioremap(hc->xhfc_origmembase,
132
+
XHFC_MEMSIZE);
133
+
if (!hc->xhfc_membase) {
134
+
printk(KERN_WARNING
135
+
"HFC-multi: failed to remap xhfc address space. "
136
+
"(internal error)\n");
137
+
return -EIO;
138
+
}
139
+
hc->xhfc_memaddr = (u_long *)(hc->xhfc_membase + 4);
140
+
hc->xhfc_memdata = (u_long *)(hc->xhfc_membase);
141
+
printk(KERN_INFO
142
+
"HFC-multi: xhfc_membase:%#lx xhfc_origmembase:%#lx "
143
+
"xhfc_memaddr:%#lx xhfc_memdata:%#lx\n",
144
+
(u_long)hc->xhfc_membase, hc->xhfc_origmembase,
145
+
(u_long)hc->xhfc_memaddr, (u_long)hc->xhfc_memdata);
146
+
break;
147
+
default:
148
+
printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
149
+
return -EIO;
150
+
}
151
+
152
+
/* Prepare the MPC8XX PortA 10 as output (address/data selector) */
153
+
hc->immap = (struct immap *)(IMAP_ADDR);
154
+
hc->immap->im_ioport.iop_papar &= ~(PA_XHFC_A0);
155
+
hc->immap->im_ioport.iop_paodr &= ~(PA_XHFC_A0);
156
+
hc->immap->im_ioport.iop_padir |= PA_XHFC_A0;
157
+
158
+
/* Prepare the MPC8xx PortB __X__ as input (ISDN__X__IRQ) */
159
+
hc->pb_irqmsk = (PB_XHFC_IRQ1 << hc->id);
160
+
hc->immap->im_cpm.cp_pbpar &= ~(hc->pb_irqmsk);
161
+
hc->immap->im_cpm.cp_pbodr &= ~(hc->pb_irqmsk);
162
+
hc->immap->im_cpm.cp_pbdir &= ~(hc->pb_irqmsk);
163
+
164
+
/* At this point the needed config is done */
165
+
/* fifos are still not enabled */
166
+
return 0;
167
+
}
+282
-132
drivers/isdn/hardware/mISDN/hfcmulti.c
+282
-132
drivers/isdn/hardware/mISDN/hfcmulti.c
···
139
139
* Selects interface with clock source for mISDN and applications.
140
140
* Set to card number starting with 1. Set to -1 to disable.
141
141
* By default, the first card is used as clock source.
142
+
*
143
+
* hwid:
144
+
* NOTE: only one hwid value must be given once
145
+
* Enable special embedded devices with XHFC controllers.
142
146
*/
143
147
144
148
/*
···
210
206
static uint timer;
211
207
static uint clockdelay_te = CLKDEL_TE;
212
208
static uint clockdelay_nt = CLKDEL_NT;
209
+
#define HWID_NONE 0
210
+
#define HWID_MINIP4 1
211
+
#define HWID_MINIP8 2
212
+
#define HWID_MINIP16 3
213
+
static uint hwid = HWID_NONE;
213
214
214
215
static int HFC_cnt, Port_cnt, PCM_cnt = 99;
215
216
···
232
223
module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
233
224
module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
234
225
module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
226
+
module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
235
227
236
228
#ifdef HFC_REGISTER_DEBUG
237
229
#define HFC_outb(hc, reg, val) \
···
260
250
#define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
261
251
#define HFC_wait(hc) (hc->HFC_wait(hc))
262
252
#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
253
+
#endif
254
+
255
+
#ifdef CONFIG_MISDN_HFCMULTI_8xx
256
+
#include "hfc_multi_8xx.h"
263
257
#endif
264
258
265
259
/* HFC_IO_MODE_PCIMEM */
···
942
928
writel(pv, plx_acc_32);
943
929
if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
944
930
pcmmaster = hc;
945
-
if (hc->type == 1) {
931
+
if (hc->ctype == HFC_TYPE_E1) {
946
932
if (debug & DEBUG_HFCMULTI_PLXSD)
947
933
printk(KERN_DEBUG
948
934
"Schedule SYNC_I\n");
···
963
949
pv |= PLX_SYNC_O_EN;
964
950
writel(pv, plx_acc_32);
965
951
/* switch to jatt PLL, if not disabled by RX_SYNC */
966
-
if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
952
+
if (hc->ctype == HFC_TYPE_E1
953
+
&& !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
967
954
if (debug & DEBUG_HFCMULTI_PLXSD)
968
955
printk(KERN_DEBUG "Schedule jatt PLL\n");
969
956
hc->e1_resync |= 2; /* switch to jatt */
···
976
961
printk(KERN_DEBUG
977
962
"id=%d (0x%p) = PCM master syncronized "
978
963
"with QUARTZ\n", hc->id, hc);
979
-
if (hc->type == 1) {
964
+
if (hc->ctype == HFC_TYPE_E1) {
980
965
/* Use the crystal clock for the PCM
981
966
master card */
982
967
if (debug & DEBUG_HFCMULTI_PLXSD)
···
987
972
if (debug & DEBUG_HFCMULTI_PLXSD)
988
973
printk(KERN_DEBUG
989
974
"QUARTZ is automatically "
990
-
"enabled by HFC-%dS\n", hc->type);
975
+
"enabled by HFC-%dS\n", hc->ctype);
991
976
}
992
977
plx_acc_32 = hc->plx_membase + PLX_GPIOC;
993
978
pv = readl(plx_acc_32);
···
1075
1060
1076
1061
/* disable memory mapped ports / io ports */
1077
1062
test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1078
-
pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1063
+
if (hc->pci_dev)
1064
+
pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1079
1065
if (hc->pci_membase)
1080
1066
iounmap(hc->pci_membase);
1081
1067
if (hc->plx_membase)
1082
1068
iounmap(hc->plx_membase);
1083
1069
if (hc->pci_iobase)
1084
1070
release_region(hc->pci_iobase, 8);
1071
+
if (hc->xhfc_membase)
1072
+
iounmap((void *)hc->xhfc_membase);
1085
1073
1086
1074
if (hc->pci_dev) {
1087
1075
pci_disable_device(hc->pci_dev);
···
1118
1100
/* revision check */
1119
1101
if (debug & DEBUG_HFCMULTI_INIT)
1120
1102
printk(KERN_DEBUG "%s: entered\n", __func__);
1121
-
val = HFC_inb(hc, R_CHIP_ID)>>4;
1122
-
if (val != 0x8 && val != 0xc && val != 0xe) {
1103
+
val = HFC_inb(hc, R_CHIP_ID);
1104
+
if ((val>>4) != 0x8 && (val>>4) != 0xc && (val>>4) != 0xe
1105
+
&& (val>>1) != 0x31) {
1123
1106
printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1124
1107
err = -EIO;
1125
1108
goto out;
···
1128
1109
rev = HFC_inb(hc, R_CHIP_RV);
1129
1110
printk(KERN_INFO
1130
1111
"HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1131
-
val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1132
-
if (rev == 0) {
1112
+
val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1113
+
" (old FIFO handling)" : "");
1114
+
if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1133
1115
test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1134
1116
printk(KERN_WARNING
1135
1117
"HFC_multi: NOTE: Your chip is revision 0, "
···
1171
1151
hc->Zmin = 0xc0;
1172
1152
hc->Zlen = 8000;
1173
1153
hc->DTMFbase = 0x2000;
1154
+
}
1155
+
if (hc->ctype == HFC_TYPE_XHFC) {
1156
+
hc->Flen = 0x8;
1157
+
hc->Zmin = 0x0;
1158
+
hc->Zlen = 64;
1159
+
hc->DTMFbase = 0x0;
1174
1160
}
1175
1161
hc->max_trans = poll << 1;
1176
1162
if (hc->max_trans > hc->Zlen)
···
1237
1211
hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1238
1212
}
1239
1213
1214
+
if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1215
+
hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1216
+
1240
1217
/* we only want the real Z2 read-pointer for revision > 0 */
1241
1218
if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1242
1219
hc->hw.r_ram_sz |= V_FZ_MD;
···
1263
1234
1264
1235
/* soft reset */
1265
1236
HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1266
-
HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1237
+
if (hc->ctype == HFC_TYPE_XHFC)
1238
+
HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1239
+
0x11 /* 16 Bytes TX/RX */);
1240
+
else
1241
+
HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1267
1242
HFC_outb(hc, R_FIFO_MD, 0);
1268
-
hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1243
+
if (hc->ctype == HFC_TYPE_XHFC)
1244
+
hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1245
+
else
1246
+
hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1247
+
| V_RLD_EPR;
1269
1248
HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1270
1249
udelay(100);
1271
1250
hc->hw.r_cirm = 0;
1272
1251
HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1273
1252
udelay(100);
1274
-
HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1253
+
if (hc->ctype != HFC_TYPE_XHFC)
1254
+
HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1275
1255
1276
1256
/* Speech Design PLX bridge pcm and sync mode */
1277
1257
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
···
1316
1278
HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1317
1279
if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1318
1280
HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1281
+
else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1282
+
HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1319
1283
else
1320
1284
HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1321
1285
HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1322
1286
for (i = 0; i < 256; i++) {
1323
1287
HFC_outb_nodebug(hc, R_SLOT, i);
1324
1288
HFC_outb_nodebug(hc, A_SL_CFG, 0);
1325
-
HFC_outb_nodebug(hc, A_CONF, 0);
1289
+
if (hc->ctype != HFC_TYPE_XHFC)
1290
+
HFC_outb_nodebug(hc, A_CONF, 0);
1326
1291
hc->slot_owner[i] = -1;
1327
1292
}
1328
1293
···
1336
1295
"%s: setting double clock\n", __func__);
1337
1296
HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1338
1297
}
1298
+
1299
+
if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1300
+
HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1339
1301
1340
1302
/* B410P GPIO */
1341
1303
if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
···
1468
1424
hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1469
1425
1470
1426
/* set E1 state machine IRQ */
1471
-
if (hc->type == 1)
1427
+
if (hc->ctype == HFC_TYPE_E1)
1472
1428
hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1473
1429
1474
1430
/* set DTMF detection */
···
1488
1444
r_conf_en = V_CONF_EN | V_ULAW;
1489
1445
else
1490
1446
r_conf_en = V_CONF_EN;
1491
-
HFC_outb(hc, R_CONF_EN, r_conf_en);
1447
+
if (hc->ctype != HFC_TYPE_XHFC)
1448
+
HFC_outb(hc, R_CONF_EN, r_conf_en);
1492
1449
1493
1450
/* setting leds */
1494
1451
switch (hc->leds) {
···
1513
1468
break;
1514
1469
}
1515
1470
1471
+
if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1472
+
hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1473
+
HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1474
+
}
1475
+
1516
1476
/* set master clock */
1517
1477
if (hc->masterclk >= 0) {
1518
1478
if (debug & DEBUG_HFCMULTI_INIT)
1519
1479
printk(KERN_DEBUG "%s: setting ST master clock "
1520
1480
"to port %d (0..%d)\n",
1521
1481
__func__, hc->masterclk, hc->ports-1);
1522
-
hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1482
+
hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1523
1483
HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1524
1484
}
1485
+
1486
+
1525
1487
1526
1488
/* setting misc irq */
1527
1489
HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
···
1981
1929
Fspace = 1;
1982
1930
}
1983
1931
/* one frame only for ST D-channels, to allow resending */
1984
-
if (hc->type != 1 && dch) {
1932
+
if (hc->ctype != HFC_TYPE_E1 && dch) {
1985
1933
if (f1 != f2)
1986
1934
Fspace = 0;
1987
1935
}
···
2023
1971
"slot_tx %d\n",
2024
1972
__func__, ch, slot_tx);
2025
1973
/* connect slot */
2026
-
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2027
-
V_HDLC_TRP | V_IFF);
1974
+
if (hc->ctype == HFC_TYPE_XHFC)
1975
+
HFC_outb(hc, A_CON_HDLC, 0xc0
1976
+
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
1977
+
/* Enable FIFO, no interrupt */
1978
+
else
1979
+
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1980
+
V_HDLC_TRP | V_IFF);
2028
1981
HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2029
1982
HFC_wait_nodebug(hc);
2030
-
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2031
-
V_HDLC_TRP | V_IFF);
1983
+
if (hc->ctype == HFC_TYPE_XHFC)
1984
+
HFC_outb(hc, A_CON_HDLC, 0xc0
1985
+
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
1986
+
/* Enable FIFO, no interrupt */
1987
+
else
1988
+
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1989
+
V_HDLC_TRP | V_IFF);
2032
1990
HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2033
1991
HFC_wait_nodebug(hc);
2034
1992
}
···
2066
2004
"FIFO data: channel %d slot_tx %d\n",
2067
2005
__func__, ch, slot_tx);
2068
2006
/* disconnect slot */
2069
-
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2007
+
if (hc->ctype == HFC_TYPE_XHFC)
2008
+
HFC_outb(hc, A_CON_HDLC, 0x80
2009
+
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2010
+
/* Enable FIFO, no interrupt */
2011
+
else
2012
+
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2013
+
V_HDLC_TRP | V_IFF);
2070
2014
HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2071
2015
HFC_wait_nodebug(hc);
2072
-
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2016
+
if (hc->ctype == HFC_TYPE_XHFC)
2017
+
HFC_outb(hc, A_CON_HDLC, 0x80
2018
+
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
2019
+
/* Enable FIFO, no interrupt */
2020
+
else
2021
+
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2022
+
V_HDLC_TRP | V_IFF);
2073
2023
HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2074
2024
HFC_wait_nodebug(hc);
2075
2025
}
···
2401
2327
spin_unlock_irqrestore(&HFClock, flags);
2402
2328
}
2403
2329
2404
-
if (hc->type != 1 || hc->e1_state == 1)
2330
+
if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2405
2331
for (ch = 0; ch <= 31; ch++) {
2406
2332
if (hc->created[hc->chan[ch].port]) {
2407
2333
hfcmulti_tx(hc, ch);
···
2424
2350
}
2425
2351
}
2426
2352
}
2427
-
if (hc->type == 1 && hc->created[0]) {
2353
+
if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2428
2354
dch = hc->chan[hc->dslot].dch;
2429
2355
if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2430
2356
/* LOS */
···
2684
2610
"card %d, this is no bug.\n", hc->id + 1, irqsem);
2685
2611
irqsem = hc->id + 1;
2686
2612
#endif
2687
-
2613
+
#ifdef CONFIG_MISDN_HFCMULTI_8xx
2614
+
if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2615
+
goto irq_notforus;
2616
+
#endif
2688
2617
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2689
2618
spin_lock_irqsave(&plx_lock, flags);
2690
2619
plx_acc = hc->plx_membase + PLX_INTCSR;
···
2727
2650
}
2728
2651
hc->irqcnt++;
2729
2652
if (r_irq_statech) {
2730
-
if (hc->type != 1)
2653
+
if (hc->ctype != HFC_TYPE_E1)
2731
2654
ph_state_irq(hc, r_irq_statech);
2732
2655
}
2733
2656
if (status & V_EXT_IRQSTA)
···
2741
2664
r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2742
2665
r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2743
2666
if (r_irq_misc & V_STA_IRQ) {
2744
-
if (hc->type == 1) {
2667
+
if (hc->ctype == HFC_TYPE_E1) {
2745
2668
/* state machine */
2746
2669
dch = hc->chan[hc->dslot].dch;
2747
2670
e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
···
2863
2786
if (hc->slot_owner[oslot_tx<<1] == ch) {
2864
2787
HFC_outb(hc, R_SLOT, oslot_tx << 1);
2865
2788
HFC_outb(hc, A_SL_CFG, 0);
2866
-
HFC_outb(hc, A_CONF, 0);
2789
+
if (hc->ctype != HFC_TYPE_XHFC)
2790
+
HFC_outb(hc, A_CONF, 0);
2867
2791
hc->slot_owner[oslot_tx<<1] = -1;
2868
2792
} else {
2869
2793
if (debug & DEBUG_HFCMULTI_MODE)
···
2917
2839
flow_tx, routing, conf);
2918
2840
HFC_outb(hc, R_SLOT, slot_tx << 1);
2919
2841
HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2920
-
HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2842
+
if (hc->ctype != HFC_TYPE_XHFC)
2843
+
HFC_outb(hc, A_CONF,
2844
+
(conf < 0) ? 0 : (conf | V_CONF_SL));
2921
2845
hc->slot_owner[slot_tx << 1] = ch;
2922
2846
hc->chan[ch].slot_tx = slot_tx;
2923
2847
hc->chan[ch].bank_tx = bank_tx;
···
2969
2889
HFC_outb(hc, A_IRQ_MSK, 0);
2970
2890
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2971
2891
HFC_wait(hc);
2972
-
if (hc->chan[ch].bch && hc->type != 1) {
2892
+
if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2973
2893
hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2974
2894
((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2975
2895
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
···
3045
2965
/* enable TX fifo */
3046
2966
HFC_outb(hc, R_FIFO, ch << 1);
3047
2967
HFC_wait(hc);
3048
-
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3049
-
V_HDLC_TRP | V_IFF);
2968
+
if (hc->ctype == HFC_TYPE_XHFC)
2969
+
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
2970
+
V_HDLC_TRP | V_IFF);
2971
+
/* Enable FIFO, no interrupt */
2972
+
else
2973
+
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2974
+
V_HDLC_TRP | V_IFF);
3050
2975
HFC_outb(hc, A_SUBCH_CFG, 0);
3051
2976
HFC_outb(hc, A_IRQ_MSK, 0);
3052
2977
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
···
3061
2976
/* enable RX fifo */
3062
2977
HFC_outb(hc, R_FIFO, (ch<<1)|1);
3063
2978
HFC_wait(hc);
3064
-
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2979
+
if (hc->ctype == HFC_TYPE_XHFC)
2980
+
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
2981
+
V_HDLC_TRP);
2982
+
/* Enable FIFO, no interrupt*/
2983
+
else
2984
+
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
2985
+
V_HDLC_TRP);
3065
2986
HFC_outb(hc, A_SUBCH_CFG, 0);
3066
2987
HFC_outb(hc, A_IRQ_MSK, 0);
3067
2988
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3068
2989
HFC_wait(hc);
3069
2990
}
3070
-
if (hc->type != 1) {
2991
+
if (hc->ctype != HFC_TYPE_E1) {
3071
2992
hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3072
2993
((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3073
2994
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
···
3094
3003
/* enable TX fifo */
3095
3004
HFC_outb(hc, R_FIFO, ch<<1);
3096
3005
HFC_wait(hc);
3097
-
if (hc->type == 1 || hc->chan[ch].bch) {
3006
+
if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3098
3007
/* E1 or B-channel */
3099
3008
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3100
3009
HFC_outb(hc, A_SUBCH_CFG, 0);
···
3110
3019
HFC_outb(hc, R_FIFO, (ch<<1)|1);
3111
3020
HFC_wait(hc);
3112
3021
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3113
-
if (hc->type == 1 || hc->chan[ch].bch)
3022
+
if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3114
3023
HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3115
3024
else
3116
3025
HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
···
3119
3028
HFC_wait(hc);
3120
3029
if (hc->chan[ch].bch) {
3121
3030
test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3122
-
if (hc->type != 1) {
3031
+
if (hc->ctype != HFC_TYPE_E1) {
3123
3032
hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3124
3033
((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3125
3034
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
···
3199
3108
case HW_RESET_REQ:
3200
3109
/* start activation */
3201
3110
spin_lock_irqsave(&hc->lock, flags);
3202
-
if (hc->type == 1) {
3111
+
if (hc->ctype == HFC_TYPE_E1) {
3203
3112
if (debug & DEBUG_HFCMULTI_MSG)
3204
3113
printk(KERN_DEBUG
3205
3114
"%s: HW_RESET_REQ no BRI\n",
···
3220
3129
case HW_DEACT_REQ:
3221
3130
/* start deactivation */
3222
3131
spin_lock_irqsave(&hc->lock, flags);
3223
-
if (hc->type == 1) {
3132
+
if (hc->ctype == HFC_TYPE_E1) {
3224
3133
if (debug & DEBUG_HFCMULTI_MSG)
3225
3134
printk(KERN_DEBUG
3226
3135
"%s: HW_DEACT_REQ no BRI\n",
···
3254
3163
break;
3255
3164
case HW_POWERUP_REQ:
3256
3165
spin_lock_irqsave(&hc->lock, flags);
3257
-
if (hc->type == 1) {
3166
+
if (hc->ctype == HFC_TYPE_E1) {
3258
3167
if (debug & DEBUG_HFCMULTI_MSG)
3259
3168
printk(KERN_DEBUG
3260
3169
"%s: HW_POWERUP_REQ no BRI\n",
···
3331
3240
__func__, hc->chan[dch->slot].port,
3332
3241
hc->ports-1);
3333
3242
/* start activation */
3334
-
if (hc->type == 1) {
3243
+
if (hc->ctype == HFC_TYPE_E1) {
3335
3244
ph_state_change(dch);
3336
3245
if (debug & DEBUG_HFCMULTI_STATE)
3337
3246
printk(KERN_DEBUG
···
3364
3273
__func__, hc->chan[dch->slot].port,
3365
3274
hc->ports-1);
3366
3275
/* start deactivation */
3367
-
if (hc->type == 1) {
3276
+
if (hc->ctype == HFC_TYPE_E1) {
3368
3277
if (debug & DEBUG_HFCMULTI_MSG)
3369
3278
printk(KERN_DEBUG
3370
3279
"%s: PH_DEACTIVATE no BRI\n",
···
3584
3493
features->hfc_id = hc->id;
3585
3494
if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3586
3495
features->hfc_dtmf = 1;
3496
+
if (test_bit(HFC_CHIP_CONF, &hc->chip))
3497
+
features->hfc_conf = 1;
3587
3498
features->hfc_loops = 0;
3588
3499
if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3589
3500
features->hfc_echocanhw = 1;
···
3723
3630
hc = dch->hw;
3724
3631
ch = dch->slot;
3725
3632
3726
-
if (hc->type == 1) {
3633
+
if (hc->ctype == HFC_TYPE_E1) {
3727
3634
if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3728
3635
if (debug & DEBUG_HFCMULTI_STATE)
3729
3636
printk(KERN_DEBUG
···
3848
3755
if (debug & DEBUG_HFCMULTI_INIT)
3849
3756
printk(KERN_DEBUG "%s: entered\n", __func__);
3850
3757
3851
-
if (hc->type == 1) {
3758
+
if (hc->ctype == HFC_TYPE_E1) {
3852
3759
hc->chan[hc->dslot].slot_tx = -1;
3853
3760
hc->chan[hc->dslot].slot_rx = -1;
3854
3761
hc->chan[hc->dslot].conf = -1;
···
3997
3904
}
3998
3905
if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3999
3906
hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3907
+
if (hc->ctype == HFC_TYPE_XHFC) {
3908
+
hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
3909
+
HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
3910
+
0x7c << 1 /* V_ST_PULSE */);
3911
+
}
4000
3912
/* line setup */
4001
3913
HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
4002
3914
/* disable E-channel */
···
4088
3990
return -EINVAL;
4089
3991
if (rq->protocol == ISDN_P_NONE)
4090
3992
return -EINVAL;
4091
-
if (hc->type == 1)
3993
+
if (hc->ctype == HFC_TYPE_E1)
4092
3994
ch = rq->adr.channel;
4093
3995
else
4094
3996
ch = (rq->adr.channel - 1) + (dch->slot - 2);
···
4179
4081
switch (rq->protocol) {
4180
4082
case ISDN_P_TE_S0:
4181
4083
case ISDN_P_NT_S0:
4182
-
if (hc->type == 1) {
4084
+
if (hc->ctype == HFC_TYPE_E1) {
4183
4085
err = -EINVAL;
4184
4086
break;
4185
4087
}
···
4187
4089
break;
4188
4090
case ISDN_P_TE_E1:
4189
4091
case ISDN_P_NT_E1:
4190
-
if (hc->type != 1) {
4092
+
if (hc->ctype != HFC_TYPE_E1) {
4191
4093
err = -EINVAL;
4192
4094
break;
4193
4095
}
···
4254
4156
disable_hwirq(hc);
4255
4157
spin_unlock_irqrestore(&hc->lock, flags);
4256
4158
4257
-
if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4159
+
if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4258
4160
"HFC-multi", hc)) {
4259
4161
printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4260
-
hc->pci_dev->irq);
4162
+
hc->irq);
4163
+
hc->irq = 0;
4261
4164
return -EIO;
4262
4165
}
4263
-
hc->irq = hc->pci_dev->irq;
4264
4166
4265
4167
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4266
4168
spin_lock_irqsave(&plx_lock, plx_flags);
···
4367
4269
hc->ledstate = 0xAFFEAFFE;
4368
4270
hc->opticalsupport = m->opticalsupport;
4369
4271
4272
+
hc->pci_iobase = 0;
4273
+
hc->pci_membase = NULL;
4274
+
hc->plx_membase = NULL;
4275
+
4370
4276
/* set memory access methods */
4371
4277
if (m->io_mode) /* use mode from card config */
4372
4278
hc->io_mode = m->io_mode;
···
4378
4276
case HFC_IO_MODE_PLXSD:
4379
4277
test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4380
4278
hc->slots = 128; /* required */
4381
-
/* fall through */
4382
-
case HFC_IO_MODE_PCIMEM:
4383
4279
hc->HFC_outb = HFC_outb_pcimem;
4384
4280
hc->HFC_inb = HFC_inb_pcimem;
4385
4281
hc->HFC_inw = HFC_inw_pcimem;
4386
4282
hc->HFC_wait = HFC_wait_pcimem;
4387
4283
hc->read_fifo = read_fifo_pcimem;
4388
4284
hc->write_fifo = write_fifo_pcimem;
4389
-
break;
4390
-
case HFC_IO_MODE_REGIO:
4391
-
hc->HFC_outb = HFC_outb_regio;
4392
-
hc->HFC_inb = HFC_inb_regio;
4393
-
hc->HFC_inw = HFC_inw_regio;
4394
-
hc->HFC_wait = HFC_wait_regio;
4395
-
hc->read_fifo = read_fifo_regio;
4396
-
hc->write_fifo = write_fifo_regio;
4397
-
break;
4398
-
default:
4399
-
printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4400
-
pci_disable_device(hc->pci_dev);
4401
-
return -EIO;
4402
-
}
4403
-
hc->HFC_outb_nodebug = hc->HFC_outb;
4404
-
hc->HFC_inb_nodebug = hc->HFC_inb;
4405
-
hc->HFC_inw_nodebug = hc->HFC_inw;
4406
-
hc->HFC_wait_nodebug = hc->HFC_wait;
4407
-
#ifdef HFC_REGISTER_DEBUG
4408
-
hc->HFC_outb = HFC_outb_debug;
4409
-
hc->HFC_inb = HFC_inb_debug;
4410
-
hc->HFC_inw = HFC_inw_debug;
4411
-
hc->HFC_wait = HFC_wait_debug;
4412
-
#endif
4413
-
hc->pci_iobase = 0;
4414
-
hc->pci_membase = NULL;
4415
-
hc->plx_membase = NULL;
4416
-
4417
-
switch (hc->io_mode) {
4418
-
case HFC_IO_MODE_PLXSD:
4419
4285
hc->plx_origmembase = hc->pci_dev->resource[0].start;
4420
4286
/* MEMBASE 1 is PLX PCI Bridge */
4421
4287
···
4431
4361
pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4432
4362
break;
4433
4363
case HFC_IO_MODE_PCIMEM:
4364
+
hc->HFC_outb = HFC_outb_pcimem;
4365
+
hc->HFC_inb = HFC_inb_pcimem;
4366
+
hc->HFC_inw = HFC_inw_pcimem;
4367
+
hc->HFC_wait = HFC_wait_pcimem;
4368
+
hc->read_fifo = read_fifo_pcimem;
4369
+
hc->write_fifo = write_fifo_pcimem;
4434
4370
hc->pci_origmembase = hc->pci_dev->resource[1].start;
4435
4371
if (!hc->pci_origmembase) {
4436
4372
printk(KERN_WARNING
···
4453
4377
pci_disable_device(hc->pci_dev);
4454
4378
return -EIO;
4455
4379
}
4456
-
printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4457
-
"HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4380
+
printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4381
+
"%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4458
4382
hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4459
4383
pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4460
4384
break;
4461
4385
case HFC_IO_MODE_REGIO:
4386
+
hc->HFC_outb = HFC_outb_regio;
4387
+
hc->HFC_inb = HFC_inb_regio;
4388
+
hc->HFC_inw = HFC_inw_regio;
4389
+
hc->HFC_wait = HFC_wait_regio;
4390
+
hc->read_fifo = read_fifo_regio;
4391
+
hc->write_fifo = write_fifo_regio;
4462
4392
hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4463
4393
if (!hc->pci_iobase) {
4464
4394
printk(KERN_WARNING
···
4546
4464
dch->timer.function = NULL;
4547
4465
}
4548
4466
4549
-
if (hc->type == 1) { /* E1 */
4467
+
if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4550
4468
/* remove sync */
4551
4469
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4552
4470
hc->syncronized = 0;
···
4945
4863
test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4946
4864
&hc->chan[i + 2].cfg);
4947
4865
}
4948
-
snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4949
-
hc->type, HFC_cnt + 1, pt + 1);
4950
-
ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4866
+
if (hc->ctype == HFC_TYPE_XHFC) {
4867
+
snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4868
+
HFC_cnt + 1, pt + 1);
4869
+
ret = mISDN_register_device(&dch->dev, NULL, name);
4870
+
} else {
4871
+
snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4872
+
hc->ctype, HFC_cnt + 1, pt + 1);
4873
+
ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4874
+
}
4951
4875
if (ret)
4952
4876
goto free_chan;
4953
4877
hc->created[pt] = 1;
···
4964
4876
}
4965
4877
4966
4878
static int
4967
-
hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4879
+
hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4880
+
const struct pci_device_id *ent)
4968
4881
{
4969
-
struct hm_map *m = (struct hm_map *)ent->driver_data;
4970
4882
int ret_err = 0;
4971
4883
int pt;
4972
4884
struct hfc_multi *hc;
···
5001
4913
}
5002
4914
spin_lock_init(&hc->lock);
5003
4915
hc->mtyp = m;
5004
-
hc->type = m->type;
4916
+
hc->ctype = m->type;
5005
4917
hc->ports = m->ports;
5006
4918
hc->id = HFC_cnt;
5007
4919
hc->pcm = pcm[HFC_cnt];
5008
4920
hc->io_mode = iomode[HFC_cnt];
5009
-
if (dslot[HFC_cnt] < 0 && hc->type == 1) {
4921
+
if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
5010
4922
hc->dslot = 0;
5011
4923
printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
5012
4924
"31 B-channels\n");
5013
-
} if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
4925
+
}
4926
+
if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
4927
+
&& hc->ctype == HFC_TYPE_E1) {
5014
4928
hc->dslot = dslot[HFC_cnt];
5015
4929
printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
5016
4930
"time slot %d\n", dslot[HFC_cnt]);
···
5034
4944
for (i = 0; i < (poll >> 1); i++)
5035
4945
hc->silence_data[i] = hc->silence;
5036
4946
5037
-
if (!(type[HFC_cnt] & 0x200))
5038
-
test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4947
+
if (hc->ctype != HFC_TYPE_XHFC) {
4948
+
if (!(type[HFC_cnt] & 0x200))
4949
+
test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4950
+
test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
4951
+
}
5039
4952
5040
4953
if (type[HFC_cnt] & 0x800)
5041
4954
test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
···
5062
4969
printk(KERN_NOTICE "Watchdog enabled\n");
5063
4970
}
5064
4971
5065
-
/* setup pci, hc->slots may change due to PLXSD */
5066
-
ret_err = setup_pci(hc, pdev, ent);
4972
+
if (pdev && ent)
4973
+
/* setup pci, hc->slots may change due to PLXSD */
4974
+
ret_err = setup_pci(hc, pdev, ent);
4975
+
else
4976
+
#ifdef CONFIG_MISDN_HFCMULTI_8xx
4977
+
ret_err = setup_embedded(hc, m);
4978
+
#else
4979
+
{
4980
+
printk(KERN_WARNING "Embedded IO Mode not selected\n");
4981
+
ret_err = -EIO;
4982
+
}
4983
+
#endif
5067
4984
if (ret_err) {
5068
4985
if (hc == syncmaster)
5069
4986
syncmaster = NULL;
···
5081
4978
return ret_err;
5082
4979
}
5083
4980
5084
-
/* crate channels */
4981
+
hc->HFC_outb_nodebug = hc->HFC_outb;
4982
+
hc->HFC_inb_nodebug = hc->HFC_inb;
4983
+
hc->HFC_inw_nodebug = hc->HFC_inw;
4984
+
hc->HFC_wait_nodebug = hc->HFC_wait;
4985
+
#ifdef HFC_REGISTER_DEBUG
4986
+
hc->HFC_outb = HFC_outb_debug;
4987
+
hc->HFC_inb = HFC_inb_debug;
4988
+
hc->HFC_inw = HFC_inw_debug;
4989
+
hc->HFC_wait = HFC_wait_debug;
4990
+
#endif
4991
+
/* create channels */
5085
4992
for (pt = 0; pt < hc->ports; pt++) {
5086
4993
if (Port_cnt >= MAX_PORTS) {
5087
4994
printk(KERN_ERR "too many ports (max=%d).\n",
···
5099
4986
ret_err = -EINVAL;
5100
4987
goto free_card;
5101
4988
}
5102
-
if (hc->type == 1)
4989
+
if (hc->ctype == HFC_TYPE_E1)
5103
4990
ret_err = init_e1_port(hc, m);
5104
4991
else
5105
4992
ret_err = init_multi_port(hc, pt);
···
5183
5070
hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5184
5071
5185
5072
/* initialize hardware */
5073
+
hc->irq = (m->irq) ? : hc->pci_dev->irq;
5186
5074
ret_err = init_card(hc);
5187
5075
if (ret_err) {
5188
5076
printk(KERN_ERR "init card returns %d\n", ret_err);
···
5234
5120
#define VENDOR_PRIM "PrimuX"
5235
5121
5236
5122
static const struct hm_map hfcm_map[] = {
5237
-
/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5238
-
/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
5239
-
/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5240
-
/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5241
-
/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5242
-
/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5243
-
/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
5244
-
/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5245
-
/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5246
-
/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5247
-
/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5248
-
/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5123
+
/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5124
+
/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5125
+
/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5126
+
/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5127
+
/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5128
+
/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5129
+
/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5130
+
/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5131
+
/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5132
+
/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5133
+
/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5134
+
/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5249
5135
5250
-
/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5136
+
/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5251
5137
/*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5252
-
HFC_IO_MODE_REGIO},
5253
-
/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5254
-
/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5138
+
HFC_IO_MODE_REGIO, 0},
5139
+
/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5140
+
/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5255
5141
5256
-
/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5257
-
/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5258
-
/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5142
+
/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5143
+
/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5144
+
/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5259
5145
5260
-
/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5261
-
/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5262
-
/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5263
-
/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5146
+
/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5147
+
/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5148
+
/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5149
+
/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5264
5150
5265
-
/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5266
-
/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5267
-
/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5151
+
/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5152
+
/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5153
+
/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5268
5154
5269
5155
/*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5270
-
HFC_IO_MODE_PLXSD},
5156
+
HFC_IO_MODE_PLXSD, 0},
5271
5157
/*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5272
-
HFC_IO_MODE_PLXSD},
5273
-
/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5274
-
/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5275
-
/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5158
+
HFC_IO_MODE_PLXSD, 0},
5159
+
/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5160
+
/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5161
+
/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5162
+
/*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5163
+
HFC_IO_MODE_EMBSD, XHFC_IRQ},
5276
5164
};
5277
5165
5278
5166
#undef H
···
5381
5265
"Please contact the driver maintainer for support.\n");
5382
5266
return -ENODEV;
5383
5267
}
5384
-
ret = hfcmulti_init(pdev, ent);
5268
+
ret = hfcmulti_init(m, pdev, ent);
5385
5269
if (ret)
5386
5270
return ret;
5387
5271
HFC_cnt++;
···
5411
5295
HFCmulti_init(void)
5412
5296
{
5413
5297
int err;
5298
+
int i, xhfc = 0;
5299
+
struct hm_map m;
5414
5300
5415
5301
printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5416
5302
···
5460
5342
if (!clock)
5461
5343
clock = 1;
5462
5344
5345
+
/* Register the embedded devices.
5346
+
* This should be done before the PCI cards registration */
5347
+
switch (hwid) {
5348
+
case HWID_MINIP4:
5349
+
xhfc = 1;
5350
+
m = hfcm_map[31];
5351
+
break;
5352
+
case HWID_MINIP8:
5353
+
xhfc = 2;
5354
+
m = hfcm_map[31];
5355
+
break;
5356
+
case HWID_MINIP16:
5357
+
xhfc = 4;
5358
+
m = hfcm_map[31];
5359
+
break;
5360
+
default:
5361
+
xhfc = 0;
5362
+
}
5363
+
5364
+
for (i = 0; i < xhfc; ++i) {
5365
+
err = hfcmulti_init(&m, NULL, NULL);
5366
+
if (err) {
5367
+
printk(KERN_ERR "error registering embedded driver: "
5368
+
"%x\n", err);
5369
+
return -err;
5370
+
}
5371
+
HFC_cnt++;
5372
+
printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5373
+
}
5374
+
5375
+
/* Register the PCI cards */
5463
5376
err = pci_register_driver(&hfcmultipci_driver);
5464
5377
if (err < 0) {
5465
5378
printk(KERN_ERR "error registering pci driver: %x\n", err);
5466
5379
return err;
5467
5380
}
5381
+
5468
5382
return 0;
5469
5383
}
5470
5384
+4
drivers/isdn/mISDN/dsp_cmx.c
+4
drivers/isdn/mISDN/dsp_cmx.c
···
947
947
if (current_conf >= 0) {
948
948
join_members:
949
949
list_for_each_entry(member, &conf->mlist, list) {
950
+
/* if no conference engine on our chip, change to
951
+
* software */
952
+
if (!member->dsp->features.hfc_conf)
953
+
goto conf_software;
950
954
/* in case of hdlc, change to software */
951
955
if (member->dsp->hdlc)
952
956
goto conf_software;
+1
include/linux/mISDNdsp.h
+1
include/linux/mISDNdsp.h
···
25
25
struct dsp_features {
26
26
int hfc_id; /* unique id to identify the chip (or -1) */
27
27
int hfc_dtmf; /* set if HFCmulti card supports dtmf */
28
+
int hfc_conf; /* set if HFCmulti card supports conferences */
28
29
int hfc_loops; /* set if card supports tone loops */
29
30
int hfc_echocanhw; /* set if card supports echocancelation*/
30
31
int pcm_id; /* unique id to identify the pcm bus (or -1) */