tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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net: ethernet: bgmac: convert to feature flags

The bgmac driver is using the bcma provides device ID and revision, as
well as the SoC ID and package, to determine which features are
necessary to enable, reset, etc in the driver. In anticipation of
removing the bcma requirement for this driver, these must be changed to
not reference that struct. In place of that, each "feature" has been
given a flag, and the flags are enabled for their respective device and
SoC.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Jon Mason and committed by
David S. Miller db791eb2 55954f3b

+140 -48
+120 -47
drivers/net/ethernet/broadcom/bgmac.c
··· 109 109 u32 ctl; 110 110 111 111 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 112 - if (bgmac->core->id.rev >= 4) { 112 + if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) { 113 113 ctl &= ~BGMAC_DMA_TX_BL_MASK; 114 114 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 115 115 ··· 331 331 u32 ctl; 332 332 333 333 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 334 - if (bgmac->core->id.rev >= 4) { 334 + if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { 335 335 ctl &= ~BGMAC_DMA_RX_BL_MASK; 336 336 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 337 337 ··· 769 769 { 770 770 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 771 771 u32 new_val = (cmdcfg & mask) | set; 772 + u32 cmdcfg_sr; 772 773 773 - bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 774 + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 775 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 776 + else 777 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 778 + 779 + bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr); 774 780 udelay(2); 775 781 776 782 if (new_val != cmdcfg || force) 777 783 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 778 784 779 - bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 785 + bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr); 780 786 udelay(2); 781 787 } 782 788 ··· 811 805 { 812 806 int i; 813 807 814 - if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 808 + if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) { 815 809 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 816 810 bgmac->mib_tx_regs[i] = 817 811 bgmac_read(bgmac, ··· 830 824 { 831 825 int i; 832 826 833 - if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 827 + if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB) 834 828 return; 835 829 836 830 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); ··· 873 867 static void bgmac_miiconfig(struct bgmac *bgmac) 874 868 { 875 869 struct bcma_device *core = bgmac->core; 876 - u8 imode; 877 870 878 - if (bgmac_is_bcm4707_family(bgmac)) { 871 + if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) { 879 872 bcma_awrite32(core, BCMA_IOCTL, 880 873 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 881 874 BGMAC_BCMA_IOCTL_SW_CLKEN); ··· 882 877 bgmac->mac_duplex = DUPLEX_FULL; 883 878 bgmac_mac_speed(bgmac); 884 879 } else { 880 + u8 imode; 881 + 885 882 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 886 883 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 887 884 if (imode == 0 || imode == 1) { ··· 898 891 static void bgmac_chip_reset(struct bgmac *bgmac) 899 892 { 900 893 struct bcma_device *core = bgmac->core; 901 - struct bcma_bus *bus = core->bus; 902 - struct bcma_chipinfo *ci = &bus->chipinfo; 903 - u32 flags; 894 + u32 cmdcfg_sr; 904 895 u32 iost; 905 896 int i; 906 897 ··· 921 916 } 922 917 923 918 iost = bcma_aread32(core, BCMA_IOST); 924 - if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 925 - (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 926 - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 919 + if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED) 927 920 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 928 921 929 922 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ 930 - if (ci->id != BCMA_CHIP_ID_BCM4707 && 931 - ci->id != BCMA_CHIP_ID_BCM47094) { 932 - flags = 0; 923 + if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) { 924 + u32 flags = 0; 933 925 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 934 926 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 935 927 if (!bgmac->has_robosw) ··· 936 934 } 937 935 938 936 /* Request Misc PLL for corerev > 2 */ 939 - if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) { 937 + if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) { 940 938 bgmac_set(bgmac, BCMA_CLKCTLST, 941 939 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 942 940 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, ··· 945 943 1000); 946 944 } 947 945 948 - if (ci->id == BCMA_CHIP_ID_BCM5357 || 949 - ci->id == BCMA_CHIP_ID_BCM4749 || 950 - ci->id == BCMA_CHIP_ID_BCM53572) { 946 + if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) { 951 947 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 952 948 u8 et_swtype = 0; 953 949 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | ··· 959 959 et_swtype &= 0x0f; 960 960 et_swtype <<= 4; 961 961 sw_type = et_swtype; 962 - } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 962 + } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) { 963 963 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 964 - } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 965 - (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 966 - (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 964 + } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) { 967 965 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 968 966 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 969 967 } ··· 981 983 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 982 984 * be keps until taking MAC out of the reset. 983 985 */ 986 + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 987 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 988 + else 989 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 990 + 984 991 bgmac_cmdcfg_maskset(bgmac, 985 992 ~(BGMAC_CMDCFG_TE | 986 993 BGMAC_CMDCFG_RE | ··· 1003 1000 BGMAC_CMDCFG_PROM | 1004 1001 BGMAC_CMDCFG_NLC | 1005 1002 BGMAC_CMDCFG_CFE | 1006 - BGMAC_CMDCFG_SR(core->id.rev), 1003 + cmdcfg_sr, 1007 1004 false); 1008 1005 bgmac->mac_speed = SPEED_UNKNOWN; 1009 1006 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1010 1007 1011 1008 bgmac_clear_mib(bgmac); 1012 - if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1009 + if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL) 1013 1010 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1014 1011 BCMA_GMAC_CMN_PC_MTE); 1015 1012 else ··· 1035 1032 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1036 1033 static void bgmac_enable(struct bgmac *bgmac) 1037 1034 { 1038 - struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1035 + u32 cmdcfg_sr; 1039 1036 u32 cmdcfg; 1040 1037 u32 mode; 1041 - u32 rxq_ctl; 1042 - u32 fl_ctl; 1043 - u16 bp_clk; 1044 - u8 mdp; 1038 + 1039 + if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) 1040 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; 1041 + else 1042 + cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; 1045 1043 1046 1044 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1047 1045 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1048 - BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1046 + cmdcfg_sr, true); 1049 1047 udelay(2); 1050 1048 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1051 1049 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1052 1050 1053 1051 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1054 1052 BGMAC_DS_MM_SHIFT; 1055 - if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1053 + if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) 1056 1054 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1057 - if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1055 + if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2) 1058 1056 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1059 1057 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1060 1058 1061 - switch (ci->id) { 1062 - case BCMA_CHIP_ID_BCM5357: 1063 - case BCMA_CHIP_ID_BCM4749: 1064 - case BCMA_CHIP_ID_BCM53572: 1065 - case BCMA_CHIP_ID_BCM4716: 1066 - case BCMA_CHIP_ID_BCM47162: 1067 - fl_ctl = 0x03cb04cb; 1068 - if (ci->id == BCMA_CHIP_ID_BCM5357 || 1069 - ci->id == BCMA_CHIP_ID_BCM4749 || 1070 - ci->id == BCMA_CHIP_ID_BCM53572) 1059 + if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 | 1060 + BGMAC_FEAT_FLW_CTRL2)) { 1061 + u32 fl_ctl; 1062 + 1063 + if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1) 1071 1064 fl_ctl = 0x2300e1; 1065 + else 1066 + fl_ctl = 0x03cb04cb; 1067 + 1072 1068 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1073 1069 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1074 - break; 1075 1070 } 1076 1071 1077 - if (!bgmac_is_bcm4707_family(bgmac)) { 1072 + if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) { 1073 + u32 rxq_ctl; 1074 + u16 bp_clk; 1075 + u8 mdp; 1076 + 1078 1077 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1079 1078 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1080 1079 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / ··· 1591 1586 1592 1587 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1593 1588 dev_warn(bgmac->dev, "Support for ADMtek ethernet switch not implemented\n"); 1589 + 1590 + /* Feature Flags */ 1591 + switch (core->bus->chipinfo.id) { 1592 + case BCMA_CHIP_ID_BCM5357: 1593 + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK; 1594 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1595 + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1; 1596 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY; 1597 + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47186) { 1598 + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED; 1599 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII; 1600 + } 1601 + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM5358) 1602 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_EPHYRMII; 1603 + break; 1604 + case BCMA_CHIP_ID_BCM53572: 1605 + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK; 1606 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1607 + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1; 1608 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY; 1609 + if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47188) { 1610 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII; 1611 + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED; 1612 + } 1613 + break; 1614 + case BCMA_CHIP_ID_BCM4749: 1615 + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK; 1616 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1617 + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1; 1618 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY; 1619 + if (core->bus->chipinfo.pkg == 10) { 1620 + bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII; 1621 + bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED; 1622 + } 1623 + break; 1624 + case BCMA_CHIP_ID_BCM4716: 1625 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1626 + /* fallthrough */ 1627 + case BCMA_CHIP_ID_BCM47162: 1628 + bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL2; 1629 + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK; 1630 + break; 1631 + /* bcm4707_family */ 1632 + case BCMA_CHIP_ID_BCM4707: 1633 + case BCMA_CHIP_ID_BCM47094: 1634 + case BCMA_CHIP_ID_BCM53018: 1635 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1636 + bgmac->feature_flags |= BGMAC_FEAT_NO_RESET; 1637 + bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500; 1638 + break; 1639 + default: 1640 + bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; 1641 + bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK; 1642 + } 1643 + 1644 + if (!bgmac_is_bcm4707_family(bgmac) && core->id.rev > 2) 1645 + bgmac->feature_flags |= BGMAC_FEAT_MISC_PLL_REQ; 1646 + 1647 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT) { 1648 + bgmac->feature_flags |= BGMAC_FEAT_CMN_PHY_CTL; 1649 + bgmac->feature_flags |= BGMAC_FEAT_NO_CLR_MIB; 1650 + } 1651 + 1652 + if (core->id.rev >= 4) { 1653 + bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4; 1654 + bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP; 1655 + bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP; 1656 + } 1594 1657 1595 1658 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1596 1659
+20 -1
drivers/net/ethernet/broadcom/bgmac.h
··· 190 190 #define BGMAC_CMDCFG_HD_SHIFT 10 191 191 #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ 192 192 #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ 193 - #define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) 194 193 #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ 195 194 #define BGMAC_CMDCFG_AE 0x00400000 196 195 #define BGMAC_CMDCFG_CFE 0x00800000 ··· 375 376 376 377 #define ETHER_MAX_LEN 1518 377 378 379 + /* Feature Flags */ 380 + #define BGMAC_FEAT_TX_MASK_SETUP BIT(0) 381 + #define BGMAC_FEAT_RX_MASK_SETUP BIT(1) 382 + #define BGMAC_FEAT_IOST_ATTACHED BIT(2) 383 + #define BGMAC_FEAT_NO_RESET BIT(3) 384 + #define BGMAC_FEAT_MISC_PLL_REQ BIT(4) 385 + #define BGMAC_FEAT_SW_TYPE_PHY BIT(5) 386 + #define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6) 387 + #define BGMAC_FEAT_SW_TYPE_RGMII BIT(7) 388 + #define BGMAC_FEAT_CMN_PHY_CTL BIT(8) 389 + #define BGMAC_FEAT_FLW_CTRL1 BIT(9) 390 + #define BGMAC_FEAT_FLW_CTRL2 BIT(10) 391 + #define BGMAC_FEAT_SET_RXQ_CLK BIT(11) 392 + #define BGMAC_FEAT_CLKCTLST BIT(12) 393 + #define BGMAC_FEAT_NO_CLR_MIB BIT(13) 394 + #define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14) 395 + #define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15) 396 + 378 397 struct bgmac_slot_info { 379 398 union { 380 399 struct sk_buff *skb; ··· 447 430 448 431 struct device *dev; 449 432 struct device *dma_dev; 433 + u32 feature_flags; 434 + 450 435 struct net_device *net_dev; 451 436 struct napi_struct napi; 452 437 struct mii_bus *mii_bus;