tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree conversions and enablement from Olof Johansson:
"Continued device tree conversion and enablement across a number of
platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
smaller series as well.
ux500 has seen continued conversion for platforms. Several platforms
have seen pinctrl-via-devicetree conversions for simpler
multiplatform. Tegra is adding data for new devices/drivers, and
Exynos has a bunch of new bindings and devices added as well.
So, pretty much the same progression in the right direction as the
last few releases."
Fix up conflicts as per Olof.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits)
ARM: ux500: Rename dbx500 cpufreq code to be more generic
ARM: dts: add missing ux500 device trees
ARM: ux500: Stop registering the PCM driver from platform code
ARM: ux500: Move board specific GPIO info out to subordinate DTS files
ARM: ux500: Disable the MMCI gpio-regulator by default
ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
ARM: Kirkwood: Add support LED of OpenBlocks A6
ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
ARM: kirkwood: Add support DT of second I2C bus
ARM: kirkwood: Convert mplcec4 board to pinctrl
ARM: Kirkwood: Convert km_kirkwood to pinctrl
ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
ARM: Kirkwood: Convert IX2-200 to pinctrl.
ARM: Kirkwood: Convert lsxl boards to pinctrl.
ARM: Kirkwood: Convert ib62x0 to pinctrl.
ARM: Kirkwood: Convert GoFlex Net to pinctrl.
ARM: Kirkwood: Convert dreamplug to pinctrl.
ARM: Kirkwood: Convert dockstar to pinctrl.
...
+8124
-1447
+11
-4
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+11
-4
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
···
4
4
to gate power to one or more peripherals on the processor.
5
5
6
6
Required Properties:
7
-
- compatiable: should be one of the following.
7
+
- compatible: should be one of the following.
8
8
* samsung,exynos4210-pd - for exynos4210 type power domain.
9
9
- reg: physical base address of the controller and length of memory mapped
10
10
region.
11
11
12
-
Optional Properties:
13
-
- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off
14
-
state during boot and remains to be turned-off until explicitly turned-on.
12
+
Node of a device using power domains must have a samsung,power-domain property
13
+
defined with a phandle to respective power domain.
15
14
16
15
Example:
17
16
18
17
lcd0: power-domain-lcd0 {
19
18
compatible = "samsung,exynos4210-pd";
20
19
reg = <0x10023C00 0x10>;
20
+
};
21
+
22
+
Example of the node using power domain:
23
+
24
+
node {
25
+
/* ... */
26
+
samsung,power-domain = <&lcd0>;
27
+
/* ... */
21
28
};
+4
Documentation/devicetree/bindings/arm/fsl.txt
+4
Documentation/devicetree/bindings/arm/fsl.txt
+14
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+14
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
···
1
+
* Samsung SATA PHY Controller
2
+
3
+
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
4
+
Each SATA PHY controller should have its own node.
5
+
6
+
Required properties:
7
+
- compatible : compatible list, contains "samsung,exynos5-sata-phy"
8
+
- reg : <registers mapping>
9
+
10
+
Example:
11
+
sata@ffe07000 {
12
+
compatible = "samsung,exynos5-sata-phy";
13
+
reg = <0xffe07000 0x1000>;
14
+
};
+17
Documentation/devicetree/bindings/ata/exynos-sata.txt
+17
Documentation/devicetree/bindings/ata/exynos-sata.txt
···
1
+
* Samsung AHCI SATA Controller
2
+
3
+
SATA nodes are defined to describe on-chip Serial ATA controllers.
4
+
Each SATA controller should have its own node.
5
+
6
+
Required properties:
7
+
- compatible : compatible list, contains "samsung,exynos5-sata"
8
+
- interrupts : <interrupt mapping for SATA IRQ>
9
+
- reg : <registers mapping>
10
+
- samsung,sata-freq : <frequency in MHz>
11
+
12
+
Example:
13
+
sata@ffe08000 {
14
+
compatible = "samsung,exynos5-sata";
15
+
reg = <0xffe08000 0x1000>;
16
+
interrupts = <115>;
17
+
};
+162
Documentation/devicetree/bindings/clock/imx25-clock.txt
+162
Documentation/devicetree/bindings/clock/imx25-clock.txt
···
1
+
* Clock bindings for Freescale i.MX25
2
+
3
+
Required properties:
4
+
- compatible: Should be "fsl,imx25-ccm"
5
+
- reg: Address and length of the register set
6
+
- interrupts: Should contain CCM interrupt
7
+
- #clock-cells: Should be <1>
8
+
9
+
The clock consumer should specify the desired clock by having the clock
10
+
ID in its "clocks" phandle cell. The following is a full list of i.MX25
11
+
clocks and IDs.
12
+
13
+
Clock ID
14
+
---------------------------
15
+
dummy 0
16
+
osc 1
17
+
mpll 2
18
+
upll 3
19
+
mpll_cpu_3_4 4
20
+
cpu_sel 5
21
+
cpu 6
22
+
ahb 7
23
+
usb_div 8
24
+
ipg 9
25
+
per0_sel 10
26
+
per1_sel 11
27
+
per2_sel 12
28
+
per3_sel 13
29
+
per4_sel 14
30
+
per5_sel 15
31
+
per6_sel 16
32
+
per7_sel 17
33
+
per8_sel 18
34
+
per9_sel 19
35
+
per10_sel 20
36
+
per11_sel 21
37
+
per12_sel 22
38
+
per13_sel 23
39
+
per14_sel 24
40
+
per15_sel 25
41
+
per0 26
42
+
per1 27
43
+
per2 28
44
+
per3 29
45
+
per4 30
46
+
per5 31
47
+
per6 32
48
+
per7 33
49
+
per8 34
50
+
per9 35
51
+
per10 36
52
+
per11 37
53
+
per12 38
54
+
per13 39
55
+
per14 40
56
+
per15 41
57
+
csi_ipg_per 42
58
+
epit_ipg_per 43
59
+
esai_ipg_per 44
60
+
esdhc1_ipg_per 45
61
+
esdhc2_ipg_per 46
62
+
gpt_ipg_per 47
63
+
i2c_ipg_per 48
64
+
lcdc_ipg_per 49
65
+
nfc_ipg_per 50
66
+
owire_ipg_per 51
67
+
pwm_ipg_per 52
68
+
sim1_ipg_per 53
69
+
sim2_ipg_per 54
70
+
ssi1_ipg_per 55
71
+
ssi2_ipg_per 56
72
+
uart_ipg_per 57
73
+
ata_ahb 58
74
+
reserved 59
75
+
csi_ahb 60
76
+
emi_ahb 61
77
+
esai_ahb 62
78
+
esdhc1_ahb 63
79
+
esdhc2_ahb 64
80
+
fec_ahb 65
81
+
lcdc_ahb 66
82
+
rtic_ahb 67
83
+
sdma_ahb 68
84
+
slcdc_ahb 69
85
+
usbotg_ahb 70
86
+
reserved 71
87
+
reserved 72
88
+
reserved 73
89
+
reserved 74
90
+
can1_ipg 75
91
+
can2_ipg 76
92
+
csi_ipg 77
93
+
cspi1_ipg 78
94
+
cspi2_ipg 79
95
+
cspi3_ipg 80
96
+
dryice_ipg 81
97
+
ect_ipg 82
98
+
epit1_ipg 83
99
+
epit2_ipg 84
100
+
reserved 85
101
+
esdhc1_ipg 86
102
+
esdhc2_ipg 87
103
+
fec_ipg 88
104
+
reserved 89
105
+
reserved 90
106
+
reserved 91
107
+
gpt1_ipg 92
108
+
gpt2_ipg 93
109
+
gpt3_ipg 94
110
+
gpt4_ipg 95
111
+
reserved 96
112
+
reserved 97
113
+
reserved 98
114
+
iim_ipg 99
115
+
reserved 100
116
+
reserved 101
117
+
kpp_ipg 102
118
+
lcdc_ipg 103
119
+
reserved 104
120
+
pwm1_ipg 105
121
+
pwm2_ipg 106
122
+
pwm3_ipg 107
123
+
pwm4_ipg 108
124
+
rngb_ipg 109
125
+
reserved 110
126
+
scc_ipg 111
127
+
sdma_ipg 112
128
+
sim1_ipg 113
129
+
sim2_ipg 114
130
+
slcdc_ipg 115
131
+
spba_ipg 116
132
+
ssi1_ipg 117
133
+
ssi2_ipg 118
134
+
tsc_ipg 119
135
+
uart1_ipg 120
136
+
uart2_ipg 121
137
+
uart3_ipg 122
138
+
uart4_ipg 123
139
+
uart5_ipg 124
140
+
reserved 125
141
+
wdt_ipg 126
142
+
143
+
Examples:
144
+
145
+
clks: ccm@53f80000 {
146
+
compatible = "fsl,imx25-ccm";
147
+
reg = <0x53f80000 0x4000>;
148
+
interrupts = <31>;
149
+
clock-output-names = ...
150
+
"uart_ipg",
151
+
"uart_serial",
152
+
...;
153
+
};
154
+
155
+
uart1: serial@43f90000 {
156
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
157
+
reg = <0x43f90000 0x4000>;
158
+
interrupts = <45>;
159
+
clocks = <&clks 79>, <&clks 50>;
160
+
clock-names = "ipg", "per";
161
+
status = "disabled";
162
+
};
+55
Documentation/devicetree/bindings/clock/zynq-7000.txt
+55
Documentation/devicetree/bindings/clock/zynq-7000.txt
···
1
+
Device Tree Clock bindings for the Zynq 7000 EPP
2
+
3
+
The Zynq EPP has several different clk providers, each with there own bindings.
4
+
The purpose of this document is to document their usage.
5
+
6
+
See clock_bindings.txt for more information on the generic clock bindings.
7
+
See Chapter 25 of Zynq TRM for more information about Zynq clocks.
8
+
9
+
== PLLs ==
10
+
11
+
Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
12
+
13
+
Required properties:
14
+
- #clock-cells : shall be 0 (only one clock is output from this node)
15
+
- compatible : "xlnx,zynq-pll"
16
+
- reg : pair of u32 values, which are the address offsets within the SLCR
17
+
of the relevant PLL_CTRL register and PLL_CFG register respectively
18
+
- clocks : phandle for parent clock. should be the phandle for ps_clk
19
+
20
+
Optional properties:
21
+
- clock-output-names : name of the output clock
22
+
23
+
Example:
24
+
armpll: armpll {
25
+
#clock-cells = <0>;
26
+
compatible = "xlnx,zynq-pll";
27
+
clocks = <&ps_clk>;
28
+
reg = <0x100 0x110>;
29
+
clock-output-names = "armpll";
30
+
};
31
+
32
+
== Peripheral clocks ==
33
+
34
+
Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
35
+
36
+
Required properties:
37
+
- #clock-cells : shall be 1
38
+
- compatible : "xlnx,zynq-periph-clock"
39
+
- reg : a single u32 value, describing the offset within the SLCR where
40
+
the CLK_CTRL register is found for this peripheral
41
+
- clocks : phandle for parent clocks. should hold phandles for
42
+
the IO_PLL, ARM_PLL, and DDR_PLL in order
43
+
- clock-output-names : names of the output clock(s). For peripherals that have
44
+
two output clocks (for example, the UART), two clocks
45
+
should be listed.
46
+
47
+
Example:
48
+
uart_clk: uart_clk {
49
+
#clock-cells = <1>;
50
+
compatible = "xlnx,zynq-periph-clock";
51
+
clocks = <&iopll &armpll &ddrpll>;
52
+
reg = <0x154>;
53
+
clock-output-names = "uart0_ref_clk",
54
+
"uart1_ref_clk";
55
+
};
+22
Documentation/devicetree/bindings/drm/exynos/hdmi.txt
+22
Documentation/devicetree/bindings/drm/exynos/hdmi.txt
···
1
+
Device-Tree bindings for drm hdmi driver
2
+
3
+
Required properties:
4
+
- compatible: value should be "samsung,exynos5-hdmi".
5
+
- reg: physical base address of the hdmi and length of memory mapped
6
+
region.
7
+
- interrupts: interrupt number to the cpu.
8
+
- hpd-gpio: following information about the hotplug gpio pin.
9
+
a) phandle of the gpio controller node.
10
+
b) pin number within the gpio controller.
11
+
c) pin function mode.
12
+
d) optional flags and pull up/down.
13
+
e) drive strength.
14
+
15
+
Example:
16
+
17
+
hdmi {
18
+
compatible = "samsung,exynos5-hdmi";
19
+
reg = <0x14530000 0x100000>;
20
+
interrupts = <0 95 0>;
21
+
hpd-gpio = <&gpx3 7 0xf 1 3>;
22
+
};
+12
Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
+12
Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
+12
Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
+12
Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
+15
Documentation/devicetree/bindings/drm/exynos/mixer.txt
+15
Documentation/devicetree/bindings/drm/exynos/mixer.txt
···
1
+
Device-Tree bindings for mixer driver
2
+
3
+
Required properties:
4
+
- compatible: value should be "samsung,exynos5-mixer".
5
+
- reg: physical base address of the mixer and length of memory mapped
6
+
region.
7
+
- interrupts: interrupt number to the cpu.
8
+
9
+
Example:
10
+
11
+
mixer {
12
+
compatible = "samsung,exynos5-mixer";
13
+
reg = <0x14450000 0x10000>;
14
+
interrupts = <0 94 0>;
15
+
};
+22
Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
+22
Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
···
1
+
GPIO line that should be set high/low to power off a device
2
+
3
+
Required properties:
4
+
- compatible : should be "gpio-poweroff".
5
+
- gpios : The GPIO to set high/low, see "gpios property" in
6
+
Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
7
+
low to power down the board set it to "Active Low", otherwise set
8
+
gpio to "Active High".
9
+
10
+
Optional properties:
11
+
- input : Initially configure the GPIO line as an input. Only reconfigure
12
+
it to an output when the pm_power_off function is called. If this optional
13
+
property is not specified, the GPIO is initialized as an output in its
14
+
inactive state.
15
+
16
+
17
+
Examples:
18
+
19
+
gpio-poweroff {
20
+
compatible = "gpio-poweroff";
21
+
gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
22
+
};
+28
Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
+28
Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
···
1
+
* Rohm BU21013 Touch Screen
2
+
3
+
Required properties:
4
+
- compatible : "rohm,bu21013_tp"
5
+
- reg : I2C device address
6
+
7
+
Optional properties:
8
+
- touch-gpio : GPIO pin registering a touch event
9
+
- <supply_name>-supply : Phandle to a regulator supply
10
+
- rohm,touch-max-x : Maximum outward permitted limit in the X axis
11
+
- rohm,touch-max-y : Maximum outward permitted limit in the Y axis
12
+
- rohm,flip-x : Flip touch coordinates on the X axis
13
+
- rohm,flip-y : Flip touch coordinates on the Y axis
14
+
15
+
Example:
16
+
17
+
i2c@80110000 {
18
+
bu21013_tp@0x5c {
19
+
compatible = "rohm,bu21013_tp";
20
+
reg = <0x5c>;
21
+
touch-gpio = <&gpio2 20 0x4>;
22
+
avdd-supply = <&ab8500_ldo_aux1_reg>;
23
+
24
+
rohm,touch-max-x = <384>;
25
+
rohm,touch-max-y = <704>;
26
+
rohm,flip-y;
27
+
};
28
+
};
+23
Documentation/devicetree/bindings/media/s5p-mfc.txt
+23
Documentation/devicetree/bindings/media/s5p-mfc.txt
···
1
+
* Samsung Multi Format Codec (MFC)
2
+
3
+
Multi Format Codec (MFC) is the IP present in Samsung SoCs which
4
+
supports high resolution decoding and encoding functionalities.
5
+
The MFC device driver is a v4l2 driver which can encode/decode
6
+
video raw/elementary streams and has support for all popular
7
+
video codecs.
8
+
9
+
Required properties:
10
+
- compatible : value should be either one among the following
11
+
(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12
+
(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13
+
14
+
- reg : Physical base address of the IP registers and length of memory
15
+
mapped region.
16
+
17
+
- interrupts : MFC interrupt number to the CPU.
18
+
19
+
- samsung,mfc-r : Base address of the first memory bank used by MFC
20
+
for DMA contiguous memory allocation and its size.
21
+
22
+
- samsung,mfc-l : Base address of the second memory bank used by MFC
23
+
for DMA contiguous memory allocation and its size.
+39
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+39
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
···
7
7
- compatible: "marvell,88f6180-pinctrl",
8
8
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9
9
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10
+
"marvell,98dx4122-pinctrl"
10
11
11
12
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13
+
It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
12
14
13
15
Available mpp pins/groups and functions:
14
16
Note: brackets (x) are not part of the mpp name for marvell,function and given
···
279
277
mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
280
278
mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
281
279
mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
280
+
281
+
* Marvell Bobcat 98dx4122
282
+
283
+
name pins functions
284
+
================================================================================
285
+
mpp0 0 gpio, nand(io2), spi(cs)
286
+
mpp1 1 gpo, nand(io3), spi(mosi)
287
+
mpp2 2 gpo, nand(io4), spi(sck)
288
+
mpp3 3 gpo, nand(io5), spi(miso)
289
+
mpp4 4 gpio, nand(io6), uart0(rxd)
290
+
mpp5 5 gpo, nand(io7), uart0(txd)
291
+
mpp6 6 sysrst(out), spi(mosi)
292
+
mpp7 7 gpo, pex(rsto), spi(cs)
293
+
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts)
294
+
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts)
295
+
mpp10 10 gpo, spi(sck), uart0(txd)
296
+
mpp11 11 gpio, spi(miso), uart0(rxd)
297
+
mpp13 13 gpio, uart1(txd)
298
+
mpp14 14 gpio, uart1(rxd)
299
+
mpp15 15 gpio, uart0(rts)
300
+
mpp16 16 gpio, uart0(cts)
301
+
mpp18 18 gpo, nand(io0)
302
+
mpp19 19 gpo, nand(io1)
303
+
mpp34 34 gpio
304
+
mpp35 35 gpio
305
+
mpp36 36 gpio
306
+
mpp37 37 gpio
307
+
mpp38 38 gpio
308
+
mpp39 39 gpio
309
+
mpp40 40 gpio
310
+
mpp41 41 gpio
311
+
mpp42 42 gpio
312
+
mpp43 43 gpio
313
+
mpp44 44 gpio
314
+
mpp45 45 gpio
315
+
mpp49 49 gpio
316
+
+15
Documentation/devicetree/bindings/usb/ehci-orion.txt
+15
Documentation/devicetree/bindings/usb/ehci-orion.txt
···
1
+
* EHCI controller, Orion Marvell variants
2
+
3
+
Required properties:
4
+
- compatible: must be "marvell,orion-ehci"
5
+
- reg: physical base address of the controller and length of memory mapped
6
+
region.
7
+
- interrupts: The EHCI interrupt
8
+
9
+
Example:
10
+
11
+
ehci@50000 {
12
+
compatible = "marvell,orion-ehci";
13
+
reg = <0x50000 0x1000>;
14
+
interrupts = <19>;
15
+
};
+1
Documentation/devicetree/bindings/vendor-prefixes.txt
+1
Documentation/devicetree/bindings/vendor-prefixes.txt
+15
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+15
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
···
1
+
* Atmel Watchdog Timers
2
+
3
+
** at91sam9-wdt
4
+
5
+
Required properties:
6
+
- compatible: must be "atmel,at91sam9260-wdt".
7
+
- reg: physical base address of the controller and length of memory mapped
8
+
region.
9
+
10
+
Example:
11
+
12
+
watchdog@fffffd40 {
13
+
compatible = "atmel,at91sam9260-wdt";
14
+
reg = <0xfffffd40 0x10>;
15
+
};
+5
arch/arm/Kconfig
+5
arch/arm/Kconfig
···
536
536
select CPU_V7
537
537
select GENERIC_CLOCKEVENTS
538
538
select MIGHT_HAVE_PCI
539
+
select PINCTRL
540
+
select PINCTRL_DOVE
539
541
select PLAT_ORION_LEGACY
540
542
select USB_ARCH_HAS_EHCI
541
543
help
···
550
548
select GENERIC_CLOCKEVENTS
551
549
select PCI
552
550
select PCI_QUIRKS
551
+
select PINCTRL
552
+
select PINCTRL_KIRKWOOD
553
553
select PLAT_ORION_LEGACY
554
554
help
555
555
Support for the following Marvell Kirkwood series SoCs:
···
966
962
bool "Xilinx Zynq ARM Cortex A9 Platform"
967
963
select ARM_AMBA
968
964
select ARM_GIC
965
+
select COMMON_CLK
969
966
select CPU_V7
970
967
select GENERIC_CLOCKEVENTS
971
968
select ICST
+30
-13
arch/arm/Kconfig.debug
+30
-13
arch/arm/Kconfig.debug
···
132
132
their output to UART1 serial port on DaVinci TNETV107X
133
133
devices.
134
134
135
+
config DEBUG_ZYNQ_UART0
136
+
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
137
+
depends on ARCH_ZYNQ
138
+
help
139
+
Say Y here if you want the debug print routines to direct
140
+
their output to UART0 on the Zynq platform.
141
+
142
+
config DEBUG_ZYNQ_UART1
143
+
bool "Kernel low-level debugging on Xilinx Zynq using UART1"
144
+
depends on ARCH_ZYNQ
145
+
help
146
+
Say Y here if you want the debug print routines to direct
147
+
their output to UART1 on the Zynq platform.
148
+
149
+
If you have a ZC702 board and want early boot messages to
150
+
appear on the USB serial adaptor, select this option.
151
+
135
152
config DEBUG_DC21285_PORT
136
153
bool "Kernel low-level debugging messages via footbridge serial port"
137
154
depends on FOOTBRIDGE
···
226
209
Say Y here if you want kernel low-level debugging support
227
210
on i.MX50 or i.MX53.
228
211
229
-
config DEBUG_IMX6Q_UART2
230
-
bool "i.MX6Q Debug UART2"
212
+
config DEBUG_IMX6Q_UART
213
+
bool "i.MX6Q Debug UART"
231
214
depends on SOC_IMX6Q
232
215
help
233
216
Say Y here if you want kernel low-level debugging support
234
-
on i.MX6Q UART2. This is correct for e.g. the SabreLite
235
-
board.
236
-
237
-
config DEBUG_IMX6Q_UART4
238
-
bool "i.MX6Q Debug UART4"
239
-
depends on SOC_IMX6Q
240
-
help
241
-
Say Y here if you want kernel low-level debugging support
242
-
on i.MX6Q UART4.
217
+
on i.MX6Q.
243
218
244
219
config DEBUG_MMP_UART2
245
220
bool "Kernel low-level debugging message via MMP UART2"
···
443
434
444
435
endchoice
445
436
437
+
config DEBUG_IMX6Q_UART_PORT
438
+
int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART
439
+
range 1 5
440
+
default 1
441
+
depends on SOC_IMX6Q
442
+
help
443
+
Choose UART port on which kernel low-level debug messages
444
+
should be output.
445
+
446
446
config DEBUG_LL_INCLUDE
447
447
string
448
448
default "debug/icedcc.S" if DEBUG_ICEDCC
···
461
443
DEBUG_IMX31_IMX35_UART || \
462
444
DEBUG_IMX51_UART || \
463
445
DEBUG_IMX50_IMX53_UART ||\
464
-
DEBUG_IMX6Q_UART2 || \
465
-
DEBUG_IMX6Q_UART4
446
+
DEBUG_IMX6Q_UART
466
447
default "debug/highbank.S" if DEBUG_HIGHBANK_UART
467
448
default "debug/mvebu.S" if DEBUG_MVEBU_UART
468
449
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+15
-2
arch/arm/boot/dts/Makefile
+15
-2
arch/arm/boot/dts/Makefile
···
34
34
35
35
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
36
36
dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
37
+
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
38
+
da850-evm.dtb
37
39
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
38
40
dove-cubox.dtb \
39
41
dove-dove-db.dtb
···
43
41
exynos4210-smdkv310.dtb \
44
42
exynos4210-trats.dtb \
45
43
exynos5250-smdk5250.dtb \
46
-
exynos5440-ssdk5440.dtb
44
+
exynos5440-ssdk5440.dtb \
45
+
exynos4412-smdk4412.dtb \
46
+
exynos5250-smdk5250.dtb \
47
+
exynos5250-snow.dtb
47
48
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
48
49
ecx-2000.dtb
49
50
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
···
84
79
imx53-qsb.dtb \
85
80
imx53-smd.dtb \
86
81
imx6q-arm2.dtb \
82
+
imx6q-sabreauto.dtb \
87
83
imx6q-sabrelite.dtb \
88
84
imx6q-sabresd.dtb
89
85
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
90
86
imx23-olinuxino.dtb \
91
87
imx23-stmp378x_devb.dtb \
88
+
imx28-apf28.dtb \
89
+
imx28-apf28dev.dtb \
92
90
imx28-apx4devkit.dtb \
93
91
imx28-cfa10036.dtb \
94
92
imx28-cfa10049.dtb \
95
93
imx28-evk.dtb \
96
94
imx28-m28evk.dtb \
95
+
imx28-sps1.dtb \
97
96
imx28-tx28.dtb
98
97
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
99
98
omap3-beagle.dtb \
···
114
105
am335x-bone.dtb
115
106
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
116
107
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
117
-
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
108
+
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
109
+
hrefprev60.dtb \
110
+
hrefv60plus.dtb \
111
+
ccu9540.dtb
118
112
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
119
113
r8a7740-armadillo800eva.dtb \
120
114
sh73a0-kzm9g.dtb \
···
149
137
dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
150
138
wm8505-ref.dtb \
151
139
wm8650-mid.dtb
140
+
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
152
141
153
142
targets += dtbs
154
143
endif
+6
arch/arm/boot/dts/at91sam9260.dtsi
+6
arch/arm/boot/dts/at91sam9260.dtsi
+6
arch/arm/boot/dts/at91sam9263.dtsi
+6
arch/arm/boot/dts/at91sam9263.dtsi
+6
arch/arm/boot/dts/at91sam9g45.dtsi
+6
arch/arm/boot/dts/at91sam9g45.dtsi
+72
arch/arm/boot/dts/ccu9540.dts
+72
arch/arm/boot/dts/ccu9540.dts
···
1
+
/*
2
+
* Copyright 2012 ST-Ericsson AB
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "dbx5x0.dtsi"
14
+
15
+
/ {
16
+
model = "ST-Ericsson CCU9540 platform with Device Tree";
17
+
compatible = "st-ericsson,ccu9540", "st-ericsson,u9540";
18
+
19
+
memory {
20
+
reg = <0x00000000 0x20000000>;
21
+
};
22
+
23
+
soc-u9500 {
24
+
uart@80120000 {
25
+
status = "okay";
26
+
};
27
+
28
+
uart@80121000 {
29
+
status = "okay";
30
+
};
31
+
32
+
uart@80007000 {
33
+
status = "okay";
34
+
};
35
+
36
+
// External Micro SD slot
37
+
sdi0_per1@80126000 {
38
+
arm,primecell-periphid = <0x10480180>;
39
+
max-frequency = <100000000>;
40
+
bus-width = <4>;
41
+
mmc-cap-sd-highspeed;
42
+
mmc-cap-mmc-highspeed;
43
+
vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
+
45
+
cd-gpios = <&gpio7 6 0x4>; // 230
46
+
cd-inverted;
47
+
48
+
status = "okay";
49
+
};
50
+
51
+
52
+
// WLAN SDIO channel
53
+
sdi1_per2@80118000 {
54
+
arm,primecell-periphid = <0x10480180>;
55
+
max-frequency = <50000000>;
56
+
bus-width = <4>;
57
+
58
+
status = "okay";
59
+
};
60
+
61
+
// On-board eMMC
62
+
sdi4_per2@80114000 {
63
+
arm,primecell-periphid = <0x10480180>;
64
+
max-frequency = <100000000>;
65
+
bus-width = <8>;
66
+
mmc-cap-mmc-highspeed;
67
+
vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
+
69
+
status = "okay";
70
+
};
71
+
};
72
+
};
+184
arch/arm/boot/dts/cros5250-common.dtsi
+184
arch/arm/boot/dts/cros5250-common.dtsi
···
1
+
/*
2
+
* Common device tree include for all Exynos 5250 boards based off of Daisy.
3
+
*
4
+
* Copyright (c) 2012 Google, Inc
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
/ {
12
+
aliases {
13
+
};
14
+
15
+
memory {
16
+
reg = <0x40000000 0x80000000>;
17
+
};
18
+
19
+
chosen {
20
+
};
21
+
22
+
i2c@12C60000 {
23
+
samsung,i2c-sda-delay = <100>;
24
+
samsung,i2c-max-bus-freq = <378000>;
25
+
gpios = <&gpb3 0 2 3 0>,
26
+
<&gpb3 1 2 3 0>;
27
+
};
28
+
29
+
i2c@12C70000 {
30
+
samsung,i2c-sda-delay = <100>;
31
+
samsung,i2c-max-bus-freq = <378000>;
32
+
gpios = <&gpb3 2 2 3 0>,
33
+
<&gpb3 3 2 3 0>;
34
+
};
35
+
36
+
i2c@12C80000 {
37
+
samsung,i2c-sda-delay = <100>;
38
+
samsung,i2c-max-bus-freq = <66000>;
39
+
40
+
/*
41
+
* Disabled pullups since external part has its own pullups and
42
+
* double-pulling gets us out of spec in some cases.
43
+
*/
44
+
gpios = <&gpa0 6 3 0 0>,
45
+
<&gpa0 7 3 0 0>;
46
+
47
+
hdmiddc@50 {
48
+
compatible = "samsung,exynos5-hdmiddc";
49
+
reg = <0x50>;
50
+
};
51
+
};
52
+
53
+
i2c@12C90000 {
54
+
samsung,i2c-sda-delay = <100>;
55
+
samsung,i2c-max-bus-freq = <66000>;
56
+
gpios = <&gpa1 2 3 3 0>,
57
+
<&gpa1 3 3 3 0>;
58
+
};
59
+
60
+
i2c@12CA0000 {
61
+
status = "disabled";
62
+
};
63
+
64
+
i2c@12CB0000 {
65
+
samsung,i2c-sda-delay = <100>;
66
+
samsung,i2c-max-bus-freq = <66000>;
67
+
gpios = <&gpa2 2 3 3 0>,
68
+
<&gpa2 3 3 3 0>;
69
+
};
70
+
71
+
i2c@12CC0000 {
72
+
status = "disabled";
73
+
};
74
+
75
+
i2c@12CD0000 {
76
+
samsung,i2c-sda-delay = <100>;
77
+
samsung,i2c-max-bus-freq = <66000>;
78
+
gpios = <&gpb2 2 3 3 0>,
79
+
<&gpb2 3 3 3 0>;
80
+
};
81
+
82
+
i2c@12CE0000 {
83
+
samsung,i2c-sda-delay = <100>;
84
+
samsung,i2c-max-bus-freq = <378000>;
85
+
86
+
hdmiphy@38 {
87
+
compatible = "samsung,exynos5-hdmiphy";
88
+
reg = <0x38>;
89
+
};
90
+
};
91
+
92
+
dwmmc0@12200000 {
93
+
num-slots = <1>;
94
+
supports-highspeed;
95
+
broken-cd;
96
+
fifo-depth = <0x80>;
97
+
card-detect-delay = <200>;
98
+
samsung,dw-mshc-ciu-div = <3>;
99
+
samsung,dw-mshc-sdr-timing = <2 3 3>;
100
+
samsung,dw-mshc-ddr-timing = <1 2 3>;
101
+
102
+
slot@0 {
103
+
reg = <0>;
104
+
bus-width = <8>;
105
+
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
106
+
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
107
+
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
108
+
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
109
+
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
110
+
};
111
+
};
112
+
113
+
dwmmc1@12210000 {
114
+
status = "disabled";
115
+
};
116
+
117
+
dwmmc2@12220000 {
118
+
num-slots = <1>;
119
+
supports-highspeed;
120
+
fifo-depth = <0x80>;
121
+
card-detect-delay = <200>;
122
+
samsung,dw-mshc-ciu-div = <3>;
123
+
samsung,dw-mshc-sdr-timing = <2 3 3>;
124
+
samsung,dw-mshc-ddr-timing = <1 2 3>;
125
+
126
+
slot@0 {
127
+
reg = <0>;
128
+
bus-width = <4>;
129
+
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
130
+
wp-gpios = <&gpc2 1 0 0 3>;
131
+
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
132
+
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
133
+
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
134
+
};
135
+
};
136
+
137
+
dwmmc3@12230000 {
138
+
num-slots = <1>;
139
+
supports-highspeed;
140
+
broken-cd;
141
+
fifo-depth = <0x80>;
142
+
card-detect-delay = <200>;
143
+
samsung,dw-mshc-ciu-div = <3>;
144
+
samsung,dw-mshc-sdr-timing = <2 3 3>;
145
+
samsung,dw-mshc-ddr-timing = <1 2 3>;
146
+
147
+
slot@0 {
148
+
reg = <0>;
149
+
bus-width = <4>;
150
+
/* See board-specific dts files for GPIOs */
151
+
};
152
+
};
153
+
154
+
spi_0: spi@12d20000 {
155
+
status = "disabled";
156
+
};
157
+
158
+
spi_1: spi@12d30000 {
159
+
gpios = <&gpa2 4 2 3 0>,
160
+
<&gpa2 6 2 3 0>,
161
+
<&gpa2 7 2 3 0>;
162
+
samsung,spi-src-clk = <0>;
163
+
num-cs = <1>;
164
+
};
165
+
166
+
spi_2: spi@12d40000 {
167
+
status = "disabled";
168
+
};
169
+
170
+
hdmi {
171
+
hpd-gpio = <&gpx3 7 0xf 1 3>;
172
+
};
173
+
174
+
gpio-keys {
175
+
compatible = "gpio-keys";
176
+
177
+
power {
178
+
label = "Power";
179
+
gpios = <&gpx1 3 0 0x10000 0>;
180
+
linux,code = <116>; /* KEY_POWER */
181
+
gpio-key,wakeup;
182
+
};
183
+
};
184
+
};
+19
-37
arch/arm/boot/dts/dbx5x0.dtsi
+19
-37
arch/arm/boot/dts/dbx5x0.dtsi
···
217
217
// DB8500_REGULATOR_VAPE
218
218
db8500_vape_reg: db8500_vape {
219
219
regulator-compatible = "db8500_vape";
220
-
regulator-name = "db8500-vape";
221
220
regulator-always-on;
222
221
};
223
222
224
223
// DB8500_REGULATOR_VARM
225
224
db8500_varm_reg: db8500_varm {
226
225
regulator-compatible = "db8500_varm";
227
-
regulator-name = "db8500-varm";
228
226
};
229
227
230
228
// DB8500_REGULATOR_VMODEM
231
229
db8500_vmodem_reg: db8500_vmodem {
232
230
regulator-compatible = "db8500_vmodem";
233
-
regulator-name = "db8500-vmodem";
234
231
};
235
232
236
233
// DB8500_REGULATOR_VPLL
237
234
db8500_vpll_reg: db8500_vpll {
238
235
regulator-compatible = "db8500_vpll";
239
-
regulator-name = "db8500-vpll";
240
236
};
241
237
242
238
// DB8500_REGULATOR_VSMPS1
243
239
db8500_vsmps1_reg: db8500_vsmps1 {
244
240
regulator-compatible = "db8500_vsmps1";
245
-
regulator-name = "db8500-vsmps1";
246
241
};
247
242
248
243
// DB8500_REGULATOR_VSMPS2
249
244
db8500_vsmps2_reg: db8500_vsmps2 {
250
245
regulator-compatible = "db8500_vsmps2";
251
-
regulator-name = "db8500-vsmps2";
252
246
};
253
247
254
248
// DB8500_REGULATOR_VSMPS3
255
249
db8500_vsmps3_reg: db8500_vsmps3 {
256
250
regulator-compatible = "db8500_vsmps3";
257
-
regulator-name = "db8500-vsmps3";
258
251
};
259
252
260
253
// DB8500_REGULATOR_VRF1
261
254
db8500_vrf1_reg: db8500_vrf1 {
262
255
regulator-compatible = "db8500_vrf1";
263
-
regulator-name = "db8500-vrf1";
264
256
};
265
257
266
258
// DB8500_REGULATOR_SWITCH_SVAMMDSP
267
259
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
268
260
regulator-compatible = "db8500_sva_mmdsp";
269
-
regulator-name = "db8500-sva-mmdsp";
270
261
};
271
262
272
263
// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
273
264
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
274
265
regulator-compatible = "db8500_sva_mmdsp_ret";
275
-
regulator-name = "db8500-sva-mmdsp-ret";
276
266
};
277
267
278
268
// DB8500_REGULATOR_SWITCH_SVAPIPE
279
269
db8500_sva_pipe_reg: db8500_sva_pipe {
280
270
regulator-compatible = "db8500_sva_pipe";
281
-
regulator-name = "db8500_sva_pipe";
282
271
};
283
272
284
273
// DB8500_REGULATOR_SWITCH_SIAMMDSP
285
274
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
286
275
regulator-compatible = "db8500_sia_mmdsp";
287
-
regulator-name = "db8500_sia_mmdsp";
288
276
};
289
277
290
278
// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
291
279
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
292
-
regulator-name = "db8500-sia-mmdsp-ret";
293
280
};
294
281
295
282
// DB8500_REGULATOR_SWITCH_SIAPIPE
296
283
db8500_sia_pipe_reg: db8500_sia_pipe {
297
284
regulator-compatible = "db8500_sia_pipe";
298
-
regulator-name = "db8500-sia-pipe";
299
285
};
300
286
301
287
// DB8500_REGULATOR_SWITCH_SGA
302
288
db8500_sga_reg: db8500_sga {
303
289
regulator-compatible = "db8500_sga";
304
-
regulator-name = "db8500-sga";
305
290
vin-supply = <&db8500_vape_reg>;
306
291
};
307
292
308
293
// DB8500_REGULATOR_SWITCH_B2R2_MCDE
309
294
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
310
295
regulator-compatible = "db8500_b2r2_mcde";
311
-
regulator-name = "db8500-b2r2-mcde";
312
296
vin-supply = <&db8500_vape_reg>;
313
297
};
314
298
315
299
// DB8500_REGULATOR_SWITCH_ESRAM12
316
300
db8500_esram12_reg: db8500_esram12 {
317
301
regulator-compatible = "db8500_esram12";
318
-
regulator-name = "db8500-esram12";
319
302
};
320
303
321
304
// DB8500_REGULATOR_SWITCH_ESRAM12RET
322
305
db8500_esram12_ret_reg: db8500_esram12_ret {
323
306
regulator-compatible = "db8500_esram12_ret";
324
-
regulator-name = "db8500-esram12-ret";
325
307
};
326
308
327
309
// DB8500_REGULATOR_SWITCH_ESRAM34
328
310
db8500_esram34_reg: db8500_esram34 {
329
311
regulator-compatible = "db8500_esram34";
330
-
regulator-name = "db8500-esram34";
331
312
};
332
313
333
314
// DB8500_REGULATOR_SWITCH_ESRAM34RET
334
315
db8500_esram34_ret_reg: db8500_esram34_ret {
335
316
regulator-compatible = "db8500_esram34_ret";
336
-
regulator-name = "db8500-esram34-ret";
337
317
};
338
318
};
339
319
···
392
412
// supplies to the display/camera
393
413
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
394
414
regulator-compatible = "ab8500_ldo_aux1";
395
-
regulator-name = "V-DISPLAY";
396
415
regulator-min-microvolt = <2500000>;
397
416
regulator-max-microvolt = <2900000>;
398
417
regulator-boot-on;
···
402
423
// supplies to the on-board eMMC
403
424
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
404
425
regulator-compatible = "ab8500_ldo_aux2";
405
-
regulator-name = "V-eMMC1";
406
426
regulator-min-microvolt = <1100000>;
407
427
regulator-max-microvolt = <3300000>;
408
428
};
···
409
431
// supply for VAUX3; SDcard slots
410
432
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
411
433
regulator-compatible = "ab8500_ldo_aux3";
412
-
regulator-name = "V-MMC-SD";
413
434
regulator-min-microvolt = <1100000>;
414
435
regulator-max-microvolt = <3300000>;
415
436
};
···
416
439
// supply for v-intcore12; VINTCORE12 LDO
417
440
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
418
441
regulator-compatible = "ab8500_ldo_initcore";
419
-
regulator-name = "V-INTCORE";
420
442
};
421
443
422
444
// supply for tvout; gpadc; TVOUT LDO
423
445
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
424
446
regulator-compatible = "ab8500_ldo_tvout";
425
-
regulator-name = "V-TVOUT";
426
447
};
427
448
428
449
// supply for ab8500-usb; USB LDO
429
450
ab8500_ldo_usb_reg: ab8500_ldo_usb {
430
451
regulator-compatible = "ab8500_ldo_usb";
431
-
regulator-name = "dummy";
432
452
};
433
453
434
454
// supply for ab8500-vaudio; VAUDIO LDO
435
455
ab8500_ldo_audio_reg: ab8500_ldo_audio {
436
456
regulator-compatible = "ab8500_ldo_audio";
437
-
regulator-name = "V-AUD";
438
457
};
439
458
440
459
// supply for v-anamic1 VAMic1-LDO
441
460
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
442
461
regulator-compatible = "ab8500_ldo_anamic1";
443
-
regulator-name = "V-AMIC1";
444
462
};
445
463
446
464
// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
447
465
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
448
466
regulator-compatible = "ab8500_ldo_amamic2";
449
-
regulator-name = "V-AMIC2";
450
467
};
451
468
452
469
// supply for v-dmic; VDMIC LDO
453
470
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
454
471
regulator-compatible = "ab8500_ldo_dmic";
455
-
regulator-name = "V-DMIC";
456
472
};
457
473
458
474
// supply for U8500 CSI/DSI; VANA LDO
459
475
ab8500_ldo_ana_reg: ab8500_ldo_ana {
460
476
regulator-compatible = "ab8500_ldo_ana";
461
-
regulator-name = "V-CSI/DSI";
462
477
};
463
478
};
464
479
};
···
554
585
status = "disabled";
555
586
};
556
587
557
-
sdi@80126000 {
588
+
sdi0_per1@80126000 {
558
589
compatible = "arm,pl18x", "arm,primecell";
559
590
reg = <0x80126000 0x1000>;
560
591
interrupts = <0 60 0x4>;
561
592
status = "disabled";
562
593
};
563
594
564
-
sdi@80118000 {
595
+
sdi1_per2@80118000 {
565
596
compatible = "arm,pl18x", "arm,primecell";
566
597
reg = <0x80118000 0x1000>;
567
598
interrupts = <0 50 0x4>;
568
599
status = "disabled";
569
600
};
570
601
571
-
sdi@80005000 {
602
+
sdi2_per3@80005000 {
572
603
compatible = "arm,pl18x", "arm,primecell";
573
604
reg = <0x80005000 0x1000>;
574
605
interrupts = <0 41 0x4>;
575
606
status = "disabled";
576
607
};
577
608
578
-
sdi@80119000 {
609
+
sdi3_per2@80119000 {
579
610
compatible = "arm,pl18x", "arm,primecell";
580
611
reg = <0x80119000 0x1000>;
581
612
interrupts = <0 59 0x4>;
582
613
status = "disabled";
583
614
};
584
615
585
-
sdi@80114000 {
616
+
sdi4_per2@80114000 {
586
617
compatible = "arm,pl18x", "arm,primecell";
587
618
reg = <0x80114000 0x1000>;
588
619
interrupts = <0 99 0x4>;
589
620
status = "disabled";
590
621
};
591
622
592
-
sdi@80008000 {
623
+
sdi5_per3@80008000 {
593
624
compatible = "arm,pl18x", "arm,primecell";
594
625
reg = <0x80008000 0x1000>;
595
626
interrupts = <0 100 0x4>;
···
643
674
status = "disabled";
644
675
};
645
676
677
+
vmmci: regulator-gpio {
678
+
compatible = "regulator-gpio";
679
+
680
+
regulator-min-microvolt = <1800000>;
681
+
regulator-max-microvolt = <2600000>;
682
+
regulator-name = "mmci-reg";
683
+
regulator-type = "voltage";
684
+
685
+
states = <1800000 0x1
686
+
2900000 0x0>;
687
+
688
+
status = "disabled";
689
+
};
646
690
};
647
691
};
+10
arch/arm/boot/dts/dove-cubox.dts
+10
arch/arm/boot/dts/dove-cubox.dts
+16
-3
arch/arm/boot/dts/dove.dtsi
+16
-3
arch/arm/boot/dts/dove.dtsi
···
4
4
compatible = "marvell,dove";
5
5
model = "Marvell Armada 88AP510 SoC";
6
6
7
+
aliases {
8
+
gpio0 = &gpio0;
9
+
gpio1 = &gpio1;
10
+
gpio2 = &gpio2;
11
+
};
12
+
7
13
soc@f1000000 {
8
14
compatible = "simple-bus";
9
15
#address-cells = <1>;
···
78
72
#gpio-cells = <2>;
79
73
gpio-controller;
80
74
reg = <0xd0400 0x20>;
81
-
ngpio = <32>;
75
+
ngpios = <32>;
76
+
interrupt-controller;
82
77
interrupts = <12>, <13>, <14>, <60>;
83
78
};
84
79
···
88
81
#gpio-cells = <2>;
89
82
gpio-controller;
90
83
reg = <0xd0420 0x20>;
91
-
ngpio = <32>;
84
+
ngpios = <32>;
85
+
interrupt-controller;
92
86
interrupts = <61>;
93
87
};
94
88
···
98
90
#gpio-cells = <2>;
99
91
gpio-controller;
100
92
reg = <0xe8400 0x0c>;
101
-
ngpio = <8>;
93
+
ngpios = <8>;
94
+
};
95
+
96
+
pinctrl: pinctrl@d0200 {
97
+
compatible = "marvell,dove-pinctrl";
98
+
reg = <0xd0200 0x10>;
102
99
};
103
100
104
101
spi0: spi@10600 {
+12
arch/arm/boot/dts/evk-pro3.dts
+12
arch/arm/boot/dts/evk-pro3.dts
···
22
22
status = "okay";
23
23
};
24
24
25
+
usart0: serial@fffb0000 {
26
+
status = "okay";
27
+
};
28
+
29
+
usart2: serial@fffb8000 {
30
+
status = "okay";
31
+
};
32
+
25
33
usb1: gadget@fffa4000 {
26
34
atmel,vbus-gpio = <&pioC 5 0>;
35
+
status = "okay";
36
+
};
37
+
38
+
watchdog@fffffd40 {
27
39
status = "okay";
28
40
};
29
41
};
+46
-8
arch/arm/boot/dts/exynos4.dtsi
+46
-8
arch/arm/boot/dts/exynos4.dtsi
···
28
28
spi0 = &spi_0;
29
29
spi1 = &spi_1;
30
30
spi2 = &spi_2;
31
+
i2c0 = &i2c_0;
32
+
i2c1 = &i2c_1;
33
+
i2c2 = &i2c_2;
34
+
i2c3 = &i2c_3;
35
+
i2c4 = &i2c_4;
36
+
i2c5 = &i2c_5;
37
+
i2c6 = &i2c_6;
38
+
i2c7 = &i2c_7;
39
+
};
40
+
41
+
pd_mfc: mfc-power-domain@10023C40 {
42
+
compatible = "samsung,exynos4210-pd";
43
+
reg = <0x10023C40 0x20>;
44
+
};
45
+
46
+
pd_g3d: g3d-power-domain@10023C60 {
47
+
compatible = "samsung,exynos4210-pd";
48
+
reg = <0x10023C60 0x20>;
49
+
};
50
+
51
+
pd_lcd0: lcd0-power-domain@10023C80 {
52
+
compatible = "samsung,exynos4210-pd";
53
+
reg = <0x10023C80 0x20>;
54
+
};
55
+
56
+
pd_tv: tv-power-domain@10023C20 {
57
+
compatible = "samsung,exynos4210-pd";
58
+
reg = <0x10023C20 0x20>;
59
+
};
60
+
61
+
pd_cam: cam-power-domain@10023C00 {
62
+
compatible = "samsung,exynos4210-pd";
63
+
reg = <0x10023C00 0x20>;
64
+
};
65
+
66
+
pd_gps: gps-power-domain@10023CE0 {
67
+
compatible = "samsung,exynos4210-pd";
68
+
reg = <0x10023CE0 0x20>;
31
69
};
32
70
33
71
gic:interrupt-controller@10490000 {
···
159
121
status = "disabled";
160
122
};
161
123
162
-
i2c@13860000 {
124
+
i2c_0: i2c@13860000 {
163
125
#address-cells = <1>;
164
126
#size-cells = <0>;
165
127
compatible = "samsung,s3c2440-i2c";
···
168
130
status = "disabled";
169
131
};
170
132
171
-
i2c@13870000 {
133
+
i2c_1: i2c@13870000 {
172
134
#address-cells = <1>;
173
135
#size-cells = <0>;
174
136
compatible = "samsung,s3c2440-i2c";
···
177
139
status = "disabled";
178
140
};
179
141
180
-
i2c@13880000 {
142
+
i2c_2: i2c@13880000 {
181
143
#address-cells = <1>;
182
144
#size-cells = <0>;
183
145
compatible = "samsung,s3c2440-i2c";
···
186
148
status = "disabled";
187
149
};
188
150
189
-
i2c@13890000 {
151
+
i2c_3: i2c@13890000 {
190
152
#address-cells = <1>;
191
153
#size-cells = <0>;
192
154
compatible = "samsung,s3c2440-i2c";
···
195
157
status = "disabled";
196
158
};
197
159
198
-
i2c@138A0000 {
160
+
i2c_4: i2c@138A0000 {
199
161
#address-cells = <1>;
200
162
#size-cells = <0>;
201
163
compatible = "samsung,s3c2440-i2c";
···
204
166
status = "disabled";
205
167
};
206
168
207
-
i2c@138B0000 {
169
+
i2c_5: i2c@138B0000 {
208
170
#address-cells = <1>;
209
171
#size-cells = <0>;
210
172
compatible = "samsung,s3c2440-i2c";
···
213
175
status = "disabled";
214
176
};
215
177
216
-
i2c@138C0000 {
178
+
i2c_6: i2c@138C0000 {
217
179
#address-cells = <1>;
218
180
#size-cells = <0>;
219
181
compatible = "samsung,s3c2440-i2c";
···
222
184
status = "disabled";
223
185
};
224
186
225
-
i2c@138D0000 {
187
+
i2c_7: i2c@138D0000 {
226
188
#address-cells = <1>;
227
189
#size-cells = <0>;
228
190
compatible = "samsung,s3c2440-i2c";
+43
-27
arch/arm/boot/dts/exynos4210-origen.dts
+43
-27
arch/arm/boot/dts/exynos4210-origen.dts
···
22
22
compatible = "insignal,origen", "samsung,exynos4210";
23
23
24
24
memory {
25
-
reg = <0x40000000 0x40000000>;
25
+
reg = <0x40000000 0x10000000
26
+
0x50000000 0x10000000
27
+
0x60000000 0x10000000
28
+
0x70000000 0x10000000>;
26
29
};
27
30
28
31
chosen {
29
32
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30
33
};
31
34
35
+
mmc_reg: voltage-regulator {
36
+
compatible = "regulator-fixed";
37
+
regulator-name = "VMEM_VDD_2.8V";
38
+
regulator-min-microvolt = <2800000>;
39
+
regulator-max-microvolt = <2800000>;
40
+
gpio = <&gpx1 1 0>;
41
+
enable-active-high;
42
+
};
43
+
32
44
sdhci@12530000 {
33
-
samsung,sdhci-bus-width = <4>;
34
-
linux,mmc_cap_4_bit_data;
35
-
samsung,sdhci-cd-internal;
36
-
gpio-cd = <&gpk2 2 2 3 3>;
37
-
gpios = <&gpk2 0 2 0 3>,
38
-
<&gpk2 1 2 0 3>,
39
-
<&gpk2 3 2 3 3>,
40
-
<&gpk2 4 2 3 3>,
41
-
<&gpk2 5 2 3 3>,
42
-
<&gpk2 6 2 3 3>;
45
+
bus-width = <4>;
46
+
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
47
+
pinctrl-names = "default";
48
+
vmmc-supply = <&mmc_reg>;
43
49
status = "okay";
44
50
};
45
51
46
52
sdhci@12510000 {
47
-
samsung,sdhci-bus-width = <4>;
48
-
linux,mmc_cap_4_bit_data;
49
-
samsung,sdhci-cd-internal;
50
-
gpio-cd = <&gpk0 2 2 3 3>;
51
-
gpios = <&gpk0 0 2 0 3>,
52
-
<&gpk0 1 2 0 3>,
53
-
<&gpk0 3 2 3 3>,
54
-
<&gpk0 4 2 3 3>,
55
-
<&gpk0 5 2 3 3>,
56
-
<&gpk0 6 2 3 3>;
53
+
bus-width = <4>;
54
+
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
55
+
pinctrl-names = "default";
56
+
vmmc-supply = <&mmc_reg>;
57
+
status = "okay";
58
+
};
59
+
60
+
serial@13800000 {
61
+
status = "okay";
62
+
};
63
+
64
+
serial@13810000 {
65
+
status = "okay";
66
+
};
67
+
68
+
serial@13820000 {
69
+
status = "okay";
70
+
};
71
+
72
+
serial@13830000 {
57
73
status = "okay";
58
74
};
59
75
···
80
64
81
65
up {
82
66
label = "Up";
83
-
gpios = <&gpx2 0 0 0x10000 2>;
67
+
gpios = <&gpx2 0 1>;
84
68
linux,code = <103>;
85
69
gpio-key,wakeup;
86
70
};
87
71
88
72
down {
89
73
label = "Down";
90
-
gpios = <&gpx2 1 0 0x10000 2>;
74
+
gpios = <&gpx2 1 1>;
91
75
linux,code = <108>;
92
76
gpio-key,wakeup;
93
77
};
94
78
95
79
back {
96
80
label = "Back";
97
-
gpios = <&gpx1 7 0 0x10000 2>;
81
+
gpios = <&gpx1 7 1>;
98
82
linux,code = <158>;
99
83
gpio-key,wakeup;
100
84
};
101
85
102
86
home {
103
87
label = "Home";
104
-
gpios = <&gpx1 6 0 0x10000 2>;
88
+
gpios = <&gpx1 6 1>;
105
89
linux,code = <102>;
106
90
gpio-key,wakeup;
107
91
};
108
92
109
93
menu {
110
94
label = "Menu";
111
-
gpios = <&gpx1 5 0 0x10000 2>;
95
+
gpios = <&gpx1 5 1>;
112
96
linux,code = <139>;
113
97
gpio-key,wakeup;
114
98
};
···
117
101
leds {
118
102
compatible = "gpio-leds";
119
103
status {
120
-
gpios = <&gpx1 3 0 0x10000 2>;
104
+
gpios = <&gpx1 3 1>;
121
105
linux,default-trigger = "heartbeat";
122
106
};
123
107
};
+28
-28
arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+28
-28
arch/arm/boot/dts/exynos4210-pinctrl.dtsi
···
482
482
samsung,pins = "gpk0-0";
483
483
samsung,pin-function = <2>;
484
484
samsung,pin-pud = <0>;
485
-
samsung,pin-drv = <0>;
485
+
samsung,pin-drv = <3>;
486
486
};
487
487
488
488
sd0_cmd: sd0-cmd {
489
489
samsung,pins = "gpk0-1";
490
490
samsung,pin-function = <2>;
491
491
samsung,pin-pud = <0>;
492
-
samsung,pin-drv = <0>;
492
+
samsung,pin-drv = <3>;
493
493
};
494
494
495
495
sd0_cd: sd0-cd {
496
496
samsung,pins = "gpk0-2";
497
497
samsung,pin-function = <2>;
498
498
samsung,pin-pud = <3>;
499
-
samsung,pin-drv = <0>;
499
+
samsung,pin-drv = <3>;
500
500
};
501
501
502
502
sd0_bus1: sd0-bus-width1 {
503
503
samsung,pins = "gpk0-3";
504
504
samsung,pin-function = <2>;
505
505
samsung,pin-pud = <3>;
506
-
samsung,pin-drv = <0>;
506
+
samsung,pin-drv = <3>;
507
507
};
508
508
509
509
sd0_bus4: sd0-bus-width4 {
510
510
samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
511
511
samsung,pin-function = <2>;
512
512
samsung,pin-pud = <3>;
513
-
samsung,pin-drv = <0>;
513
+
samsung,pin-drv = <3>;
514
514
};
515
515
516
516
sd0_bus8: sd0-bus-width8 {
517
517
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
518
518
samsung,pin-function = <3>;
519
519
samsung,pin-pud = <3>;
520
-
samsung,pin-drv = <0>;
520
+
samsung,pin-drv = <3>;
521
521
};
522
522
523
523
sd4_clk: sd4-clk {
524
524
samsung,pins = "gpk0-0";
525
525
samsung,pin-function = <3>;
526
526
samsung,pin-pud = <0>;
527
-
samsung,pin-drv = <0>;
527
+
samsung,pin-drv = <3>;
528
528
};
529
529
530
530
sd4_cmd: sd4-cmd {
531
531
samsung,pins = "gpk0-1";
532
532
samsung,pin-function = <3>;
533
533
samsung,pin-pud = <0>;
534
-
samsung,pin-drv = <0>;
534
+
samsung,pin-drv = <3>;
535
535
};
536
536
537
537
sd4_cd: sd4-cd {
538
538
samsung,pins = "gpk0-2";
539
539
samsung,pin-function = <3>;
540
540
samsung,pin-pud = <3>;
541
-
samsung,pin-drv = <0>;
541
+
samsung,pin-drv = <3>;
542
542
};
543
543
544
544
sd4_bus1: sd4-bus-width1 {
545
545
samsung,pins = "gpk0-3";
546
546
samsung,pin-function = <3>;
547
547
samsung,pin-pud = <3>;
548
-
samsung,pin-drv = <0>;
548
+
samsung,pin-drv = <3>;
549
549
};
550
550
551
551
sd4_bus4: sd4-bus-width4 {
552
552
samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
553
553
samsung,pin-function = <3>;
554
554
samsung,pin-pud = <3>;
555
-
samsung,pin-drv = <0>;
555
+
samsung,pin-drv = <3>;
556
556
};
557
557
558
558
sd4_bus8: sd4-bus-width8 {
559
559
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
560
560
samsung,pin-function = <3>;
561
561
samsung,pin-pud = <4>;
562
-
samsung,pin-drv = <0>;
562
+
samsung,pin-drv = <3>;
563
563
};
564
564
565
565
sd1_clk: sd1-clk {
566
566
samsung,pins = "gpk1-0";
567
567
samsung,pin-function = <2>;
568
568
samsung,pin-pud = <0>;
569
-
samsung,pin-drv = <0>;
569
+
samsung,pin-drv = <3>;
570
570
};
571
571
572
572
sd1_cmd: sd1-cmd {
573
573
samsung,pins = "gpk1-1";
574
574
samsung,pin-function = <2>;
575
575
samsung,pin-pud = <0>;
576
-
samsung,pin-drv = <0>;
576
+
samsung,pin-drv = <3>;
577
577
};
578
578
579
579
sd1_cd: sd1-cd {
580
580
samsung,pins = "gpk1-2";
581
581
samsung,pin-function = <2>;
582
582
samsung,pin-pud = <3>;
583
-
samsung,pin-drv = <0>;
583
+
samsung,pin-drv = <3>;
584
584
};
585
585
586
586
sd1_bus1: sd1-bus-width1 {
587
587
samsung,pins = "gpk1-3";
588
588
samsung,pin-function = <2>;
589
589
samsung,pin-pud = <3>;
590
-
samsung,pin-drv = <0>;
590
+
samsung,pin-drv = <3>;
591
591
};
592
592
593
593
sd1_bus4: sd1-bus-width4 {
594
594
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
595
595
samsung,pin-function = <2>;
596
596
samsung,pin-pud = <3>;
597
-
samsung,pin-drv = <0>;
597
+
samsung,pin-drv = <3>;
598
598
};
599
599
600
600
sd2_clk: sd2-clk {
601
601
samsung,pins = "gpk2-0";
602
602
samsung,pin-function = <2>;
603
603
samsung,pin-pud = <0>;
604
-
samsung,pin-drv = <0>;
604
+
samsung,pin-drv = <3>;
605
605
};
606
606
607
607
sd2_cmd: sd2-cmd {
608
608
samsung,pins = "gpk2-1";
609
609
samsung,pin-function = <2>;
610
610
samsung,pin-pud = <0>;
611
-
samsung,pin-drv = <0>;
611
+
samsung,pin-drv = <3>;
612
612
};
613
613
614
614
sd2_cd: sd2-cd {
615
615
samsung,pins = "gpk2-2";
616
616
samsung,pin-function = <2>;
617
617
samsung,pin-pud = <3>;
618
-
samsung,pin-drv = <0>;
618
+
samsung,pin-drv = <3>;
619
619
};
620
620
621
621
sd2_bus1: sd2-bus-width1 {
622
622
samsung,pins = "gpk2-3";
623
623
samsung,pin-function = <2>;
624
624
samsung,pin-pud = <3>;
625
-
samsung,pin-drv = <0>;
625
+
samsung,pin-drv = <3>;
626
626
};
627
627
628
628
sd2_bus4: sd2-bus-width4 {
629
629
samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
630
630
samsung,pin-function = <2>;
631
631
samsung,pin-pud = <3>;
632
-
samsung,pin-drv = <0>;
632
+
samsung,pin-drv = <3>;
633
633
};
634
634
635
635
sd2_bus8: sd2-bus-width8 {
636
636
samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
637
637
samsung,pin-function = <3>;
638
638
samsung,pin-pud = <3>;
639
-
samsung,pin-drv = <0>;
639
+
samsung,pin-drv = <3>;
640
640
};
641
641
642
642
sd3_clk: sd3-clk {
643
643
samsung,pins = "gpk3-0";
644
644
samsung,pin-function = <2>;
645
645
samsung,pin-pud = <0>;
646
-
samsung,pin-drv = <0>;
646
+
samsung,pin-drv = <3>;
647
647
};
648
648
649
649
sd3_cmd: sd3-cmd {
650
650
samsung,pins = "gpk3-1";
651
651
samsung,pin-function = <2>;
652
652
samsung,pin-pud = <0>;
653
-
samsung,pin-drv = <0>;
653
+
samsung,pin-drv = <3>;
654
654
};
655
655
656
656
sd3_cd: sd3-cd {
657
657
samsung,pins = "gpk3-2";
658
658
samsung,pin-function = <2>;
659
659
samsung,pin-pud = <3>;
660
-
samsung,pin-drv = <0>;
660
+
samsung,pin-drv = <3>;
661
661
};
662
662
663
663
sd3_bus1: sd3-bus-width1 {
664
664
samsung,pins = "gpk3-3";
665
665
samsung,pin-function = <2>;
666
666
samsung,pin-pud = <3>;
667
-
samsung,pin-drv = <0>;
667
+
samsung,pin-drv = <3>;
668
668
};
669
669
670
670
sd3_bus4: sd3-bus-width4 {
671
671
samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
672
672
samsung,pin-function = <2>;
673
673
samsung,pin-pud = <3>;
674
-
samsung,pin-drv = <0>;
674
+
samsung,pin-drv = <3>;
675
675
};
676
676
677
677
eint0: ext-int0 {
+16
arch/arm/boot/dts/exynos4210-smdkv310.dts
+16
arch/arm/boot/dts/exynos4210-smdkv310.dts
···
43
43
status = "okay";
44
44
};
45
45
46
+
serial@13800000 {
47
+
status = "okay";
48
+
};
49
+
50
+
serial@13810000 {
51
+
status = "okay";
52
+
};
53
+
54
+
serial@13820000 {
55
+
status = "okay";
56
+
};
57
+
58
+
serial@13830000 {
59
+
status = "okay";
60
+
};
61
+
46
62
keypad@100A0000 {
47
63
samsung,keypad-num-rows = <2>;
48
64
samsung,keypad-num-columns = <8>;
+70
-17
arch/arm/boot/dts/exynos4210-trats.dts
+70
-17
arch/arm/boot/dts/exynos4210-trats.dts
···
35
35
regulator-name = "VMEM_VDD_2.8V";
36
36
regulator-min-microvolt = <2800000>;
37
37
regulator-max-microvolt = <2800000>;
38
-
gpio = <&gpk0 2 1 0 0>;
38
+
gpio = <&gpk0 2 0>;
39
39
enable-active-high;
40
40
};
41
41
42
42
sdhci_emmc: sdhci@12510000 {
43
43
bus-width = <8>;
44
44
non-removable;
45
-
broken-voltage;
46
-
gpios = <&gpk0 0 2 0 3>,
47
-
<&gpk0 1 2 0 3>,
48
-
<&gpk0 3 2 2 3>,
49
-
<&gpk0 4 2 2 3>,
50
-
<&gpk0 5 2 2 3>,
51
-
<&gpk0 6 2 2 3>,
52
-
<&gpk1 3 3 3 3>,
53
-
<&gpk1 4 3 3 3>,
54
-
<&gpk1 5 3 3 3>,
55
-
<&gpk1 6 3 3 3>;
45
+
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
46
+
pinctrl-names = "default";
56
47
vmmc-supply = <&vemmc_reg>;
57
48
status = "okay";
58
49
};
···
64
73
status = "okay";
65
74
};
66
75
76
+
gpio-keys {
77
+
compatible = "gpio-keys";
78
+
79
+
vol-down-key {
80
+
gpios = <&gpx2 1 1>;
81
+
linux,code = <114>;
82
+
label = "volume down";
83
+
debounce-interval = <10>;
84
+
};
85
+
86
+
vol-up-key {
87
+
gpios = <&gpx2 0 1>;
88
+
linux,code = <115>;
89
+
label = "volume up";
90
+
debounce-interval = <10>;
91
+
};
92
+
93
+
power-key {
94
+
gpios = <&gpx2 7 1>;
95
+
linux,code = <116>;
96
+
label = "power";
97
+
debounce-interval = <10>;
98
+
gpio-key,wakeup;
99
+
};
100
+
101
+
ok-key {
102
+
gpios = <&gpx3 5 1>;
103
+
linux,code = <352>;
104
+
label = "ok";
105
+
debounce-interval = <10>;
106
+
};
107
+
};
108
+
109
+
tsp_reg: voltage-regulator {
110
+
compatible = "regulator-fixed";
111
+
regulator-name = "TSP_FIXED_VOLTAGES";
112
+
regulator-min-microvolt = <2800000>;
113
+
regulator-max-microvolt = <2800000>;
114
+
gpio = <&gpl0 3 0>;
115
+
enable-active-high;
116
+
};
117
+
118
+
i2c@13890000 {
119
+
samsung,i2c-sda-delay = <100>;
120
+
samsung,i2c-slave-addr = <0x10>;
121
+
samsung,i2c-max-bus-freq = <400000>;
122
+
pinctrl-0 = <&i2c3_bus>;
123
+
pinctrl-names = "default";
124
+
status = "okay";
125
+
126
+
mms114-touchscreen@48 {
127
+
compatible = "melfas,mms114";
128
+
reg = <0x48>;
129
+
interrupt-parent = <&gpx0>;
130
+
interrupts = <4 2>;
131
+
x-size = <720>;
132
+
y-size = <1280>;
133
+
avdd-supply = <&tsp_reg>;
134
+
vdd-supply = <&tsp_reg>;
135
+
};
136
+
};
137
+
67
138
i2c@138B0000 {
68
139
samsung,i2c-sda-delay = <100>;
69
140
samsung,i2c-slave-addr = <0x10>;
70
141
samsung,i2c-max-bus-freq = <100000>;
71
-
gpios = <&gpb 6 3 3 0>,
72
-
<&gpb 7 3 3 0>;
142
+
pinctrl-0 = <&i2c5_bus>;
143
+
pinctrl-names = "default";
73
144
status = "okay";
74
145
75
146
max8997_pmic@66 {
···
146
93
max8997,pmic-ignore-gpiodvs-side-effect;
147
94
max8997,pmic-buck125-default-dvs-idx = <0>;
148
95
149
-
max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
150
-
<&gpx0 6 1 0 0>,
151
-
<&gpl0 0 1 0 0>;
96
+
max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>,
97
+
<&gpx0 6 0>,
98
+
<&gpl0 0 0>;
152
99
153
100
max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
154
101
<1250000>, <1200000>,
+12
arch/arm/boot/dts/exynos4210.dtsi
+12
arch/arm/boot/dts/exynos4210.dtsi
···
31
31
pinctrl2 = &pinctrl_2;
32
32
};
33
33
34
+
pd_lcd1: lcd1-power-domain@10023CA0 {
35
+
compatible = "samsung,exynos4210-pd";
36
+
reg = <0x10023CA0 0x20>;
37
+
};
38
+
34
39
gic:interrupt-controller@10490000 {
35
40
cpu-offset = <0x8000>;
36
41
};
···
68
63
pinctrl_2: pinctrl@03860000 {
69
64
compatible = "samsung,pinctrl-exynos4210";
70
65
reg = <0x03860000 0x1000>;
66
+
};
67
+
68
+
tmu@100C0000 {
69
+
compatible = "samsung,exynos4210-tmu";
70
+
interrupt-parent = <&combiner>;
71
+
reg = <0x100C0000 0x100>;
72
+
interrupts = <2 4>;
71
73
};
72
74
};
+28
arch/arm/boot/dts/exynos4212.dtsi
+28
arch/arm/boot/dts/exynos4212.dtsi
···
1
+
/*
2
+
* Samsung's Exynos4212 SoC device tree source
3
+
*
4
+
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
5
+
* http://www.samsung.com
6
+
*
7
+
* Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
8
+
* based board files can include this file and provide values for board specfic
9
+
* bindings.
10
+
*
11
+
* Note: This file does not include device nodes for all the controllers in
12
+
* Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
13
+
* nodes can be added to this file.
14
+
*
15
+
* This program is free software; you can redistribute it and/or modify
16
+
* it under the terms of the GNU General Public License version 2 as
17
+
* published by the Free Software Foundation.
18
+
*/
19
+
20
+
/include/ "exynos4x12.dtsi"
21
+
22
+
/ {
23
+
compatible = "samsung,exynos4212";
24
+
25
+
gic:interrupt-controller@10490000 {
26
+
cpu-offset = <0x8000>;
27
+
};
28
+
};
+45
arch/arm/boot/dts/exynos4412-smdk4412.dts
+45
arch/arm/boot/dts/exynos4412-smdk4412.dts
···
1
+
/*
2
+
* Samsung's Exynos4412 based SMDK board device tree source
3
+
*
4
+
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5
+
* http://www.samsung.com
6
+
*
7
+
* Device tree source file for Samsung's SMDK4412 board which is based on
8
+
* Samsung's Exynos4412 SoC.
9
+
*
10
+
* This program is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*/
14
+
15
+
/dts-v1/;
16
+
/include/ "exynos4412.dtsi"
17
+
18
+
/ {
19
+
model = "Samsung SMDK evaluation board based on Exynos4412";
20
+
compatible = "samsung,smdk4412", "samsung,exynos4412";
21
+
22
+
memory {
23
+
reg = <0x40000000 0x40000000>;
24
+
};
25
+
26
+
chosen {
27
+
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28
+
};
29
+
30
+
serial@13800000 {
31
+
status = "okay";
32
+
};
33
+
34
+
serial@13810000 {
35
+
status = "okay";
36
+
};
37
+
38
+
serial@13820000 {
39
+
status = "okay";
40
+
};
41
+
42
+
serial@13830000 {
43
+
status = "okay";
44
+
};
45
+
};
+28
arch/arm/boot/dts/exynos4412.dtsi
+28
arch/arm/boot/dts/exynos4412.dtsi
···
1
+
/*
2
+
* Samsung's Exynos4412 SoC device tree source
3
+
*
4
+
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
5
+
* http://www.samsung.com
6
+
*
7
+
* Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8
+
* based board files can include this file and provide values for board specfic
9
+
* bindings.
10
+
*
11
+
* Note: This file does not include device nodes for all the controllers in
12
+
* Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13
+
* nodes can be added to this file.
14
+
*
15
+
* This program is free software; you can redistribute it and/or modify
16
+
* it under the terms of the GNU General Public License version 2 as
17
+
* published by the Free Software Foundation.
18
+
*/
19
+
20
+
/include/ "exynos4x12.dtsi"
21
+
22
+
/ {
23
+
compatible = "samsung,exynos4412";
24
+
25
+
gic:interrupt-controller@10490000 {
26
+
cpu-offset = <0x4000>;
27
+
};
28
+
};
+965
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+965
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
···
1
+
/*
2
+
* Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
3
+
*
4
+
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
5
+
* http://www.samsung.com
6
+
*
7
+
* Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
8
+
* tree nodes are listed in this file.
9
+
*
10
+
* This program is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*/
14
+
15
+
/ {
16
+
pinctrl@11400000 {
17
+
gpa0: gpa0 {
18
+
gpio-controller;
19
+
#gpio-cells = <2>;
20
+
21
+
interrupt-controller;
22
+
#interrupt-cells = <2>;
23
+
};
24
+
25
+
gpa1: gpa1 {
26
+
gpio-controller;
27
+
#gpio-cells = <2>;
28
+
29
+
interrupt-controller;
30
+
#interrupt-cells = <2>;
31
+
};
32
+
33
+
gpb: gpb {
34
+
gpio-controller;
35
+
#gpio-cells = <2>;
36
+
37
+
interrupt-controller;
38
+
#interrupt-cells = <2>;
39
+
};
40
+
41
+
gpc0: gpc0 {
42
+
gpio-controller;
43
+
#gpio-cells = <2>;
44
+
45
+
interrupt-controller;
46
+
#interrupt-cells = <2>;
47
+
};
48
+
49
+
gpc1: gpc1 {
50
+
gpio-controller;
51
+
#gpio-cells = <2>;
52
+
53
+
interrupt-controller;
54
+
#interrupt-cells = <2>;
55
+
};
56
+
57
+
gpd0: gpd0 {
58
+
gpio-controller;
59
+
#gpio-cells = <2>;
60
+
61
+
interrupt-controller;
62
+
#interrupt-cells = <2>;
63
+
};
64
+
65
+
gpd1: gpd1 {
66
+
gpio-controller;
67
+
#gpio-cells = <2>;
68
+
69
+
interrupt-controller;
70
+
#interrupt-cells = <2>;
71
+
};
72
+
73
+
gpf0: gpf0 {
74
+
gpio-controller;
75
+
#gpio-cells = <2>;
76
+
77
+
interrupt-controller;
78
+
#interrupt-cells = <2>;
79
+
};
80
+
81
+
gpf1: gpf1 {
82
+
gpio-controller;
83
+
#gpio-cells = <2>;
84
+
85
+
interrupt-controller;
86
+
#interrupt-cells = <2>;
87
+
};
88
+
89
+
gpf2: gpf2 {
90
+
gpio-controller;
91
+
#gpio-cells = <2>;
92
+
93
+
interrupt-controller;
94
+
#interrupt-cells = <2>;
95
+
};
96
+
97
+
gpf3: gpf3 {
98
+
gpio-controller;
99
+
#gpio-cells = <2>;
100
+
101
+
interrupt-controller;
102
+
#interrupt-cells = <2>;
103
+
};
104
+
105
+
gpj0: gpj0 {
106
+
gpio-controller;
107
+
#gpio-cells = <2>;
108
+
109
+
interrupt-controller;
110
+
#interrupt-cells = <2>;
111
+
};
112
+
113
+
gpj1: gpj1 {
114
+
gpio-controller;
115
+
#gpio-cells = <2>;
116
+
117
+
interrupt-controller;
118
+
#interrupt-cells = <2>;
119
+
};
120
+
121
+
uart0_data: uart0-data {
122
+
samsung,pins = "gpa0-0", "gpa0-1";
123
+
samsung,pin-function = <0x2>;
124
+
samsung,pin-pud = <0>;
125
+
samsung,pin-drv = <0>;
126
+
};
127
+
128
+
uart0_fctl: uart0-fctl {
129
+
samsung,pins = "gpa0-2", "gpa0-3";
130
+
samsung,pin-function = <2>;
131
+
samsung,pin-pud = <0>;
132
+
samsung,pin-drv = <0>;
133
+
};
134
+
135
+
uart1_data: uart1-data {
136
+
samsung,pins = "gpa0-4", "gpa0-5";
137
+
samsung,pin-function = <2>;
138
+
samsung,pin-pud = <0>;
139
+
samsung,pin-drv = <0>;
140
+
};
141
+
142
+
uart1_fctl: uart1-fctl {
143
+
samsung,pins = "gpa0-6", "gpa0-7";
144
+
samsung,pin-function = <2>;
145
+
samsung,pin-pud = <0>;
146
+
samsung,pin-drv = <0>;
147
+
};
148
+
149
+
i2c2_bus: i2c2-bus {
150
+
samsung,pins = "gpa0-6", "gpa0-7";
151
+
samsung,pin-function = <3>;
152
+
samsung,pin-pud = <3>;
153
+
samsung,pin-drv = <0>;
154
+
};
155
+
156
+
uart2_data: uart2-data {
157
+
samsung,pins = "gpa1-0", "gpa1-1";
158
+
samsung,pin-function = <2>;
159
+
samsung,pin-pud = <0>;
160
+
samsung,pin-drv = <0>;
161
+
};
162
+
163
+
uart2_fctl: uart2-fctl {
164
+
samsung,pins = "gpa1-2", "gpa1-3";
165
+
samsung,pin-function = <2>;
166
+
samsung,pin-pud = <0>;
167
+
samsung,pin-drv = <0>;
168
+
};
169
+
170
+
uart_audio_a: uart-audio-a {
171
+
samsung,pins = "gpa1-0", "gpa1-1";
172
+
samsung,pin-function = <4>;
173
+
samsung,pin-pud = <0>;
174
+
samsung,pin-drv = <0>;
175
+
};
176
+
177
+
i2c3_bus: i2c3-bus {
178
+
samsung,pins = "gpa1-2", "gpa1-3";
179
+
samsung,pin-function = <3>;
180
+
samsung,pin-pud = <3>;
181
+
samsung,pin-drv = <0>;
182
+
};
183
+
184
+
uart3_data: uart3-data {
185
+
samsung,pins = "gpa1-4", "gpa1-5";
186
+
samsung,pin-function = <2>;
187
+
samsung,pin-pud = <0>;
188
+
samsung,pin-drv = <0>;
189
+
};
190
+
191
+
uart_audio_b: uart-audio-b {
192
+
samsung,pins = "gpa1-4", "gpa1-5";
193
+
samsung,pin-function = <4>;
194
+
samsung,pin-pud = <0>;
195
+
samsung,pin-drv = <0>;
196
+
};
197
+
198
+
spi0_bus: spi0-bus {
199
+
samsung,pins = "gpb-0", "gpb-2", "gpb-3";
200
+
samsung,pin-function = <2>;
201
+
samsung,pin-pud = <3>;
202
+
samsung,pin-drv = <0>;
203
+
};
204
+
205
+
i2c4_bus: i2c4-bus {
206
+
samsung,pins = "gpb-0", "gpb-1";
207
+
samsung,pin-function = <3>;
208
+
samsung,pin-pud = <3>;
209
+
samsung,pin-drv = <0>;
210
+
};
211
+
212
+
spi1_bus: spi1-bus {
213
+
samsung,pins = "gpb-4", "gpb-6", "gpb-7";
214
+
samsung,pin-function = <2>;
215
+
samsung,pin-pud = <3>;
216
+
samsung,pin-drv = <0>;
217
+
};
218
+
219
+
i2c5_bus: i2c5-bus {
220
+
samsung,pins = "gpb-2", "gpb-3";
221
+
samsung,pin-function = <3>;
222
+
samsung,pin-pud = <3>;
223
+
samsung,pin-drv = <0>;
224
+
};
225
+
226
+
i2s1_bus: i2s1-bus {
227
+
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
228
+
"gpc0-4";
229
+
samsung,pin-function = <2>;
230
+
samsung,pin-pud = <0>;
231
+
samsung,pin-drv = <0>;
232
+
};
233
+
234
+
pcm1_bus: pcm1-bus {
235
+
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
236
+
"gpc0-4";
237
+
samsung,pin-function = <3>;
238
+
samsung,pin-pud = <0>;
239
+
samsung,pin-drv = <0>;
240
+
};
241
+
242
+
ac97_bus: ac97-bus {
243
+
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
244
+
"gpc0-4";
245
+
samsung,pin-function = <4>;
246
+
samsung,pin-pud = <0>;
247
+
samsung,pin-drv = <0>;
248
+
};
249
+
250
+
i2s2_bus: i2s2-bus {
251
+
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
252
+
"gpc1-4";
253
+
samsung,pin-function = <2>;
254
+
samsung,pin-pud = <0>;
255
+
samsung,pin-drv = <0>;
256
+
};
257
+
258
+
pcm2_bus: pcm2-bus {
259
+
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
260
+
"gpc1-4";
261
+
samsung,pin-function = <3>;
262
+
samsung,pin-pud = <0>;
263
+
samsung,pin-drv = <0>;
264
+
};
265
+
266
+
spdif_bus: spdif-bus {
267
+
samsung,pins = "gpc1-0", "gpc1-1";
268
+
samsung,pin-function = <4>;
269
+
samsung,pin-pud = <0>;
270
+
samsung,pin-drv = <0>;
271
+
};
272
+
273
+
i2c6_bus: i2c6-bus {
274
+
samsung,pins = "gpc1-3", "gpc1-4";
275
+
samsung,pin-function = <4>;
276
+
samsung,pin-pud = <3>;
277
+
samsung,pin-drv = <0>;
278
+
};
279
+
280
+
spi2_bus: spi2-bus {
281
+
samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
282
+
samsung,pin-function = <5>;
283
+
samsung,pin-pud = <3>;
284
+
samsung,pin-drv = <0>;
285
+
};
286
+
287
+
pwm0_out: pwm0-out {
288
+
samsung,pins = "gpd0-0";
289
+
samsung,pin-function = <2>;
290
+
samsung,pin-pud = <0>;
291
+
samsung,pin-drv = <0>;
292
+
};
293
+
294
+
pwm1_out: pwm1-out {
295
+
samsung,pins = "gpd0-1";
296
+
samsung,pin-function = <2>;
297
+
samsung,pin-pud = <0>;
298
+
samsung,pin-drv = <0>;
299
+
};
300
+
301
+
lcd_ctrl: lcd-ctrl {
302
+
samsung,pins = "gpd0-0", "gpd0-1";
303
+
samsung,pin-function = <3>;
304
+
samsung,pin-pud = <0>;
305
+
samsung,pin-drv = <0>;
306
+
};
307
+
308
+
i2c7_bus: i2c7-bus {
309
+
samsung,pins = "gpd0-2", "gpd0-3";
310
+
samsung,pin-function = <3>;
311
+
samsung,pin-pud = <3>;
312
+
samsung,pin-drv = <0>;
313
+
};
314
+
315
+
pwm2_out: pwm2-out {
316
+
samsung,pins = "gpd0-2";
317
+
samsung,pin-function = <2>;
318
+
samsung,pin-pud = <0>;
319
+
samsung,pin-drv = <0>;
320
+
};
321
+
322
+
pwm3_out: pwm3-out {
323
+
samsung,pins = "gpd0-3";
324
+
samsung,pin-function = <2>;
325
+
samsung,pin-pud = <0>;
326
+
samsung,pin-drv = <0>;
327
+
};
328
+
329
+
i2c0_bus: i2c0-bus {
330
+
samsung,pins = "gpd1-0", "gpd1-1";
331
+
samsung,pin-function = <2>;
332
+
samsung,pin-pud = <3>;
333
+
samsung,pin-drv = <0>;
334
+
};
335
+
336
+
mipi0_clk: mipi0-clk {
337
+
samsung,pins = "gpd1-0", "gpd1-1";
338
+
samsung,pin-function = <3>;
339
+
samsung,pin-pud = <0>;
340
+
samsung,pin-drv = <0>;
341
+
};
342
+
343
+
i2c1_bus: i2c1-bus {
344
+
samsung,pins = "gpd1-2", "gpd1-3";
345
+
samsung,pin-function = <2>;
346
+
samsung,pin-pud = <3>;
347
+
samsung,pin-drv = <0>;
348
+
};
349
+
350
+
mipi1_clk: mipi1-clk {
351
+
samsung,pins = "gpd1-2", "gpd1-3";
352
+
samsung,pin-function = <3>;
353
+
samsung,pin-pud = <0>;
354
+
samsung,pin-drv = <0>;
355
+
};
356
+
357
+
lcd_clk: lcd-clk {
358
+
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
359
+
samsung,pin-function = <2>;
360
+
samsung,pin-pud = <0>;
361
+
samsung,pin-drv = <0>;
362
+
};
363
+
364
+
lcd_data16: lcd-data-width16 {
365
+
samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
366
+
"gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
367
+
"gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
368
+
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
369
+
samsung,pin-function = <2>;
370
+
samsung,pin-pud = <0>;
371
+
samsung,pin-drv = <0>;
372
+
};
373
+
374
+
lcd_data18: lcd-data-width18 {
375
+
samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
376
+
"gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
377
+
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
378
+
"gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
379
+
"gpf3-2", "gpf3-3";
380
+
samsung,pin-function = <2>;
381
+
samsung,pin-pud = <0>;
382
+
samsung,pin-drv = <0>;
383
+
};
384
+
385
+
lcd_data24: lcd-data-width24 {
386
+
samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
387
+
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
388
+
"gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
389
+
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
390
+
"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
391
+
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
392
+
samsung,pin-function = <2>;
393
+
samsung,pin-pud = <0>;
394
+
samsung,pin-drv = <0>;
395
+
};
396
+
397
+
lcd_ldi: lcd-ldi {
398
+
samsung,pins = "gpf3-4";
399
+
samsung,pin-function = <2>;
400
+
samsung,pin-pud = <0>;
401
+
samsung,pin-drv = <0>;
402
+
};
403
+
404
+
cam_port_a: cam-port-a {
405
+
samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
406
+
"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
407
+
"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
408
+
"gpj1-4";
409
+
samsung,pin-function = <2>;
410
+
samsung,pin-pud = <3>;
411
+
samsung,pin-drv = <0>;
412
+
};
413
+
};
414
+
415
+
pinctrl@11000000 {
416
+
gpk0: gpk0 {
417
+
gpio-controller;
418
+
#gpio-cells = <2>;
419
+
420
+
interrupt-controller;
421
+
#interrupt-cells = <2>;
422
+
};
423
+
424
+
gpk1: gpk1 {
425
+
gpio-controller;
426
+
#gpio-cells = <2>;
427
+
428
+
interrupt-controller;
429
+
#interrupt-cells = <2>;
430
+
};
431
+
432
+
gpk2: gpk2 {
433
+
gpio-controller;
434
+
#gpio-cells = <2>;
435
+
436
+
interrupt-controller;
437
+
#interrupt-cells = <2>;
438
+
};
439
+
440
+
gpk3: gpk3 {
441
+
gpio-controller;
442
+
#gpio-cells = <2>;
443
+
444
+
interrupt-controller;
445
+
#interrupt-cells = <2>;
446
+
};
447
+
448
+
gpl0: gpl0 {
449
+
gpio-controller;
450
+
#gpio-cells = <2>;
451
+
452
+
interrupt-controller;
453
+
#interrupt-cells = <2>;
454
+
};
455
+
456
+
gpl1: gpl1 {
457
+
gpio-controller;
458
+
#gpio-cells = <2>;
459
+
460
+
interrupt-controller;
461
+
#interrupt-cells = <2>;
462
+
};
463
+
464
+
gpl2: gpl2 {
465
+
gpio-controller;
466
+
#gpio-cells = <2>;
467
+
468
+
interrupt-controller;
469
+
#interrupt-cells = <2>;
470
+
};
471
+
472
+
gpm0: gpm0 {
473
+
gpio-controller;
474
+
#gpio-cells = <2>;
475
+
476
+
interrupt-controller;
477
+
#interrupt-cells = <2>;
478
+
};
479
+
480
+
gpm1: gpm1 {
481
+
gpio-controller;
482
+
#gpio-cells = <2>;
483
+
484
+
interrupt-controller;
485
+
#interrupt-cells = <2>;
486
+
};
487
+
488
+
gpm2: gpm2 {
489
+
gpio-controller;
490
+
#gpio-cells = <2>;
491
+
492
+
interrupt-controller;
493
+
#interrupt-cells = <2>;
494
+
};
495
+
496
+
gpm3: gpm3 {
497
+
gpio-controller;
498
+
#gpio-cells = <2>;
499
+
500
+
interrupt-controller;
501
+
#interrupt-cells = <2>;
502
+
};
503
+
504
+
gpm4: gpm4 {
505
+
gpio-controller;
506
+
#gpio-cells = <2>;
507
+
508
+
interrupt-controller;
509
+
#interrupt-cells = <2>;
510
+
};
511
+
512
+
gpy0: gpy0 {
513
+
gpio-controller;
514
+
#gpio-cells = <2>;
515
+
};
516
+
517
+
gpy1: gpy1 {
518
+
gpio-controller;
519
+
#gpio-cells = <2>;
520
+
};
521
+
522
+
gpy2: gpy2 {
523
+
gpio-controller;
524
+
#gpio-cells = <2>;
525
+
};
526
+
527
+
gpy3: gpy3 {
528
+
gpio-controller;
529
+
#gpio-cells = <2>;
530
+
};
531
+
532
+
gpy4: gpy4 {
533
+
gpio-controller;
534
+
#gpio-cells = <2>;
535
+
};
536
+
537
+
gpy5: gpy5 {
538
+
gpio-controller;
539
+
#gpio-cells = <2>;
540
+
};
541
+
542
+
gpy6: gpy6 {
543
+
gpio-controller;
544
+
#gpio-cells = <2>;
545
+
};
546
+
547
+
gpx0: gpx0 {
548
+
gpio-controller;
549
+
#gpio-cells = <2>;
550
+
551
+
interrupt-controller;
552
+
interrupt-parent = <&gic>;
553
+
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
554
+
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
555
+
#interrupt-cells = <2>;
556
+
};
557
+
558
+
gpx1: gpx1 {
559
+
gpio-controller;
560
+
#gpio-cells = <2>;
561
+
562
+
interrupt-controller;
563
+
interrupt-parent = <&gic>;
564
+
interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
565
+
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
566
+
#interrupt-cells = <2>;
567
+
};
568
+
569
+
gpx2: gpx2 {
570
+
gpio-controller;
571
+
#gpio-cells = <2>;
572
+
573
+
interrupt-controller;
574
+
#interrupt-cells = <2>;
575
+
};
576
+
577
+
gpx3: gpx3 {
578
+
gpio-controller;
579
+
#gpio-cells = <2>;
580
+
581
+
interrupt-controller;
582
+
#interrupt-cells = <2>;
583
+
};
584
+
585
+
sd0_clk: sd0-clk {
586
+
samsung,pins = "gpk0-0";
587
+
samsung,pin-function = <2>;
588
+
samsung,pin-pud = <0>;
589
+
samsung,pin-drv = <3>;
590
+
};
591
+
592
+
sd0_cmd: sd0-cmd {
593
+
samsung,pins = "gpk0-1";
594
+
samsung,pin-function = <2>;
595
+
samsung,pin-pud = <0>;
596
+
samsung,pin-drv = <3>;
597
+
};
598
+
599
+
sd0_cd: sd0-cd {
600
+
samsung,pins = "gpk0-2";
601
+
samsung,pin-function = <2>;
602
+
samsung,pin-pud = <3>;
603
+
samsung,pin-drv = <3>;
604
+
};
605
+
606
+
sd0_bus1: sd0-bus-width1 {
607
+
samsung,pins = "gpk0-3";
608
+
samsung,pin-function = <2>;
609
+
samsung,pin-pud = <3>;
610
+
samsung,pin-drv = <3>;
611
+
};
612
+
613
+
sd0_bus4: sd0-bus-width4 {
614
+
samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
615
+
samsung,pin-function = <2>;
616
+
samsung,pin-pud = <3>;
617
+
samsung,pin-drv = <3>;
618
+
};
619
+
620
+
sd0_bus8: sd0-bus-width8 {
621
+
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
622
+
samsung,pin-function = <3>;
623
+
samsung,pin-pud = <3>;
624
+
samsung,pin-drv = <3>;
625
+
};
626
+
627
+
sd4_clk: sd4-clk {
628
+
samsung,pins = "gpk0-0";
629
+
samsung,pin-function = <3>;
630
+
samsung,pin-pud = <0>;
631
+
samsung,pin-drv = <3>;
632
+
};
633
+
634
+
sd4_cmd: sd4-cmd {
635
+
samsung,pins = "gpk0-1";
636
+
samsung,pin-function = <3>;
637
+
samsung,pin-pud = <0>;
638
+
samsung,pin-drv = <3>;
639
+
};
640
+
641
+
sd4_cd: sd4-cd {
642
+
samsung,pins = "gpk0-2";
643
+
samsung,pin-function = <3>;
644
+
samsung,pin-pud = <3>;
645
+
samsung,pin-drv = <3>;
646
+
};
647
+
648
+
sd4_bus1: sd4-bus-width1 {
649
+
samsung,pins = "gpk0-3";
650
+
samsung,pin-function = <3>;
651
+
samsung,pin-pud = <3>;
652
+
samsung,pin-drv = <3>;
653
+
};
654
+
655
+
sd4_bus4: sd4-bus-width4 {
656
+
samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
657
+
samsung,pin-function = <3>;
658
+
samsung,pin-pud = <3>;
659
+
samsung,pin-drv = <3>;
660
+
};
661
+
662
+
sd4_bus8: sd4-bus-width8 {
663
+
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
664
+
samsung,pin-function = <3>;
665
+
samsung,pin-pud = <4>;
666
+
samsung,pin-drv = <3>;
667
+
};
668
+
669
+
sd1_clk: sd1-clk {
670
+
samsung,pins = "gpk1-0";
671
+
samsung,pin-function = <2>;
672
+
samsung,pin-pud = <0>;
673
+
samsung,pin-drv = <3>;
674
+
};
675
+
676
+
sd1_cmd: sd1-cmd {
677
+
samsung,pins = "gpk1-1";
678
+
samsung,pin-function = <2>;
679
+
samsung,pin-pud = <0>;
680
+
samsung,pin-drv = <3>;
681
+
};
682
+
683
+
sd1_cd: sd1-cd {
684
+
samsung,pins = "gpk1-2";
685
+
samsung,pin-function = <2>;
686
+
samsung,pin-pud = <3>;
687
+
samsung,pin-drv = <3>;
688
+
};
689
+
690
+
sd1_bus1: sd1-bus-width1 {
691
+
samsung,pins = "gpk1-3";
692
+
samsung,pin-function = <2>;
693
+
samsung,pin-pud = <3>;
694
+
samsung,pin-drv = <3>;
695
+
};
696
+
697
+
sd1_bus4: sd1-bus-width4 {
698
+
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
699
+
samsung,pin-function = <2>;
700
+
samsung,pin-pud = <3>;
701
+
samsung,pin-drv = <3>;
702
+
};
703
+
704
+
sd2_clk: sd2-clk {
705
+
samsung,pins = "gpk2-0";
706
+
samsung,pin-function = <2>;
707
+
samsung,pin-pud = <0>;
708
+
samsung,pin-drv = <3>;
709
+
};
710
+
711
+
sd2_cmd: sd2-cmd {
712
+
samsung,pins = "gpk2-1";
713
+
samsung,pin-function = <2>;
714
+
samsung,pin-pud = <0>;
715
+
samsung,pin-drv = <3>;
716
+
};
717
+
718
+
sd2_cd: sd2-cd {
719
+
samsung,pins = "gpk2-2";
720
+
samsung,pin-function = <2>;
721
+
samsung,pin-pud = <3>;
722
+
samsung,pin-drv = <3>;
723
+
};
724
+
725
+
sd2_bus1: sd2-bus-width1 {
726
+
samsung,pins = "gpk2-3";
727
+
samsung,pin-function = <2>;
728
+
samsung,pin-pud = <3>;
729
+
samsung,pin-drv = <3>;
730
+
};
731
+
732
+
sd2_bus4: sd2-bus-width4 {
733
+
samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
734
+
samsung,pin-function = <2>;
735
+
samsung,pin-pud = <3>;
736
+
samsung,pin-drv = <3>;
737
+
};
738
+
739
+
sd2_bus8: sd2-bus-width8 {
740
+
samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
741
+
samsung,pin-function = <3>;
742
+
samsung,pin-pud = <3>;
743
+
samsung,pin-drv = <3>;
744
+
};
745
+
746
+
sd3_clk: sd3-clk {
747
+
samsung,pins = "gpk3-0";
748
+
samsung,pin-function = <2>;
749
+
samsung,pin-pud = <0>;
750
+
samsung,pin-drv = <3>;
751
+
};
752
+
753
+
sd3_cmd: sd3-cmd {
754
+
samsung,pins = "gpk3-1";
755
+
samsung,pin-function = <2>;
756
+
samsung,pin-pud = <0>;
757
+
samsung,pin-drv = <3>;
758
+
};
759
+
760
+
sd3_cd: sd3-cd {
761
+
samsung,pins = "gpk3-2";
762
+
samsung,pin-function = <2>;
763
+
samsung,pin-pud = <3>;
764
+
samsung,pin-drv = <3>;
765
+
};
766
+
767
+
sd3_bus1: sd3-bus-width1 {
768
+
samsung,pins = "gpk3-3";
769
+
samsung,pin-function = <2>;
770
+
samsung,pin-pud = <3>;
771
+
samsung,pin-drv = <3>;
772
+
};
773
+
774
+
sd3_bus4: sd3-bus-width4 {
775
+
samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
776
+
samsung,pin-function = <2>;
777
+
samsung,pin-pud = <3>;
778
+
samsung,pin-drv = <3>;
779
+
};
780
+
781
+
keypad_col0: keypad-col0 {
782
+
samsung,pins = "gpl2-0";
783
+
samsung,pin-function = <3>;
784
+
samsung,pin-pud = <0>;
785
+
samsung,pin-drv = <0>;
786
+
};
787
+
788
+
keypad_col1: keypad-col1 {
789
+
samsung,pins = "gpl2-1";
790
+
samsung,pin-function = <3>;
791
+
samsung,pin-pud = <0>;
792
+
samsung,pin-drv = <0>;
793
+
};
794
+
795
+
keypad_col2: keypad-col2 {
796
+
samsung,pins = "gpl2-2";
797
+
samsung,pin-function = <3>;
798
+
samsung,pin-pud = <0>;
799
+
samsung,pin-drv = <0>;
800
+
};
801
+
802
+
keypad_col3: keypad-col3 {
803
+
samsung,pins = "gpl2-3";
804
+
samsung,pin-function = <3>;
805
+
samsung,pin-pud = <0>;
806
+
samsung,pin-drv = <0>;
807
+
};
808
+
809
+
keypad_col4: keypad-col4 {
810
+
samsung,pins = "gpl2-4";
811
+
samsung,pin-function = <3>;
812
+
samsung,pin-pud = <0>;
813
+
samsung,pin-drv = <0>;
814
+
};
815
+
816
+
keypad_col5: keypad-col5 {
817
+
samsung,pins = "gpl2-5";
818
+
samsung,pin-function = <3>;
819
+
samsung,pin-pud = <0>;
820
+
samsung,pin-drv = <0>;
821
+
};
822
+
823
+
keypad_col6: keypad-col6 {
824
+
samsung,pins = "gpl2-6";
825
+
samsung,pin-function = <3>;
826
+
samsung,pin-pud = <0>;
827
+
samsung,pin-drv = <0>;
828
+
};
829
+
830
+
keypad_col7: keypad-col7 {
831
+
samsung,pins = "gpl2-7";
832
+
samsung,pin-function = <3>;
833
+
samsung,pin-pud = <0>;
834
+
samsung,pin-drv = <0>;
835
+
};
836
+
837
+
cam_port_b: cam-port-b {
838
+
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
839
+
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
840
+
"gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
841
+
"gpm2-2";
842
+
samsung,pin-function = <3>;
843
+
samsung,pin-pud = <3>;
844
+
samsung,pin-drv = <0>;
845
+
};
846
+
847
+
eint0: ext-int0 {
848
+
samsung,pins = "gpx0-0";
849
+
samsung,pin-function = <0xf>;
850
+
samsung,pin-pud = <0>;
851
+
samsung,pin-drv = <0>;
852
+
};
853
+
854
+
eint8: ext-int8 {
855
+
samsung,pins = "gpx1-0";
856
+
samsung,pin-function = <0xf>;
857
+
samsung,pin-pud = <0>;
858
+
samsung,pin-drv = <0>;
859
+
};
860
+
861
+
eint15: ext-int15 {
862
+
samsung,pins = "gpx1-7";
863
+
samsung,pin-function = <0xf>;
864
+
samsung,pin-pud = <0>;
865
+
samsung,pin-drv = <0>;
866
+
};
867
+
868
+
eint16: ext-int16 {
869
+
samsung,pins = "gpx2-0";
870
+
samsung,pin-function = <0xf>;
871
+
samsung,pin-pud = <0>;
872
+
samsung,pin-drv = <0>;
873
+
};
874
+
875
+
eint31: ext-int31 {
876
+
samsung,pins = "gpx3-7";
877
+
samsung,pin-function = <0xf>;
878
+
samsung,pin-pud = <0>;
879
+
samsung,pin-drv = <0>;
880
+
};
881
+
};
882
+
883
+
pinctrl@03860000 {
884
+
gpz: gpz {
885
+
gpio-controller;
886
+
#gpio-cells = <2>;
887
+
888
+
interrupt-controller;
889
+
#interrupt-cells = <2>;
890
+
};
891
+
892
+
i2s0_bus: i2s0-bus {
893
+
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
894
+
"gpz-4", "gpz-5", "gpz-6";
895
+
samsung,pin-function = <0x2>;
896
+
samsung,pin-pud = <0>;
897
+
samsung,pin-drv = <0>;
898
+
};
899
+
900
+
pcm0_bus: pcm0-bus {
901
+
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
902
+
"gpz-4";
903
+
samsung,pin-function = <0x3>;
904
+
samsung,pin-pud = <0>;
905
+
samsung,pin-drv = <0>;
906
+
};
907
+
};
908
+
909
+
pinctrl@106E0000 {
910
+
gpv0: gpv0 {
911
+
gpio-controller;
912
+
#gpio-cells = <2>;
913
+
914
+
interrupt-controller;
915
+
#interrupt-cells = <2>;
916
+
};
917
+
918
+
gpv1: gpv1 {
919
+
gpio-controller;
920
+
#gpio-cells = <2>;
921
+
922
+
interrupt-controller;
923
+
#interrupt-cells = <2>;
924
+
};
925
+
926
+
gpv2: gpv2 {
927
+
gpio-controller;
928
+
#gpio-cells = <2>;
929
+
930
+
interrupt-controller;
931
+
#interrupt-cells = <2>;
932
+
};
933
+
934
+
gpv3: gpv3 {
935
+
gpio-controller;
936
+
#gpio-cells = <2>;
937
+
938
+
interrupt-controller;
939
+
#interrupt-cells = <2>;
940
+
};
941
+
942
+
gpv4: gpv4 {
943
+
gpio-controller;
944
+
#gpio-cells = <2>;
945
+
946
+
interrupt-controller;
947
+
#interrupt-cells = <2>;
948
+
};
949
+
950
+
c2c_bus: c2c-bus {
951
+
samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
952
+
"gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
953
+
"gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
954
+
"gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
955
+
"gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
956
+
"gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
957
+
"gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
958
+
"gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
959
+
"gpv4-0", "gpv4-1";
960
+
samsung,pin-function = <0x2>;
961
+
samsung,pin-pud = <0>;
962
+
samsung,pin-drv = <0>;
963
+
};
964
+
};
965
+
};
+69
arch/arm/boot/dts/exynos4x12.dtsi
+69
arch/arm/boot/dts/exynos4x12.dtsi
···
1
+
/*
2
+
* Samsung's Exynos4x12 SoCs device tree source
3
+
*
4
+
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
5
+
* http://www.samsung.com
6
+
*
7
+
* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8
+
* based board files can include this file and provide values for board specfic
9
+
* bindings.
10
+
*
11
+
* Note: This file does not include device nodes for all the controllers in
12
+
* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13
+
* nodes can be added to this file.
14
+
*
15
+
* This program is free software; you can redistribute it and/or modify
16
+
* it under the terms of the GNU General Public License version 2 as
17
+
* published by the Free Software Foundation.
18
+
*/
19
+
20
+
/include/ "exynos4.dtsi"
21
+
/include/ "exynos4x12-pinctrl.dtsi"
22
+
23
+
/ {
24
+
aliases {
25
+
pinctrl0 = &pinctrl_0;
26
+
pinctrl1 = &pinctrl_1;
27
+
pinctrl2 = &pinctrl_2;
28
+
pinctrl3 = &pinctrl_3;
29
+
};
30
+
31
+
combiner:interrupt-controller@10440000 {
32
+
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33
+
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34
+
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35
+
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36
+
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37
+
};
38
+
39
+
pinctrl_0: pinctrl@11400000 {
40
+
compatible = "samsung,pinctrl-exynos4x12";
41
+
reg = <0x11400000 0x1000>;
42
+
interrupts = <0 47 0>;
43
+
};
44
+
45
+
pinctrl_1: pinctrl@11000000 {
46
+
compatible = "samsung,pinctrl-exynos4x12";
47
+
reg = <0x11000000 0x1000>;
48
+
interrupts = <0 46 0>;
49
+
50
+
wakup_eint: wakeup-interrupt-controller {
51
+
compatible = "samsung,exynos4210-wakeup-eint";
52
+
interrupt-parent = <&gic>;
53
+
interrupts = <0 32 0>;
54
+
};
55
+
};
56
+
57
+
pinctrl_2: pinctrl@03860000 {
58
+
compatible = "samsung,pinctrl-exynos4x12";
59
+
reg = <0x03860000 0x1000>;
60
+
interrupt-parent = <&combiner>;
61
+
interrupts = <10 0>;
62
+
};
63
+
64
+
pinctrl_3: pinctrl@106E0000 {
65
+
compatible = "samsung,pinctrl-exynos4x12";
66
+
reg = <0x106E0000 0x1000>;
67
+
interrupts = <0 72 0>;
68
+
};
69
+
};
+47
-9
arch/arm/boot/dts/exynos5250-smdk5250.dts
+47
-9
arch/arm/boot/dts/exynos5250-smdk5250.dts
···
17
17
compatible = "samsung,smdk5250", "samsung,exynos5250";
18
18
19
19
aliases {
20
-
mshc0 = &dwmmc_0;
21
-
mshc1 = &dwmmc_1;
22
-
mshc2 = &dwmmc_2;
23
-
mshc3 = &dwmmc_3;
24
20
};
25
21
26
22
memory {
···
51
55
};
52
56
};
53
57
58
+
i2c@121D0000 {
59
+
samsung,i2c-sda-delay = <100>;
60
+
samsung,i2c-max-bus-freq = <40000>;
61
+
samsung,i2c-slave-addr = <0x38>;
62
+
63
+
sata-phy {
64
+
compatible = "samsung,sata-phy";
65
+
reg = <0x38>;
66
+
};
67
+
};
68
+
69
+
sata@122F0000 {
70
+
samsung,sata-freq = <66>;
71
+
};
72
+
54
73
i2c@12C80000 {
55
-
status = "disabled";
74
+
samsung,i2c-sda-delay = <100>;
75
+
samsung,i2c-max-bus-freq = <66000>;
76
+
gpios = <&gpa0 6 3 3 0>,
77
+
<&gpa0 7 3 3 0>;
78
+
79
+
hdmiddc@50 {
80
+
compatible = "samsung,exynos5-hdmiddc";
81
+
reg = <0x50>;
82
+
};
56
83
};
57
84
58
85
i2c@12C90000 {
···
98
79
status = "disabled";
99
80
};
100
81
101
-
dwmmc_0: dwmmc0@12200000 {
82
+
i2c@12CE0000 {
83
+
samsung,i2c-sda-delay = <100>;
84
+
samsung,i2c-max-bus-freq = <66000>;
85
+
86
+
hdmiphy@38 {
87
+
compatible = "samsung,exynos5-hdmiphy";
88
+
reg = <0x38>;
89
+
};
90
+
};
91
+
92
+
dwmmc0@12200000 {
102
93
num-slots = <1>;
103
94
supports-highspeed;
104
95
broken-cd;
···
129
100
};
130
101
};
131
102
132
-
dwmmc_1: dwmmc1@12210000 {
103
+
dwmmc1@12210000 {
133
104
status = "disabled";
134
105
};
135
106
136
-
dwmmc_2: dwmmc2@12220000 {
107
+
dwmmc2@12220000 {
137
108
num-slots = <1>;
138
109
supports-highspeed;
139
110
fifo-depth = <0x80>;
···
154
125
};
155
126
};
156
127
157
-
dwmmc_3: dwmmc3@12230000 {
128
+
dwmmc3@12230000 {
158
129
status = "disabled";
159
130
};
160
131
···
194
165
195
166
spi_2: spi@12d40000 {
196
167
status = "disabled";
168
+
};
169
+
170
+
hdmi {
171
+
hpd-gpio = <&gpx3 7 0xf 1 3>;
172
+
};
173
+
174
+
codec@11000000 {
175
+
samsung,mfc-r = <0x43000000 0x800000>;
176
+
samsung,mfc-l = <0x51000000 0x800000>;
197
177
};
198
178
};
+43
arch/arm/boot/dts/exynos5250-snow.dts
+43
arch/arm/boot/dts/exynos5250-snow.dts
···
1
+
/*
2
+
* Google Snow board device tree source
3
+
*
4
+
* Copyright (c) 2012 Google, Inc
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
/dts-v1/;
12
+
/include/ "exynos5250.dtsi"
13
+
/include/ "cros5250-common.dtsi"
14
+
15
+
/ {
16
+
model = "Google Snow";
17
+
compatible = "google,snow", "samsung,exynos5250";
18
+
19
+
gpio-keys {
20
+
compatible = "gpio-keys";
21
+
22
+
lid-switch {
23
+
label = "Lid";
24
+
gpios = <&gpx3 5 0 0x10000 0>;
25
+
linux,input-type = <5>; /* EV_SW */
26
+
linux,code = <0>; /* SW_LID */
27
+
debounce-interval = <1>;
28
+
gpio-key,wakeup;
29
+
};
30
+
};
31
+
32
+
/*
33
+
* On Snow we've got SIP WiFi and so can keep drive strengths low to
34
+
* reduce EMI.
35
+
*/
36
+
dwmmc3@12230000 {
37
+
slot@0 {
38
+
gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
39
+
<&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
40
+
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41
+
};
42
+
};
43
+
};
+58
-4
arch/arm/boot/dts/exynos5250.dtsi
+58
-4
arch/arm/boot/dts/exynos5250.dtsi
···
31
31
gsc1 = &gsc_1;
32
32
gsc2 = &gsc_2;
33
33
gsc3 = &gsc_3;
34
+
mshc0 = &dwmmc_0;
35
+
mshc1 = &dwmmc_1;
36
+
mshc2 = &dwmmc_2;
37
+
mshc3 = &dwmmc_3;
34
38
};
35
39
36
40
gic:interrupt-controller@10481000 {
···
66
62
interrupts = <0 42 0>;
67
63
};
68
64
65
+
codec@11000000 {
66
+
compatible = "samsung,mfc-v6";
67
+
reg = <0x11000000 0x10000>;
68
+
interrupts = <0 96 0>;
69
+
};
70
+
69
71
rtc {
70
72
compatible = "samsung,s3c6410-rtc";
71
73
reg = <0x101E0000 0x100>;
72
74
interrupts = <0 43 0>, <0 44 0>;
75
+
};
76
+
77
+
tmu@10060000 {
78
+
compatible = "samsung,exynos5250-tmu";
79
+
reg = <0x10060000 0x100>;
80
+
interrupts = <0 65 0>;
73
81
};
74
82
75
83
serial@12C00000 {
···
106
90
compatible = "samsung,exynos4210-uart";
107
91
reg = <0x12C30000 0x100>;
108
92
interrupts = <0 54 0>;
93
+
};
94
+
95
+
sata@122F0000 {
96
+
compatible = "samsung,exynos5-sata-ahci";
97
+
reg = <0x122F0000 0x1ff>;
98
+
interrupts = <0 115 0>;
99
+
};
100
+
101
+
sata-phy@12170000 {
102
+
compatible = "samsung,exynos5-sata-phy";
103
+
reg = <0x12170000 0x1ff>;
109
104
};
110
105
111
106
i2c@12C60000 {
···
183
156
#size-cells = <0>;
184
157
};
185
158
159
+
i2c@12CE0000 {
160
+
compatible = "samsung,s3c2440-hdmiphy-i2c";
161
+
reg = <0x12CE0000 0x1000>;
162
+
interrupts = <0 64 0>;
163
+
#address-cells = <1>;
164
+
#size-cells = <0>;
165
+
};
166
+
167
+
i2c@121D0000 {
168
+
compatible = "samsung,exynos5-sata-phy-i2c";
169
+
reg = <0x121D0000 0x100>;
170
+
#address-cells = <1>;
171
+
#size-cells = <0>;
172
+
};
173
+
186
174
spi_0: spi@12d20000 {
187
175
compatible = "samsung,exynos4210-spi";
188
176
reg = <0x12d20000 0x100>;
···
228
186
#size-cells = <0>;
229
187
};
230
188
231
-
dwmmc0@12200000 {
189
+
dwmmc_0: dwmmc0@12200000 {
232
190
compatible = "samsung,exynos5250-dw-mshc";
233
191
reg = <0x12200000 0x1000>;
234
192
interrupts = <0 75 0>;
···
236
194
#size-cells = <0>;
237
195
};
238
196
239
-
dwmmc1@12210000 {
197
+
dwmmc_1: dwmmc1@12210000 {
240
198
compatible = "samsung,exynos5250-dw-mshc";
241
199
reg = <0x12210000 0x1000>;
242
200
interrupts = <0 76 0>;
···
244
202
#size-cells = <0>;
245
203
};
246
204
247
-
dwmmc2@12220000 {
205
+
dwmmc_2: dwmmc2@12220000 {
248
206
compatible = "samsung,exynos5250-dw-mshc";
249
207
reg = <0x12220000 0x1000>;
250
208
interrupts = <0 77 0>;
···
252
210
#size-cells = <0>;
253
211
};
254
212
255
-
dwmmc3@12230000 {
213
+
dwmmc_3: dwmmc3@12230000 {
256
214
compatible = "samsung,exynos5250-dw-mshc";
257
215
reg = <0x12230000 0x1000>;
258
216
interrupts = <0 78 0>;
···
561
519
compatible = "samsung,exynos5-gsc";
562
520
reg = <0x13e30000 0x1000>;
563
521
interrupts = <0 88 0>;
522
+
};
523
+
524
+
hdmi {
525
+
compatible = "samsung,exynos5-hdmi";
526
+
reg = <0x14530000 0x100000>;
527
+
interrupts = <0 95 0>;
528
+
};
529
+
530
+
mixer {
531
+
compatible = "samsung,exynos5-mixer";
532
+
reg = <0x14450000 0x10000>;
533
+
interrupts = <0 94 0>;
564
534
};
565
535
};
+273
arch/arm/boot/dts/href.dtsi
+273
arch/arm/boot/dts/href.dtsi
···
1
+
/*
2
+
* Copyright 2012 ST-Ericsson AB
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/include/ "dbx5x0.dtsi"
13
+
14
+
/ {
15
+
memory {
16
+
reg = <0x00000000 0x20000000>;
17
+
};
18
+
19
+
gpio_keys {
20
+
compatible = "gpio-keys";
21
+
#address-cells = <1>;
22
+
#size-cells = <0>;
23
+
24
+
button@1 {
25
+
linux,code = <11>;
26
+
label = "SFH7741 Proximity Sensor";
27
+
};
28
+
};
29
+
30
+
soc-u9500 {
31
+
uart@80120000 {
32
+
status = "okay";
33
+
};
34
+
35
+
uart@80121000 {
36
+
status = "okay";
37
+
};
38
+
39
+
uart@80007000 {
40
+
status = "okay";
41
+
};
42
+
43
+
i2c@80004000 {
44
+
tc3589x@42 {
45
+
compatible = "tc3589x";
46
+
reg = <0x42>;
47
+
interrupt-parent = <&gpio6>;
48
+
interrupts = <25 0x1>;
49
+
50
+
interrupt-controller;
51
+
#interrupt-cells = <2>;
52
+
53
+
tc3589x_gpio: tc3589x_gpio {
54
+
compatible = "tc3589x-gpio";
55
+
interrupts = <0 0x1>;
56
+
57
+
interrupt-controller;
58
+
#interrupt-cells = <2>;
59
+
gpio-controller;
60
+
#gpio-cells = <2>;
61
+
};
62
+
};
63
+
};
64
+
65
+
i2c@80128000 {
66
+
lp5521@0x33 {
67
+
compatible = "lp5521";
68
+
reg = <0x33>;
69
+
};
70
+
71
+
lp5521@0x34 {
72
+
compatible = "lp5521";
73
+
reg = <0x34>;
74
+
};
75
+
76
+
bh1780@0x29 {
77
+
compatible = "rohm,bh1780gli";
78
+
reg = <0x33>;
79
+
};
80
+
};
81
+
82
+
// External Micro SD slot
83
+
sdi0_per1@80126000 {
84
+
arm,primecell-periphid = <0x10480180>;
85
+
max-frequency = <50000000>;
86
+
bus-width = <4>;
87
+
mmc-cap-sd-highspeed;
88
+
mmc-cap-mmc-highspeed;
89
+
vmmc-supply = <&ab8500_ldo_aux3_reg>;
90
+
91
+
cd-gpios = <&tc3589x_gpio 3 0x4>;
92
+
93
+
status = "okay";
94
+
};
95
+
96
+
// WLAN SDIO channel
97
+
sdi1_per2@80118000 {
98
+
arm,primecell-periphid = <0x10480180>;
99
+
max-frequency = <50000000>;
100
+
bus-width = <4>;
101
+
102
+
status = "okay";
103
+
};
104
+
105
+
// PoP:ed eMMC
106
+
sdi2_per3@80005000 {
107
+
arm,primecell-periphid = <0x10480180>;
108
+
max-frequency = <50000000>;
109
+
bus-width = <8>;
110
+
mmc-cap-mmc-highspeed;
111
+
112
+
status = "okay";
113
+
};
114
+
115
+
// On-board eMMC
116
+
sdi4_per2@80114000 {
117
+
arm,primecell-periphid = <0x10480180>;
118
+
max-frequency = <50000000>;
119
+
bus-width = <8>;
120
+
mmc-cap-mmc-highspeed;
121
+
vmmc-supply = <&ab8500_ldo_aux2_reg>;
122
+
123
+
status = "okay";
124
+
};
125
+
126
+
sound {
127
+
compatible = "stericsson,snd-soc-mop500";
128
+
129
+
stericsson,cpu-dai = <&msp1 &msp3>;
130
+
stericsson,audio-codec = <&codec>;
131
+
};
132
+
133
+
msp1: msp@80124000 {
134
+
status = "okay";
135
+
};
136
+
137
+
msp3: msp@80125000 {
138
+
status = "okay";
139
+
};
140
+
141
+
prcmu@80157000 {
142
+
db8500-prcmu-regulators {
143
+
db8500_vape_reg: db8500_vape {
144
+
regulator-name = "db8500-vape";
145
+
};
146
+
147
+
db8500_varm_reg: db8500_varm {
148
+
regulator-name = "db8500-varm";
149
+
};
150
+
151
+
db8500_vmodem_reg: db8500_vmodem {
152
+
regulator-name = "db8500-vmodem";
153
+
};
154
+
155
+
db8500_vpll_reg: db8500_vpll {
156
+
regulator-name = "db8500-vpll";
157
+
};
158
+
159
+
db8500_vsmps1_reg: db8500_vsmps1 {
160
+
regulator-name = "db8500-vsmps1";
161
+
};
162
+
163
+
db8500_vsmps2_reg: db8500_vsmps2 {
164
+
regulator-name = "db8500-vsmps2";
165
+
};
166
+
167
+
db8500_vsmps3_reg: db8500_vsmps3 {
168
+
regulator-name = "db8500-vsmps3";
169
+
};
170
+
171
+
db8500_vrf1_reg: db8500_vrf1 {
172
+
regulator-name = "db8500-vrf1";
173
+
};
174
+
175
+
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
176
+
regulator-name = "db8500-sva-mmdsp";
177
+
};
178
+
179
+
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
180
+
regulator-name = "db8500-sva-mmdsp-ret";
181
+
};
182
+
183
+
db8500_sva_pipe_reg: db8500_sva_pipe {
184
+
regulator-name = "db8500_sva_pipe";
185
+
};
186
+
187
+
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
188
+
regulator-name = "db8500_sia_mmdsp";
189
+
};
190
+
191
+
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
192
+
regulator-name = "db8500-sia-mmdsp-ret";
193
+
};
194
+
195
+
db8500_sia_pipe_reg: db8500_sia_pipe {
196
+
regulator-name = "db8500-sia-pipe";
197
+
};
198
+
199
+
db8500_sga_reg: db8500_sga {
200
+
regulator-name = "db8500-sga";
201
+
};
202
+
203
+
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
204
+
regulator-name = "db8500-b2r2-mcde";
205
+
};
206
+
207
+
db8500_esram12_reg: db8500_esram12 {
208
+
regulator-name = "db8500-esram12";
209
+
};
210
+
211
+
db8500_esram12_ret_reg: db8500_esram12_ret {
212
+
regulator-name = "db8500-esram12-ret";
213
+
};
214
+
215
+
db8500_esram34_reg: db8500_esram34 {
216
+
regulator-name = "db8500-esram34";
217
+
};
218
+
219
+
db8500_esram34_ret_reg: db8500_esram34_ret {
220
+
regulator-name = "db8500-esram34-ret";
221
+
};
222
+
};
223
+
224
+
ab8500@5 {
225
+
ab8500-regulators {
226
+
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
227
+
regulator-name = "V-DISPLAY";
228
+
};
229
+
230
+
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
231
+
regulator-name = "V-eMMC1";
232
+
};
233
+
234
+
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
235
+
regulator-name = "V-MMC-SD";
236
+
};
237
+
238
+
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
239
+
regulator-name = "V-INTCORE";
240
+
};
241
+
242
+
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
243
+
regulator-name = "V-TVOUT";
244
+
};
245
+
246
+
ab8500_ldo_usb_reg: ab8500_ldo_usb {
247
+
regulator-name = "dummy";
248
+
};
249
+
250
+
ab8500_ldo_audio_reg: ab8500_ldo_audio {
251
+
regulator-name = "V-AUD";
252
+
};
253
+
254
+
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
255
+
regulator-name = "V-AMIC1";
256
+
};
257
+
258
+
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
259
+
regulator-name = "V-AMIC2";
260
+
};
261
+
262
+
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
263
+
regulator-name = "V-DMIC";
264
+
};
265
+
266
+
ab8500_ldo_ana_reg: ab8500_ldo_ana {
267
+
regulator-name = "V-CSI/DSI";
268
+
};
269
+
};
270
+
};
271
+
};
272
+
};
273
+
};
+48
arch/arm/boot/dts/hrefprev60.dts
+48
arch/arm/boot/dts/hrefprev60.dts
···
1
+
/*
2
+
* Copyright 2012 ST-Ericsson AB
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "dbx5x0.dtsi"
14
+
/include/ "href.dtsi"
15
+
/include/ "stuib.dtsi"
16
+
17
+
/ {
18
+
model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
19
+
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
20
+
21
+
gpio_keys {
22
+
button@1 {
23
+
gpios = <&tc3589x_gpio 7 0x4>;
24
+
};
25
+
};
26
+
27
+
soc-u9500 {
28
+
i2c@80004000 {
29
+
tps61052@33 {
30
+
compatible = "tps61052";
31
+
reg = <0x33>;
32
+
};
33
+
};
34
+
35
+
i2c@80110000 {
36
+
bu21013_tp@0x5c {
37
+
reset-gpio = <&tc3589x_gpio 13 0x4>;
38
+
};
39
+
};
40
+
41
+
vmmci: regulator-gpio {
42
+
gpios = <&tc3589x_gpio 18 0x4>;
43
+
gpio-enable = <&tc3589x_gpio 17 0x4>;
44
+
45
+
status = "okay";
46
+
};
47
+
};
48
+
};
+172
-57
arch/arm/boot/dts/hrefv60plus.dts
+172
-57
arch/arm/boot/dts/hrefv60plus.dts
···
11
11
12
12
/dts-v1/;
13
13
/include/ "dbx5x0.dtsi"
14
+
/include/ "href.dtsi"
15
+
/include/ "stuib.dtsi"
14
16
15
17
/ {
16
-
model = "ST-Ericsson HREF platform with Device Tree";
17
-
compatible = "st-ericsson,hrefv60+";
18
+
model = "ST-Ericsson HREF (v60+) platform with Device Tree";
19
+
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
18
20
19
-
memory {
20
-
reg = <0x00000000 0x20000000>;
21
+
gpio_keys {
22
+
button@1 {
23
+
gpios = <&gpio6 25 0x4>;
24
+
};
21
25
};
22
26
23
27
soc-u9500 {
24
-
uart@80120000 {
28
+
i2c@80110000 {
29
+
bu21013_tp@0x5c {
30
+
reset-gpio = <&gpio4 15 0x4>;
31
+
};
32
+
};
33
+
34
+
// External Micro SD slot
35
+
sdi0_per1@80126000 {
36
+
arm,primecell-periphid = <0x10480180>;
37
+
max-frequency = <50000000>;
38
+
bus-width = <4>;
39
+
mmc-cap-sd-highspeed;
40
+
mmc-cap-mmc-highspeed;
41
+
vmmc-supply = <&ab8500_ldo_aux3_reg>;
42
+
43
+
cd-gpios = <&tc3589x_gpio 3 0x4>;
44
+
25
45
status = "okay";
26
46
};
27
47
28
-
uart@80121000 {
48
+
// WLAN SDIO channel
49
+
sdi1_per2@80118000 {
50
+
arm,primecell-periphid = <0x10480180>;
51
+
max-frequency = <50000000>;
52
+
bus-width = <4>;
53
+
29
54
status = "okay";
30
55
};
31
56
32
-
uart@80007000 {
57
+
// PoP:ed eMMC
58
+
sdi2_per3@80005000 {
59
+
arm,primecell-periphid = <0x10480180>;
60
+
max-frequency = <50000000>;
61
+
bus-width = <8>;
62
+
mmc-cap-mmc-highspeed;
63
+
33
64
status = "okay";
34
65
};
35
66
36
-
i2c@80004000 {
37
-
tc3589x@42 {
38
-
compatible = "tc3589x";
39
-
reg = <0x42>;
40
-
interrupt-parent = <&gpio6>;
41
-
interrupts = <25 0x1>;
67
+
// On-board eMMC
68
+
sdi4_per2@80114000 {
69
+
arm,primecell-periphid = <0x10480180>;
70
+
max-frequency = <50000000>;
71
+
bus-width = <8>;
72
+
mmc-cap-mmc-highspeed;
73
+
vmmc-supply = <&ab8500_ldo_aux2_reg>;
42
74
43
-
interrupt-controller;
44
-
#interrupt-cells = <2>;
75
+
status = "okay";
76
+
};
45
77
46
-
tc3589x_gpio: tc3589x_gpio {
47
-
compatible = "tc3589x-gpio";
48
-
interrupts = <0 0x1>;
78
+
prcmu@80157000 {
79
+
db8500-prcmu-regulators {
80
+
db8500_vape_reg: db8500_vape {
81
+
regulator-name = "db8500-vape";
82
+
};
49
83
50
-
interrupt-controller;
51
-
#interrupt-cells = <2>;
52
-
gpio-controller;
53
-
#gpio-cells = <2>;
84
+
db8500_varm_reg: db8500_varm {
85
+
regulator-name = "db8500-varm";
86
+
};
87
+
88
+
db8500_vmodem_reg: db8500_vmodem {
89
+
regulator-name = "db8500-vmodem";
90
+
};
91
+
92
+
db8500_vpll_reg: db8500_vpll {
93
+
regulator-name = "db8500-vpll";
94
+
};
95
+
96
+
db8500_vsmps1_reg: db8500_vsmps1 {
97
+
regulator-name = "db8500-vsmps1";
98
+
};
99
+
100
+
db8500_vsmps2_reg: db8500_vsmps2 {
101
+
regulator-name = "db8500-vsmps2";
102
+
};
103
+
104
+
db8500_vsmps3_reg: db8500_vsmps3 {
105
+
regulator-name = "db8500-vsmps3";
106
+
};
107
+
108
+
db8500_vrf1_reg: db8500_vrf1 {
109
+
regulator-name = "db8500-vrf1";
110
+
};
111
+
112
+
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
113
+
regulator-name = "db8500-sva-mmdsp";
114
+
};
115
+
116
+
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
117
+
regulator-name = "db8500-sva-mmdsp-ret";
118
+
};
119
+
120
+
db8500_sva_pipe_reg: db8500_sva_pipe {
121
+
regulator-name = "db8500_sva_pipe";
122
+
};
123
+
124
+
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
125
+
regulator-name = "db8500_sia_mmdsp";
126
+
};
127
+
128
+
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
129
+
regulator-name = "db8500-sia-mmdsp-ret";
130
+
};
131
+
132
+
db8500_sia_pipe_reg: db8500_sia_pipe {
133
+
regulator-name = "db8500-sia-pipe";
134
+
};
135
+
136
+
db8500_sga_reg: db8500_sga {
137
+
regulator-name = "db8500-sga";
138
+
};
139
+
140
+
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
141
+
regulator-name = "db8500-b2r2-mcde";
142
+
};
143
+
144
+
db8500_esram12_reg: db8500_esram12 {
145
+
regulator-name = "db8500-esram12";
146
+
};
147
+
148
+
db8500_esram12_ret_reg: db8500_esram12_ret {
149
+
regulator-name = "db8500-esram12-ret";
150
+
};
151
+
152
+
db8500_esram34_reg: db8500_esram34 {
153
+
regulator-name = "db8500-esram34";
154
+
};
155
+
156
+
db8500_esram34_ret_reg: db8500_esram34_ret {
157
+
regulator-name = "db8500-esram34-ret";
54
158
};
55
159
};
56
160
57
-
tps61052@33 {
58
-
compatible = "tps61052";
59
-
reg = <0x33>;
161
+
ab8500@5 {
162
+
ab8500-regulators {
163
+
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
164
+
regulator-name = "V-DISPLAY";
165
+
};
166
+
167
+
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
168
+
regulator-name = "V-eMMC1";
169
+
};
170
+
171
+
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
172
+
regulator-name = "V-MMC-SD";
173
+
};
174
+
175
+
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
176
+
regulator-name = "V-INTCORE";
177
+
};
178
+
179
+
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
180
+
regulator-name = "V-TVOUT";
181
+
};
182
+
183
+
ab8500_ldo_usb_reg: ab8500_ldo_usb {
184
+
regulator-name = "dummy";
185
+
};
186
+
187
+
ab8500_ldo_audio_reg: ab8500_ldo_audio {
188
+
regulator-name = "V-AUD";
189
+
};
190
+
191
+
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
192
+
regulator-name = "V-AMIC1";
193
+
};
194
+
195
+
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
196
+
regulator-name = "V-AMIC2";
197
+
};
198
+
199
+
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
200
+
regulator-name = "V-DMIC";
201
+
};
202
+
203
+
ab8500_ldo_ana_reg: ab8500_ldo_ana {
204
+
regulator-name = "V-CSI/DSI";
205
+
};
206
+
};
60
207
};
61
-
};
62
-
63
-
i2c@80128000 {
64
-
lp5521@0x33 {
65
-
compatible = "lp5521";
66
-
reg = <0x33>;
67
-
};
68
-
69
-
lp5521@0x34 {
70
-
compatible = "lp5521";
71
-
reg = <0x34>;
72
-
};
73
-
74
-
bh1780@0x29 {
75
-
compatible = "rohm,bh1780gli";
76
-
reg = <0x33>;
77
-
};
78
-
};
79
-
80
-
sound {
81
-
compatible = "stericsson,snd-soc-mop500";
82
-
83
-
stericsson,cpu-dai = <&msp1 &msp3>;
84
-
stericsson,audio-codec = <&codec>;
85
-
};
86
-
87
-
msp1: msp@80124000 {
88
-
status = "okay";
89
-
};
90
-
91
-
msp3: msp@80125000 {
92
-
status = "okay";
93
208
};
94
209
};
95
210
};
+21
-2
arch/arm/boot/dts/imx23-olinuxino.dts
+21
-2
arch/arm/boot/dts/imx23-olinuxino.dts
···
40
40
reg = <0>;
41
41
fsl,pinmux-ids = <
42
42
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
43
+
>;
44
+
fsl,drive-strength = <0>;
45
+
fsl,voltage = <1>;
46
+
fsl,pull-up = <0>;
47
+
};
48
+
49
+
led_pin_gpio0_17: led_gpio0_17@0 {
50
+
reg = <0>;
51
+
fsl,pinmux-ids = <
43
52
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
44
53
>;
45
54
fsl,drive-strength = <0>;
46
55
fsl,voltage = <1>;
47
56
fsl,pull-up = <0>;
48
57
};
58
+
};
59
+
60
+
ssp1: ssp@80034000 {
61
+
#address-cells = <1>;
62
+
#size-cells = <0>;
63
+
compatible = "fsl,imx23-spi";
64
+
pinctrl-names = "default";
65
+
pinctrl-0 = <&spi2_pins_a>;
66
+
status = "okay";
49
67
};
50
68
};
51
69
···
109
91
110
92
leds {
111
93
compatible = "gpio-leds";
94
+
pinctrl-names = "default";
95
+
pinctrl-0 = <&led_pin_gpio0_17>;
112
96
113
97
user {
114
98
label = "green";
115
-
gpios = <&gpio2 1 0>;
116
-
linux,default-trigger = "default-on";
99
+
gpios = <&gpio2 1 1>;
117
100
};
118
101
};
119
102
};
+13
arch/arm/boot/dts/imx23.dtsi
+13
arch/arm/boot/dts/imx23.dtsi
···
279
279
fsl,voltage = <1>;
280
280
fsl,pull-up = <0>;
281
281
};
282
+
283
+
spi2_pins_a: spi2@0 {
284
+
reg = <0>;
285
+
fsl,pinmux-ids = <
286
+
0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
287
+
0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
288
+
0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
289
+
0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
290
+
>;
291
+
fsl,drive-strength = <1>;
292
+
fsl,voltage = <1>;
293
+
fsl,pull-up = <1>;
294
+
};
282
295
};
283
296
284
297
digctl@8001c000 {
+44
arch/arm/boot/dts/imx25-karo-tx25.dts
+44
arch/arm/boot/dts/imx25-karo-tx25.dts
···
1
+
/*
2
+
* Copyright 2012 Sascha Hauer, Pengutronix
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "imx25.dtsi"
14
+
15
+
/ {
16
+
model = "Ka-Ro TX25";
17
+
compatible = "karo,imx25-tx25", "fsl,imx25";
18
+
19
+
memory {
20
+
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21
+
};
22
+
23
+
soc {
24
+
aips@43f00000 {
25
+
uart1: serial@43f90000 {
26
+
status = "okay";
27
+
};
28
+
};
29
+
30
+
spba@50000000 {
31
+
fec: ethernet@50038000 {
32
+
status = "okay";
33
+
phy-mode = "rmii";
34
+
};
35
+
};
36
+
37
+
emi@80000000 {
38
+
nand@bb000000 {
39
+
nand-on-flash-bbt;
40
+
status = "okay";
41
+
};
42
+
};
43
+
};
44
+
};
+515
arch/arm/boot/dts/imx25.dtsi
+515
arch/arm/boot/dts/imx25.dtsi
···
1
+
/*
2
+
* Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/include/ "skeleton.dtsi"
13
+
14
+
/ {
15
+
aliases {
16
+
serial0 = &uart1;
17
+
serial1 = &uart2;
18
+
serial2 = &uart3;
19
+
serial3 = &uart4;
20
+
serial4 = &uart5;
21
+
gpio0 = &gpio1;
22
+
gpio1 = &gpio2;
23
+
gpio2 = &gpio3;
24
+
gpio3 = &gpio4;
25
+
usb0 = &usbotg;
26
+
usb1 = &usbhost1;
27
+
};
28
+
29
+
asic: asic-interrupt-controller@68000000 {
30
+
compatible = "fsl,imx25-asic", "fsl,avic";
31
+
interrupt-controller;
32
+
#interrupt-cells = <1>;
33
+
reg = <0x68000000 0x8000000>;
34
+
};
35
+
36
+
clocks {
37
+
#address-cells = <1>;
38
+
#size-cells = <0>;
39
+
40
+
osc {
41
+
compatible = "fsl,imx-osc", "fixed-clock";
42
+
clock-frequency = <24000000>;
43
+
};
44
+
};
45
+
46
+
soc {
47
+
#address-cells = <1>;
48
+
#size-cells = <1>;
49
+
compatible = "simple-bus";
50
+
interrupt-parent = <&asic>;
51
+
ranges;
52
+
53
+
aips@43f00000 { /* AIPS1 */
54
+
compatible = "fsl,aips-bus", "simple-bus";
55
+
#address-cells = <1>;
56
+
#size-cells = <1>;
57
+
reg = <0x43f00000 0x100000>;
58
+
ranges;
59
+
60
+
i2c1: i2c@43f80000 {
61
+
#address-cells = <1>;
62
+
#size-cells = <0>;
63
+
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
64
+
reg = <0x43f80000 0x4000>;
65
+
clocks = <&clks 48>;
66
+
clock-names = "";
67
+
interrupts = <3>;
68
+
status = "disabled";
69
+
};
70
+
71
+
i2c3: i2c@43f84000 {
72
+
#address-cells = <1>;
73
+
#size-cells = <0>;
74
+
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
75
+
reg = <0x43f84000 0x4000>;
76
+
clocks = <&clks 48>;
77
+
clock-names = "";
78
+
interrupts = <10>;
79
+
status = "disabled";
80
+
};
81
+
82
+
can1: can@43f88000 {
83
+
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
84
+
reg = <0x43f88000 0x4000>;
85
+
interrupts = <43>;
86
+
clocks = <&clks 75>, <&clks 75>;
87
+
clock-names = "ipg", "per";
88
+
status = "disabled";
89
+
};
90
+
91
+
can2: can@43f8c000 {
92
+
compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
93
+
reg = <0x43f8c000 0x4000>;
94
+
interrupts = <44>;
95
+
clocks = <&clks 76>, <&clks 76>;
96
+
clock-names = "ipg", "per";
97
+
status = "disabled";
98
+
};
99
+
100
+
uart1: serial@43f90000 {
101
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
102
+
reg = <0x43f90000 0x4000>;
103
+
interrupts = <45>;
104
+
clocks = <&clks 120>, <&clks 57>;
105
+
clock-names = "ipg", "per";
106
+
status = "disabled";
107
+
};
108
+
109
+
uart2: serial@43f94000 {
110
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
111
+
reg = <0x43f94000 0x4000>;
112
+
interrupts = <32>;
113
+
clocks = <&clks 121>, <&clks 57>;
114
+
clock-names = "ipg", "per";
115
+
status = "disabled";
116
+
};
117
+
118
+
i2c2: i2c@43f98000 {
119
+
#address-cells = <1>;
120
+
#size-cells = <0>;
121
+
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
122
+
reg = <0x43f98000 0x4000>;
123
+
clocks = <&clks 48>;
124
+
clock-names = "";
125
+
interrupts = <4>;
126
+
status = "disabled";
127
+
};
128
+
129
+
owire@43f9c000 {
130
+
#address-cells = <1>;
131
+
#size-cells = <0>;
132
+
reg = <0x43f9c000 0x4000>;
133
+
clocks = <&clks 51>;
134
+
clock-names = "";
135
+
interrupts = <2>;
136
+
status = "disabled";
137
+
};
138
+
139
+
spi1: cspi@43fa4000 {
140
+
#address-cells = <1>;
141
+
#size-cells = <0>;
142
+
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
143
+
reg = <0x43fa4000 0x4000>;
144
+
clocks = <&clks 62>;
145
+
clock-names = "ipg";
146
+
interrupts = <14>;
147
+
status = "disabled";
148
+
};
149
+
150
+
kpp@43fa8000 {
151
+
#address-cells = <1>;
152
+
#size-cells = <0>;
153
+
reg = <0x43fa8000 0x4000>;
154
+
clocks = <&clks 102>;
155
+
clock-names = "";
156
+
interrupts = <24>;
157
+
status = "disabled";
158
+
};
159
+
160
+
iomuxc@43fac000{
161
+
compatible = "fsl,imx25-iomuxc";
162
+
reg = <0x43fac000 0x4000>;
163
+
};
164
+
165
+
audmux@43fb0000 {
166
+
compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
167
+
reg = <0x43fb0000 0x4000>;
168
+
status = "disabled";
169
+
};
170
+
};
171
+
172
+
spba@50000000 {
173
+
compatible = "fsl,spba-bus", "simple-bus";
174
+
#address-cells = <1>;
175
+
#size-cells = <1>;
176
+
reg = <0x50000000 0x40000>;
177
+
ranges;
178
+
179
+
spi3: cspi@50004000 {
180
+
#address-cells = <1>;
181
+
#size-cells = <0>;
182
+
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
183
+
reg = <0x50004000 0x4000>;
184
+
interrupts = <0>;
185
+
clocks = <&clks 80>;
186
+
clock-names = "ipg";
187
+
status = "disabled";
188
+
};
189
+
190
+
uart4: serial@50008000 {
191
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
192
+
reg = <0x50008000 0x4000>;
193
+
interrupts = <5>;
194
+
clocks = <&clks 123>, <&clks 57>;
195
+
clock-names = "ipg", "per";
196
+
status = "disabled";
197
+
};
198
+
199
+
uart3: serial@5000c000 {
200
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
201
+
reg = <0x5000c000 0x4000>;
202
+
interrupts = <18>;
203
+
clocks = <&clks 122>, <&clks 57>;
204
+
clock-names = "ipg", "per";
205
+
status = "disabled";
206
+
};
207
+
208
+
spi2: cspi@50010000 {
209
+
#address-cells = <1>;
210
+
#size-cells = <0>;
211
+
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
212
+
reg = <0x50010000 0x4000>;
213
+
clocks = <&clks 79>;
214
+
clock-names = "ipg";
215
+
interrupts = <13>;
216
+
status = "disabled";
217
+
};
218
+
219
+
ssi2: ssi@50014000 {
220
+
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
221
+
reg = <0x50014000 0x4000>;
222
+
interrupts = <11>;
223
+
status = "disabled";
224
+
};
225
+
226
+
esai@50018000 {
227
+
reg = <0x50018000 0x4000>;
228
+
interrupts = <7>;
229
+
};
230
+
231
+
uart5: serial@5002c000 {
232
+
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
233
+
reg = <0x5002c000 0x4000>;
234
+
interrupts = <40>;
235
+
clocks = <&clks 124>, <&clks 57>;
236
+
clock-names = "ipg", "per";
237
+
status = "disabled";
238
+
};
239
+
240
+
tsc: tsc@50030000 {
241
+
compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
242
+
reg = <0x50030000 0x4000>;
243
+
interrupts = <46>;
244
+
clocks = <&clks 119>;
245
+
clock-names = "ipg";
246
+
status = "disabled";
247
+
};
248
+
249
+
ssi1: ssi@50034000 {
250
+
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
251
+
reg = <0x50034000 0x4000>;
252
+
interrupts = <12>;
253
+
status = "disabled";
254
+
};
255
+
256
+
fec: ethernet@50038000 {
257
+
compatible = "fsl,imx25-fec";
258
+
reg = <0x50038000 0x4000>;
259
+
interrupts = <57>;
260
+
clocks = <&clks 88>, <&clks 65>;
261
+
clock-names = "ipg", "ahb";
262
+
status = "disabled";
263
+
};
264
+
};
265
+
266
+
aips@53f00000 { /* AIPS2 */
267
+
compatible = "fsl,aips-bus", "simple-bus";
268
+
#address-cells = <1>;
269
+
#size-cells = <1>;
270
+
reg = <0x53f00000 0x100000>;
271
+
ranges;
272
+
273
+
clks: ccm@53f80000 {
274
+
compatible = "fsl,imx25-ccm";
275
+
reg = <0x53f80000 0x4000>;
276
+
interrupts = <31>;
277
+
#clock-cells = <1>;
278
+
};
279
+
280
+
gpt4: timer@53f84000 {
281
+
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
282
+
reg = <0x53f84000 0x4000>;
283
+
clocks = <&clks 9>, <&clks 45>;
284
+
clock-names = "ipg", "per";
285
+
interrupts = <1>;
286
+
};
287
+
288
+
gpt3: timer@53f88000 {
289
+
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
290
+
reg = <0x53f88000 0x4000>;
291
+
clocks = <&clks 9>, <&clks 47>;
292
+
clock-names = "ipg", "per";
293
+
interrupts = <29>;
294
+
};
295
+
296
+
gpt2: timer@53f8c000 {
297
+
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
298
+
reg = <0x53f8c000 0x4000>;
299
+
clocks = <&clks 9>, <&clks 47>;
300
+
clock-names = "ipg", "per";
301
+
interrupts = <53>;
302
+
};
303
+
304
+
gpt1: timer@53f90000 {
305
+
compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
306
+
reg = <0x53f90000 0x4000>;
307
+
clocks = <&clks 9>, <&clks 47>;
308
+
clock-names = "ipg", "per";
309
+
interrupts = <54>;
310
+
};
311
+
312
+
epit1: timer@53f94000 {
313
+
compatible = "fsl,imx25-epit";
314
+
reg = <0x53f94000 0x4000>;
315
+
interrupts = <28>;
316
+
};
317
+
318
+
epit2: timer@53f98000 {
319
+
compatible = "fsl,imx25-epit";
320
+
reg = <0x53f98000 0x4000>;
321
+
interrupts = <27>;
322
+
};
323
+
324
+
gpio4: gpio@53f9c000 {
325
+
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
326
+
reg = <0x53f9c000 0x4000>;
327
+
interrupts = <23>;
328
+
gpio-controller;
329
+
#gpio-cells = <2>;
330
+
interrupt-controller;
331
+
#interrupt-cells = <2>;
332
+
};
333
+
334
+
pwm2: pwm@53fa0000 {
335
+
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
336
+
#pwm-cells = <2>;
337
+
reg = <0x53fa0000 0x4000>;
338
+
clocks = <&clks 106>, <&clks 36>;
339
+
clock-names = "ipg", "per";
340
+
interrupts = <36>;
341
+
};
342
+
343
+
gpio3: gpio@53fa4000 {
344
+
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
345
+
reg = <0x53fa4000 0x4000>;
346
+
interrupts = <16>;
347
+
gpio-controller;
348
+
#gpio-cells = <2>;
349
+
interrupt-controller;
350
+
#interrupt-cells = <2>;
351
+
};
352
+
353
+
pwm3: pwm@53fa8000 {
354
+
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
355
+
#pwm-cells = <2>;
356
+
reg = <0x53fa8000 0x4000>;
357
+
clocks = <&clks 107>, <&clks 36>;
358
+
clock-names = "ipg", "per";
359
+
interrupts = <41>;
360
+
};
361
+
362
+
esdhc1: esdhc@53fb4000 {
363
+
compatible = "fsl,imx25-esdhc";
364
+
reg = <0x53fb4000 0x4000>;
365
+
interrupts = <9>;
366
+
clocks = <&clks 86>, <&clks 63>, <&clks 45>;
367
+
clock-names = "ipg", "ahb", "per";
368
+
status = "disabled";
369
+
};
370
+
371
+
esdhc2: esdhc@53fb8000 {
372
+
compatible = "fsl,imx25-esdhc";
373
+
reg = <0x53fb8000 0x4000>;
374
+
interrupts = <8>;
375
+
clocks = <&clks 87>, <&clks 64>, <&clks 46>;
376
+
clock-names = "ipg", "ahb", "per";
377
+
status = "disabled";
378
+
};
379
+
380
+
lcdc@53fbc000 {
381
+
reg = <0x53fbc000 0x4000>;
382
+
interrupts = <39>;
383
+
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
384
+
clock-names = "ipg", "ahb", "per";
385
+
status = "disabled";
386
+
};
387
+
388
+
slcdc@53fc0000 {
389
+
reg = <0x53fc0000 0x4000>;
390
+
interrupts = <38>;
391
+
status = "disabled";
392
+
};
393
+
394
+
pwm4: pwm@53fc8000 {
395
+
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
396
+
reg = <0x53fc8000 0x4000>;
397
+
clocks = <&clks 108>, <&clks 36>;
398
+
clock-names = "ipg", "per";
399
+
interrupts = <42>;
400
+
};
401
+
402
+
gpio1: gpio@53fcc000 {
403
+
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404
+
reg = <0x53fcc000 0x4000>;
405
+
interrupts = <52>;
406
+
gpio-controller;
407
+
#gpio-cells = <2>;
408
+
interrupt-controller;
409
+
#interrupt-cells = <2>;
410
+
};
411
+
412
+
gpio2: gpio@53fd0000 {
413
+
compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
414
+
reg = <0x53fd0000 0x4000>;
415
+
interrupts = <51>;
416
+
gpio-controller;
417
+
#gpio-cells = <2>;
418
+
interrupt-controller;
419
+
#interrupt-cells = <2>;
420
+
};
421
+
422
+
sdma@53fd4000 {
423
+
compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
424
+
reg = <0x53fd4000 0x4000>;
425
+
clocks = <&clks 112>, <&clks 68>;
426
+
clock-names = "ipg", "ahb";
427
+
interrupts = <34>;
428
+
};
429
+
430
+
wdog@53fdc000 {
431
+
compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
432
+
reg = <0x53fdc000 0x4000>;
433
+
clocks = <&clks 126>;
434
+
clock-names = "";
435
+
interrupts = <55>;
436
+
};
437
+
438
+
pwm1: pwm@53fe0000 {
439
+
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
440
+
#pwm-cells = <2>;
441
+
reg = <0x53fe0000 0x4000>;
442
+
clocks = <&clks 105>, <&clks 36>;
443
+
clock-names = "ipg", "per";
444
+
interrupts = <26>;
445
+
};
446
+
447
+
usbphy1: usbphy@1 {
448
+
compatible = "nop-usbphy";
449
+
status = "disabled";
450
+
};
451
+
452
+
usbphy2: usbphy@2 {
453
+
compatible = "nop-usbphy";
454
+
status = "disabled";
455
+
};
456
+
457
+
usbotg: usb@53ff4000 {
458
+
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
459
+
reg = <0x53ff4000 0x0200>;
460
+
interrupts = <37>;
461
+
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
462
+
clock-names = "ipg", "ahb", "per";
463
+
fsl,usbmisc = <&usbmisc 0>;
464
+
status = "disabled";
465
+
};
466
+
467
+
usbhost1: usb@53ff4400 {
468
+
compatible = "fsl,imx25-usb", "fsl,imx27-usb";
469
+
reg = <0x53ff4400 0x0200>;
470
+
interrupts = <35>;
471
+
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
472
+
clock-names = "ipg", "ahb", "per";
473
+
fsl,usbmisc = <&usbmisc 1>;
474
+
status = "disabled";
475
+
};
476
+
477
+
usbmisc: usbmisc@53ff4600 {
478
+
#index-cells = <1>;
479
+
compatible = "fsl,imx25-usbmisc";
480
+
clocks = <&clks 9>, <&clks 70>, <&clks 8>;
481
+
clock-names = "ipg", "ahb", "per";
482
+
reg = <0x53ff4600 0x00f>;
483
+
status = "disabled";
484
+
};
485
+
486
+
dryice@53ffc000 {
487
+
compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
488
+
reg = <0x53ffc000 0x4000>;
489
+
clocks = <&clks 81>;
490
+
clock-names = "ipg";
491
+
interrupts = <25>;
492
+
};
493
+
};
494
+
495
+
emi@80000000 {
496
+
compatible = "fsl,emi-bus", "simple-bus";
497
+
#address-cells = <1>;
498
+
#size-cells = <1>;
499
+
reg = <0x80000000 0x3b002000>;
500
+
ranges;
501
+
502
+
nand@bb000000 {
503
+
#address-cells = <1>;
504
+
#size-cells = <1>;
505
+
506
+
compatible = "fsl,imx25-nand";
507
+
reg = <0xbb000000 0x2000>;
508
+
clocks = <&clks 50>;
509
+
clock-names = "";
510
+
interrupts = <33>;
511
+
status = "disabled";
512
+
};
513
+
};
514
+
};
515
+
};
+89
arch/arm/boot/dts/imx27-apf27.dts
+89
arch/arm/boot/dts/imx27-apf27.dts
···
1
+
/*
2
+
* Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
3
+
* Copyright 2012 Armadeus Systems <support@armadeus.com>
4
+
*
5
+
* Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
6
+
*
7
+
* The code contained herein is licensed under the GNU General Public
8
+
* License. You may obtain a copy of the GNU General Public License
9
+
* Version 2 or later at the following locations:
10
+
*
11
+
* http://www.opensource.org/licenses/gpl-license.html
12
+
* http://www.gnu.org/copyleft/gpl.html
13
+
*/
14
+
15
+
/dts-v1/;
16
+
/include/ "imx27.dtsi"
17
+
18
+
/ {
19
+
model = "Armadeus Systems APF27 module";
20
+
compatible = "armadeus,imx27-apf27", "fsl,imx27";
21
+
22
+
memory {
23
+
reg = <0xa0000000 0x04000000>;
24
+
};
25
+
26
+
clocks {
27
+
#address-cells = <1>;
28
+
#size-cells = <0>;
29
+
30
+
osc26m {
31
+
compatible = "fsl,imx-osc26m", "fixed-clock";
32
+
clock-frequency = <0>;
33
+
};
34
+
};
35
+
36
+
soc {
37
+
aipi@10000000 {
38
+
serial@1000a000 {
39
+
status = "okay";
40
+
};
41
+
42
+
ethernet@1002b000 {
43
+
status = "okay";
44
+
};
45
+
};
46
+
47
+
nand@d8000000 {
48
+
status = "okay";
49
+
nand-bus-width = <16>;
50
+
nand-ecc-mode = "hw";
51
+
nand-on-flash-bbt;
52
+
53
+
partition@0 {
54
+
label = "u-boot";
55
+
reg = <0x0 0x100000>;
56
+
};
57
+
58
+
partition@100000 {
59
+
label = "env";
60
+
reg = <0x100000 0x80000>;
61
+
};
62
+
63
+
partition@180000 {
64
+
label = "env2";
65
+
reg = <0x180000 0x80000>;
66
+
};
67
+
68
+
partition@200000 {
69
+
label = "firmware";
70
+
reg = <0x200000 0x80000>;
71
+
};
72
+
73
+
partition@280000 {
74
+
label = "dtb";
75
+
reg = <0x280000 0x80000>;
76
+
};
77
+
78
+
partition@300000 {
79
+
label = "kernel";
80
+
reg = <0x300000 0x500000>;
81
+
};
82
+
83
+
partition@800000 {
84
+
label = "rootfs";
85
+
reg = <0x800000 0xf800000>;
86
+
};
87
+
};
88
+
};
89
+
};
+3
-2
arch/arm/boot/dts/imx27.dtsi
+3
-2
arch/arm/boot/dts/imx27.dtsi
···
58
58
reg = <0x10000000 0x10000000>;
59
59
ranges;
60
60
61
-
wdog@10002000 {
61
+
wdog: wdog@10002000 {
62
62
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63
63
reg = <0x10002000 0x4000>;
64
64
interrupts = <27>;
···
218
218
status = "disabled";
219
219
};
220
220
};
221
-
nand@d8000000 {
221
+
222
+
nfc: nand@d8000000 {
222
223
#address-cells = <1>;
223
224
#size-cells = <1>;
224
225
+85
arch/arm/boot/dts/imx28-apf28.dts
+85
arch/arm/boot/dts/imx28-apf28.dts
···
1
+
/*
2
+
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "imx28.dtsi"
14
+
15
+
/ {
16
+
model = "Armadeus Systems APF28 module";
17
+
compatible = "armadeus,imx28-apf28", "fsl,imx28";
18
+
19
+
memory {
20
+
reg = <0x40000000 0x08000000>;
21
+
};
22
+
23
+
apb@80000000 {
24
+
apbh@80000000 {
25
+
gpmi-nand@8000c000 {
26
+
pinctrl-names = "default";
27
+
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28
+
status = "okay";
29
+
30
+
partition@0 {
31
+
label = "u-boot";
32
+
reg = <0x0 0x300000>;
33
+
};
34
+
35
+
partition@300000 {
36
+
label = "env";
37
+
reg = <0x300000 0x80000>;
38
+
};
39
+
40
+
partition@380000 {
41
+
label = "env2";
42
+
reg = <0x380000 0x80000>;
43
+
};
44
+
45
+
partition@400000 {
46
+
label = "dtb";
47
+
reg = <0x400000 0x80000>;
48
+
};
49
+
50
+
partition@480000 {
51
+
label = "splash";
52
+
reg = <0x480000 0x80000>;
53
+
};
54
+
55
+
partition@500000 {
56
+
label = "kernel";
57
+
reg = <0x500000 0x800000>;
58
+
};
59
+
60
+
partition@d00000 {
61
+
label = "rootfs";
62
+
reg = <0xd00000 0xf300000>;
63
+
};
64
+
};
65
+
};
66
+
67
+
apbx@80040000 {
68
+
duart: serial@80074000 {
69
+
pinctrl-names = "default";
70
+
pinctrl-0 = <&duart_pins_a>;
71
+
status = "okay";
72
+
};
73
+
};
74
+
};
75
+
76
+
ahb@80080000 {
77
+
mac0: ethernet@800f0000 {
78
+
phy-mode = "rmii";
79
+
pinctrl-names = "default";
80
+
pinctrl-0 = <&mac0_pins_a>;
81
+
phy-reset-gpios = <&gpio4 13 0>;
82
+
status = "okay";
83
+
};
84
+
};
85
+
};
+154
arch/arm/boot/dts/imx28-apf28dev.dts
+154
arch/arm/boot/dts/imx28-apf28dev.dts
···
1
+
/*
2
+
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/* APF28Dev is a docking board for the APF28 SOM */
13
+
/include/ "imx28-apf28.dts"
14
+
15
+
/ {
16
+
model = "Armadeus Systems APF28Dev docking/development board";
17
+
compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
18
+
19
+
apb@80000000 {
20
+
apbh@80000000 {
21
+
ssp0: ssp@80010000 {
22
+
compatible = "fsl,imx28-mmc";
23
+
pinctrl-names = "default";
24
+
pinctrl-0 = <&mmc0_4bit_pins_a
25
+
&mmc0_cd_cfg &mmc0_sck_cfg>;
26
+
bus-width = <4>;
27
+
status = "okay";
28
+
};
29
+
30
+
ssp2: ssp@80014000 {
31
+
compatible = "fsl,imx28-spi";
32
+
pinctrl-names = "default";
33
+
pinctrl-0 = <&spi2_pins_a>;
34
+
status = "okay";
35
+
};
36
+
37
+
pinctrl@80018000 {
38
+
pinctrl-names = "default";
39
+
pinctrl-0 = <&hog_pins_apf28dev>;
40
+
41
+
hog_pins_apf28dev: hog@0 {
42
+
reg = <0>;
43
+
fsl,pinmux-ids = <
44
+
0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */
45
+
0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */
46
+
0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */
47
+
0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */
48
+
0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */
49
+
0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
50
+
0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
51
+
>;
52
+
fsl,drive-strength = <0>;
53
+
fsl,voltage = <1>;
54
+
fsl,pull-up = <0>;
55
+
};
56
+
57
+
lcdif_pins_apf28dev: lcdif-apf28dev@0 {
58
+
reg = <0>;
59
+
fsl,pinmux-ids = <
60
+
0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
61
+
0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
62
+
0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
63
+
0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
64
+
>;
65
+
fsl,drive-strength = <0>;
66
+
fsl,voltage = <1>;
67
+
fsl,pull-up = <0>;
68
+
};
69
+
};
70
+
71
+
lcdif@80030000 {
72
+
pinctrl-names = "default";
73
+
pinctrl-0 = <&lcdif_16bit_pins_a
74
+
&lcdif_pins_apf28dev>;
75
+
status = "okay";
76
+
};
77
+
};
78
+
79
+
apbx@80040000 {
80
+
lradc@80050000 {
81
+
status = "okay";
82
+
};
83
+
84
+
i2c0: i2c@80058000 {
85
+
pinctrl-names = "default";
86
+
pinctrl-0 = <&i2c0_pins_a>;
87
+
status = "okay";
88
+
};
89
+
90
+
pwm: pwm@80064000 {
91
+
pinctrl-names = "default";
92
+
pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
93
+
status = "okay";
94
+
};
95
+
96
+
usbphy0: usbphy@8007c000 {
97
+
status = "okay";
98
+
};
99
+
100
+
usbphy1: usbphy@8007e000 {
101
+
status = "okay";
102
+
};
103
+
};
104
+
};
105
+
106
+
ahb@80080000 {
107
+
usb0: usb@80080000 {
108
+
vbus-supply = <®_usb0_vbus>;
109
+
status = "okay";
110
+
};
111
+
112
+
usb1: usb@80090000 {
113
+
status = "okay";
114
+
};
115
+
116
+
mac1: ethernet@800f4000 {
117
+
phy-mode = "rmii";
118
+
pinctrl-names = "default";
119
+
pinctrl-0 = <&mac1_pins_a>;
120
+
phy-reset-gpios = <&gpio0 23 0>;
121
+
status = "okay";
122
+
};
123
+
};
124
+
125
+
regulators {
126
+
compatible = "simple-bus";
127
+
128
+
reg_usb0_vbus: usb0_vbus {
129
+
compatible = "regulator-fixed";
130
+
regulator-name = "usb0_vbus";
131
+
regulator-min-microvolt = <5000000>;
132
+
regulator-max-microvolt = <5000000>;
133
+
gpio = <&gpio1 23 1>;
134
+
};
135
+
};
136
+
137
+
leds {
138
+
compatible = "gpio-leds";
139
+
140
+
user {
141
+
label = "Heartbeat";
142
+
gpios = <&gpio0 21 0>;
143
+
linux,default-trigger = "heartbeat";
144
+
};
145
+
};
146
+
147
+
backlight {
148
+
compatible = "pwm-backlight";
149
+
150
+
pwms = <&pwm 3 191000>;
151
+
brightness-levels = <0 4 8 16 32 64 128 255>;
152
+
default-brightness-level = <6>;
153
+
};
154
+
};
+46
arch/arm/boot/dts/imx28-cfa10036.dts
+46
arch/arm/boot/dts/imx28-cfa10036.dts
···
22
22
23
23
apb@80000000 {
24
24
apbh@80000000 {
25
+
pinctrl@80018000 {
26
+
pinctrl-names = "default";
27
+
pinctrl-0 = <&hog_pins_cfa10036>;
28
+
29
+
hog_pins_cfa10036: hog-10036@0 {
30
+
reg = <0>;
31
+
fsl,pinmux-ids = <
32
+
0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
33
+
>;
34
+
fsl,drive-strength = <0>;
35
+
fsl,voltage = <1>;
36
+
fsl,pull-up = <0>;
37
+
};
38
+
39
+
led_pins_cfa10036: leds-10036@0 {
40
+
reg = <0>;
41
+
fsl,pinmux-ids = <
42
+
0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
43
+
>;
44
+
fsl,drive-strength = <0>;
45
+
fsl,voltage = <1>;
46
+
fsl,pull-up = <0>;
47
+
};
48
+
};
49
+
25
50
ssp0: ssp@80010000 {
26
51
compatible = "fsl,imx28-mmc";
27
52
pinctrl-names = "default";
···
58
33
};
59
34
60
35
apbx@80040000 {
36
+
pwm: pwm@80064000 {
37
+
pinctrl-names = "default";
38
+
pinctrl-0 = <&pwm4_pins_a>;
39
+
status = "okay";
40
+
};
41
+
61
42
duart: serial@80074000 {
62
43
pinctrl-names = "default";
63
44
pinctrl-0 = <&duart_pins_b>;
64
45
status = "okay";
46
+
};
47
+
48
+
i2c0: i2c@80058000 {
49
+
pinctrl-names = "default";
50
+
pinctrl-0 = <&i2c0_pins_b>;
51
+
status = "okay";
52
+
53
+
ssd1307: oled@3c {
54
+
compatible = "solomon,ssd1307fb-i2c";
55
+
reg = <0x3c>;
56
+
pwms = <&pwm 4 3000>;
57
+
reset-gpios = <&gpio2 7 0>;
58
+
};
65
59
};
66
60
};
67
61
};
68
62
69
63
leds {
70
64
compatible = "gpio-leds";
65
+
pinctrl-names = "default";
66
+
pinctrl-0 = <&led_pins_cfa10036>;
71
67
72
68
power {
73
69
gpios = <&gpio3 4 1>;
+33
arch/arm/boot/dts/imx28-cfa10049.dts
+33
arch/arm/boot/dts/imx28-cfa10049.dts
···
22
22
apb@80000000 {
23
23
apbh@80000000 {
24
24
pinctrl@80018000 {
25
+
pinctrl-names = "default", "default";
26
+
pinctrl-1 = <&hog_pins_cfa10049>;
27
+
28
+
hog_pins_cfa10049: hog-10049@0 {
29
+
reg = <0>;
30
+
fsl,pinmux-ids = <
31
+
0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
32
+
0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
33
+
0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
34
+
0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
35
+
>;
36
+
fsl,drive-strength = <0>;
37
+
fsl,voltage = <1>;
38
+
fsl,pull-up = <0>;
39
+
};
40
+
25
41
spi3_pins_cfa10049: spi3-cfa10049@0 {
26
42
reg = <0>;
27
43
fsl,pinmux-ids = <
···
45
29
0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
46
30
0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
47
31
0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
32
+
0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
48
33
>;
49
34
fsl,drive-strength = <1>;
50
35
fsl,voltage = <1>;
···
77
60
spi-max-frequency = <100000>;
78
61
};
79
62
63
+
dac0: dh2228@2 {
64
+
compatible = "rohm,dh2228fv";
65
+
reg = <2>;
66
+
spi-max-frequency = <100000>;
67
+
};
80
68
};
81
69
};
82
70
···
116
94
regulator-min-microvolt = <5000000>;
117
95
regulator-max-microvolt = <5000000>;
118
96
gpio = <&gpio0 7 1>;
97
+
};
98
+
};
99
+
100
+
ahb@80080000 {
101
+
mac0: ethernet@800f0000 {
102
+
phy-mode = "rmii";
103
+
pinctrl-names = "default";
104
+
pinctrl-0 = <&mac0_pins_a>;
105
+
phy-reset-gpios = <&gpio2 21 0>;
106
+
phy-reset-duration = <100>;
107
+
status = "okay";
119
108
};
120
109
};
121
110
};
+12
-1
arch/arm/boot/dts/imx28-evk.dts
+12
-1
arch/arm/boot/dts/imx28-evk.dts
···
76
76
0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
77
77
0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
78
78
0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
79
-
0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
80
79
0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
81
80
0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
81
+
>;
82
+
fsl,drive-strength = <0>;
83
+
fsl,voltage = <1>;
84
+
fsl,pull-up = <0>;
85
+
};
86
+
87
+
led_pin_gpio3_5: led_gpio3_5@0 {
88
+
reg = <0>;
89
+
fsl,pinmux-ids = <
90
+
0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
82
91
>;
83
92
fsl,drive-strength = <0>;
84
93
fsl,voltage = <1>;
···
297
288
298
289
leds {
299
290
compatible = "gpio-leds";
291
+
pinctrl-names = "default";
292
+
pinctrl-0 = <&led_pin_gpio3_5>;
300
293
301
294
user {
302
295
label = "Heartbeat";
+169
arch/arm/boot/dts/imx28-sps1.dts
+169
arch/arm/boot/dts/imx28-sps1.dts
···
1
+
/*
2
+
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "imx28.dtsi"
14
+
15
+
/ {
16
+
model = "SchulerControl GmbH, SC SPS 1";
17
+
compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
18
+
19
+
memory {
20
+
reg = <0x40000000 0x08000000>;
21
+
};
22
+
23
+
apb@80000000 {
24
+
apbh@80000000 {
25
+
pinctrl@80018000 {
26
+
pinctrl-names = "default";
27
+
pinctrl-0 = <&hog_pins_a>;
28
+
29
+
hog_pins_a: hog-gpios@0 {
30
+
reg = <0>;
31
+
fsl,pinmux-ids = <
32
+
0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
33
+
0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
34
+
0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
35
+
>;
36
+
fsl,drive-strength = <0>;
37
+
fsl,voltage = <1>;
38
+
fsl,pull-up = <0>;
39
+
};
40
+
41
+
};
42
+
43
+
ssp0: ssp@80010000 {
44
+
compatible = "fsl,imx28-mmc";
45
+
pinctrl-names = "default";
46
+
pinctrl-0 = <&mmc0_4bit_pins_a>;
47
+
bus-width = <4>;
48
+
status = "okay";
49
+
};
50
+
51
+
ssp2: ssp@80014000 {
52
+
#address-cells = <1>;
53
+
#size-cells = <0>;
54
+
compatible = "fsl,imx28-spi";
55
+
pinctrl-names = "default";
56
+
pinctrl-0 = <&spi2_pins_a>;
57
+
status = "okay";
58
+
59
+
flash: m25p80@0 {
60
+
#address-cells = <1>;
61
+
#size-cells = <1>;
62
+
compatible = "everspin,mr25h256", "mr25h256";
63
+
spi-max-frequency = <40000000>;
64
+
reg = <0>;
65
+
};
66
+
};
67
+
};
68
+
69
+
apbx@80040000 {
70
+
i2c0: i2c@80058000 {
71
+
pinctrl-names = "default";
72
+
pinctrl-0 = <&i2c0_pins_a>;
73
+
clock-frequency = <400000>;
74
+
status = "okay";
75
+
76
+
rtc: rtc@51 {
77
+
compatible = "nxp,pcf8563";
78
+
reg = <0x51>;
79
+
};
80
+
81
+
eeprom: eeprom@52 {
82
+
compatible = "atmel,24c64";
83
+
reg = <0x52>;
84
+
pagesize = <32>;
85
+
};
86
+
};
87
+
88
+
duart: serial@80074000 {
89
+
pinctrl-names = "default";
90
+
pinctrl-0 = <&duart_pins_a>;
91
+
status = "okay";
92
+
};
93
+
94
+
usbphy0: usbphy@8007c000 {
95
+
status = "okay";
96
+
};
97
+
98
+
auart0: serial@8006a000 {
99
+
pinctrl-names = "default";
100
+
pinctrl-0 = <&auart0_pins_a>;
101
+
status = "okay";
102
+
};
103
+
};
104
+
};
105
+
106
+
ahb@80080000 {
107
+
usb0: usb@80080000 {
108
+
vbus-supply = <®_usb0_vbus>;
109
+
pinctrl-names = "default";
110
+
pinctrl-0 = <&usbphy0_pins_b>;
111
+
status = "okay";
112
+
};
113
+
114
+
mac0: ethernet@800f0000 {
115
+
phy-mode = "rmii";
116
+
pinctrl-names = "default";
117
+
pinctrl-0 = <&mac0_pins_a>;
118
+
status = "okay";
119
+
};
120
+
121
+
mac1: ethernet@800f4000 {
122
+
phy-mode = "rmii";
123
+
pinctrl-names = "default";
124
+
pinctrl-0 = <&mac1_pins_a>;
125
+
status = "okay";
126
+
};
127
+
};
128
+
129
+
regulators {
130
+
compatible = "simple-bus";
131
+
132
+
reg_usb0_vbus: usb0_vbus {
133
+
compatible = "regulator-fixed";
134
+
regulator-name = "usb0_vbus";
135
+
regulator-min-microvolt = <5000000>;
136
+
regulator-max-microvolt = <5000000>;
137
+
gpio = <&gpio3 9 0>;
138
+
};
139
+
};
140
+
141
+
leds {
142
+
#address-cells = <1>;
143
+
#size-cells = <0>;
144
+
compatible = "gpio-leds";
145
+
status = "okay";
146
+
147
+
led@1 {
148
+
label = "sps1-1:yellow:user";
149
+
gpios = <&gpio0 6 0>;
150
+
linux,default-trigger = "heartbeat";
151
+
reg = <0>;
152
+
};
153
+
154
+
led@2 {
155
+
label = "sps1-2:red:user";
156
+
gpios = <&gpio0 3 0>;
157
+
linux,default-trigger = "heartbeat";
158
+
reg = <1>;
159
+
};
160
+
161
+
led@3 {
162
+
label = "sps1-3:red:user";
163
+
gpios = <&gpio0 0 0>;
164
+
default-trigger = "heartbeat";
165
+
reg = <2>;
166
+
};
167
+
168
+
};
169
+
};
+35
arch/arm/boot/dts/imx28.dtsi
+35
arch/arm/boot/dts/imx28.dtsi
···
492
492
fsl,pull-up = <0>;
493
493
};
494
494
495
+
pwm3_pins_a: pwm3@0 {
496
+
reg = <0>;
497
+
fsl,pinmux-ids = <
498
+
0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499
+
>;
500
+
fsl,drive-strength = <0>;
501
+
fsl,voltage = <1>;
502
+
fsl,pull-up = <0>;
503
+
};
504
+
495
505
pwm4_pins_a: pwm4@0 {
496
506
reg = <0>;
497
507
fsl,pinmux-ids = <
···
539
529
0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
540
530
0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
541
531
0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
532
+
>;
533
+
fsl,drive-strength = <0>;
534
+
fsl,voltage = <1>;
535
+
fsl,pull-up = <0>;
536
+
};
537
+
538
+
lcdif_16bit_pins_a: lcdif-16bit@0 {
539
+
reg = <0>;
540
+
fsl,pinmux-ids = <
541
+
0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
542
+
0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
543
+
0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
544
+
0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
545
+
0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
546
+
0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
547
+
0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
548
+
0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
549
+
0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
550
+
0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
551
+
0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
552
+
0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
553
+
0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
554
+
0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
555
+
0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
556
+
0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
542
557
>;
543
558
fsl,drive-strength = <0>;
544
559
fsl,voltage = <1>;
+23
-20
arch/arm/boot/dts/imx51.dtsi
+23
-20
arch/arm/boot/dts/imx51.dtsi
···
83
83
reg = <0x70000000 0x40000>;
84
84
ranges;
85
85
86
-
esdhc@70004000 { /* ESDHC1 */
86
+
esdhc1: esdhc@70004000 {
87
87
compatible = "fsl,imx51-esdhc";
88
88
reg = <0x70004000 0x4000>;
89
89
interrupts = <1>;
···
92
92
status = "disabled";
93
93
};
94
94
95
-
esdhc@70008000 { /* ESDHC2 */
95
+
esdhc2: esdhc@70008000 {
96
96
compatible = "fsl,imx51-esdhc";
97
97
reg = <0x70008000 0x4000>;
98
98
interrupts = <2>;
99
99
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100
100
clock-names = "ipg", "ahb", "per";
101
+
bus-width = <4>;
101
102
status = "disabled";
102
103
};
103
104
···
111
110
status = "disabled";
112
111
};
113
112
114
-
ecspi@70010000 { /* ECSPI1 */
113
+
ecspi1: ecspi@70010000 {
115
114
#address-cells = <1>;
116
115
#size-cells = <0>;
117
116
compatible = "fsl,imx51-ecspi";
···
132
131
status = "disabled";
133
132
};
134
133
135
-
esdhc@70020000 { /* ESDHC3 */
134
+
esdhc3: esdhc@70020000 {
136
135
compatible = "fsl,imx51-esdhc";
137
136
reg = <0x70020000 0x4000>;
138
137
interrupts = <3>;
139
138
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140
139
clock-names = "ipg", "ahb", "per";
140
+
bus-width = <4>;
141
141
status = "disabled";
142
142
};
143
143
144
-
esdhc@70024000 { /* ESDHC4 */
144
+
esdhc4: esdhc@70024000 {
145
145
compatible = "fsl,imx51-esdhc";
146
146
reg = <0x70024000 0x4000>;
147
147
interrupts = <4>;
148
148
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
149
149
clock-names = "ipg", "ahb", "per";
150
+
bus-width = <4>;
150
151
status = "disabled";
151
152
};
152
153
};
153
154
154
-
usb@73f80000 {
155
+
usbotg: usb@73f80000 {
155
156
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156
157
reg = <0x73f80000 0x0200>;
157
158
interrupts = <18>;
158
159
status = "disabled";
159
160
};
160
161
161
-
usb@73f80200 {
162
+
usbh1: usb@73f80200 {
162
163
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
163
164
reg = <0x73f80200 0x0200>;
164
165
interrupts = <14>;
165
166
status = "disabled";
166
167
};
167
168
168
-
usb@73f80400 {
169
+
usbh2: usb@73f80400 {
169
170
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
170
171
reg = <0x73f80400 0x0200>;
171
172
interrupts = <16>;
172
173
status = "disabled";
173
174
};
174
175
175
-
usb@73f80600 {
176
+
usbh3: usb@73f80600 {
176
177
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
177
178
reg = <0x73f80600 0x0200>;
178
179
interrupts = <17>;
···
221
218
#interrupt-cells = <2>;
222
219
};
223
220
224
-
wdog@73f98000 { /* WDOG1 */
221
+
wdog1: wdog@73f98000 {
225
222
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
226
223
reg = <0x73f98000 0x4000>;
227
224
interrupts = <58>;
228
225
clocks = <&clks 0>;
229
226
};
230
227
231
-
wdog@73f9c000 { /* WDOG2 */
228
+
wdog2: wdog@73f9c000 {
232
229
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
233
230
reg = <0x73f9c000 0x4000>;
234
231
interrupts = <59>;
···
236
233
status = "disabled";
237
234
};
238
235
239
-
iomuxc@73fa8000 {
236
+
iomuxc: iomuxc@73fa8000 {
240
237
compatible = "fsl,imx51-iomuxc";
241
238
reg = <0x73fa8000 0x4000>;
242
239
···
463
460
reg = <0x80000000 0x10000000>;
464
461
ranges;
465
462
466
-
ecspi@83fac000 { /* ECSPI2 */
463
+
ecspi2: ecspi@83fac000 {
467
464
#address-cells = <1>;
468
465
#size-cells = <0>;
469
466
compatible = "fsl,imx51-ecspi";
···
474
471
status = "disabled";
475
472
};
476
473
477
-
sdma@83fb0000 {
474
+
sdma: sdma@83fb0000 {
478
475
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
479
476
reg = <0x83fb0000 0x4000>;
480
477
interrupts = <6>;
···
483
480
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
484
481
};
485
482
486
-
cspi@83fc0000 {
483
+
cspi: cspi@83fc0000 {
487
484
#address-cells = <1>;
488
485
#size-cells = <0>;
489
486
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
···
494
491
status = "disabled";
495
492
};
496
493
497
-
i2c@83fc4000 { /* I2C2 */
494
+
i2c2: i2c@83fc4000 {
498
495
#address-cells = <1>;
499
496
#size-cells = <0>;
500
497
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
···
504
501
status = "disabled";
505
502
};
506
503
507
-
i2c@83fc8000 { /* I2C1 */
504
+
i2c1: i2c@83fc8000 {
508
505
#address-cells = <1>;
509
506
#size-cells = <0>;
510
507
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
···
524
521
status = "disabled";
525
522
};
526
523
527
-
audmux@83fd0000 {
524
+
audmux: audmux@83fd0000 {
528
525
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
529
526
reg = <0x83fd0000 0x4000>;
530
527
status = "disabled";
531
528
};
532
529
533
-
nand@83fdb000 {
530
+
nfc: nand@83fdb000 {
534
531
compatible = "fsl,imx51-nand";
535
532
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
536
533
interrupts = <8>;
···
548
545
status = "disabled";
549
546
};
550
547
551
-
ethernet@83fec000 {
548
+
fec: ethernet@83fec000 {
552
549
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
553
550
reg = <0x83fec000 0x4000>;
554
551
interrupts = <87>;
+44
-18
arch/arm/boot/dts/imx53-qsb.dts
+44
-18
arch/arm/boot/dts/imx53-qsb.dts
···
60
60
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61
61
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62
62
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63
+
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64
+
>;
65
+
};
66
+
67
+
led_pin_gpio7_7: led_gpio7_7@0 {
68
+
fsl,pins = <
63
69
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
64
70
>;
65
71
};
66
72
};
73
+
67
74
};
68
75
69
76
uart1: serial@53fbc000 {
···
107
100
pmic: dialog@48 {
108
101
compatible = "dlg,da9053-aa", "dlg,da9052";
109
102
reg = <0x48>;
103
+
interrupt-parent = <&gpio7>;
104
+
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
110
105
111
106
regulators {
112
-
buck0 {
107
+
buck1_reg: buck1 {
113
108
regulator-min-microvolt = <500000>;
114
109
regulator-max-microvolt = <2075000>;
110
+
regulator-always-on;
115
111
};
116
112
117
-
buck1 {
113
+
buck2_reg: buck2 {
118
114
regulator-min-microvolt = <500000>;
119
115
regulator-max-microvolt = <2075000>;
116
+
regulator-always-on;
120
117
};
121
118
122
-
buck2 {
119
+
buck3_reg: buck3 {
123
120
regulator-min-microvolt = <925000>;
124
121
regulator-max-microvolt = <2500000>;
122
+
regulator-always-on;
125
123
};
126
124
127
-
buck3 {
125
+
buck4_reg: buck4 {
128
126
regulator-min-microvolt = <925000>;
129
127
regulator-max-microvolt = <2500000>;
128
+
regulator-always-on;
130
129
};
131
130
132
-
ldo4 {
131
+
ldo1_reg: ldo1 {
133
132
regulator-min-microvolt = <600000>;
134
133
regulator-max-microvolt = <1800000>;
134
+
regulator-boot-on;
135
+
regulator-always-on;
135
136
};
136
137
137
-
ldo5 {
138
+
ldo2_reg: ldo2 {
139
+
regulator-min-microvolt = <600000>;
140
+
regulator-max-microvolt = <1800000>;
141
+
regulator-always-on;
142
+
};
143
+
144
+
ldo3_reg: ldo3 {
138
145
regulator-min-microvolt = <600000>;
139
146
regulator-max-microvolt = <1800000>;
147
+
regulator-always-on;
140
148
};
141
149
142
-
ldo6 {
150
+
ldo4_reg: ldo4 {
143
151
regulator-min-microvolt = <1725000>;
144
152
regulator-max-microvolt = <3300000>;
153
+
regulator-always-on;
145
154
};
146
155
147
-
ldo7 {
156
+
ldo5_reg: ldo5 {
148
157
regulator-min-microvolt = <1725000>;
149
158
regulator-max-microvolt = <3300000>;
159
+
regulator-always-on;
150
160
};
151
161
152
-
ldo8 {
162
+
ldo6_reg: ldo6 {
153
163
regulator-min-microvolt = <1200000>;
154
164
regulator-max-microvolt = <3600000>;
165
+
regulator-always-on;
155
166
};
156
167
157
-
ldo9 {
168
+
ldo7_reg: ldo7 {
158
169
regulator-min-microvolt = <1200000>;
159
170
regulator-max-microvolt = <3600000>;
171
+
regulator-always-on;
160
172
};
161
173
162
-
ldo10 {
174
+
ldo8_reg: ldo8 {
163
175
regulator-min-microvolt = <1200000>;
164
176
regulator-max-microvolt = <3600000>;
177
+
regulator-always-on;
165
178
};
166
179
167
-
ldo11 {
180
+
ldo9_reg: ldo9 {
168
181
regulator-min-microvolt = <1200000>;
169
182
regulator-max-microvolt = <3600000>;
183
+
regulator-always-on;
170
184
};
171
185
172
-
ldo12 {
186
+
ldo10_reg: ldo10 {
173
187
regulator-min-microvolt = <1250000>;
174
188
regulator-max-microvolt = <3650000>;
175
-
};
176
-
177
-
ldo13 {
178
-
regulator-min-microvolt = <1200000>;
179
-
regulator-max-microvolt = <3600000>;
189
+
regulator-always-on;
180
190
};
181
191
};
182
192
};
···
240
216
241
217
leds {
242
218
compatible = "gpio-leds";
219
+
pinctrl-names = "default";
220
+
pinctrl-0 = <&led_pin_gpio7_7>;
243
221
244
222
user {
245
223
label = "Heartbeat";
+71
-21
arch/arm/boot/dts/imx53.dtsi
+71
-21
arch/arm/boot/dts/imx53.dtsi
···
88
88
reg = <0x50000000 0x40000>;
89
89
ranges;
90
90
91
-
esdhc@50004000 { /* ESDHC1 */
91
+
esdhc1: esdhc@50004000 {
92
92
compatible = "fsl,imx53-esdhc";
93
93
reg = <0x50004000 0x4000>;
94
94
interrupts = <1>;
95
95
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96
96
clock-names = "ipg", "ahb", "per";
97
+
bus-width = <4>;
97
98
status = "disabled";
98
99
};
99
100
100
-
esdhc@50008000 { /* ESDHC2 */
101
+
esdhc2: esdhc@50008000 {
101
102
compatible = "fsl,imx53-esdhc";
102
103
reg = <0x50008000 0x4000>;
103
104
interrupts = <2>;
104
105
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
105
106
clock-names = "ipg", "ahb", "per";
107
+
bus-width = <4>;
106
108
status = "disabled";
107
109
};
108
110
···
117
115
status = "disabled";
118
116
};
119
117
120
-
ecspi@50010000 { /* ECSPI1 */
118
+
ecspi1: ecspi@50010000 {
121
119
#address-cells = <1>;
122
120
#size-cells = <0>;
123
121
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
···
138
136
status = "disabled";
139
137
};
140
138
141
-
esdhc@50020000 { /* ESDHC3 */
139
+
esdhc3: esdhc@50020000 {
142
140
compatible = "fsl,imx53-esdhc";
143
141
reg = <0x50020000 0x4000>;
144
142
interrupts = <3>;
145
143
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146
144
clock-names = "ipg", "ahb", "per";
145
+
bus-width = <4>;
147
146
status = "disabled";
148
147
};
149
148
150
-
esdhc@50024000 { /* ESDHC4 */
149
+
esdhc4: esdhc@50024000 {
151
150
compatible = "fsl,imx53-esdhc";
152
151
reg = <0x50024000 0x4000>;
153
152
interrupts = <4>;
154
153
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
155
154
clock-names = "ipg", "ahb", "per";
155
+
bus-width = <4>;
156
156
status = "disabled";
157
157
};
158
158
};
159
159
160
-
usb@53f80000 {
160
+
usbotg: usb@53f80000 {
161
161
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
162
162
reg = <0x53f80000 0x0200>;
163
163
interrupts = <18>;
164
164
status = "disabled";
165
165
};
166
166
167
-
usb@53f80200 {
167
+
usbh1: usb@53f80200 {
168
168
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
169
169
reg = <0x53f80200 0x0200>;
170
170
interrupts = <14>;
171
171
status = "disabled";
172
172
};
173
173
174
-
usb@53f80400 {
174
+
usbh2: usb@53f80400 {
175
175
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
176
176
reg = <0x53f80400 0x0200>;
177
177
interrupts = <16>;
178
178
status = "disabled";
179
179
};
180
180
181
-
usb@53f80600 {
181
+
usbh3: usb@53f80600 {
182
182
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
183
183
reg = <0x53f80600 0x0200>;
184
184
interrupts = <17>;
···
227
223
#interrupt-cells = <2>;
228
224
};
229
225
230
-
wdog@53f98000 { /* WDOG1 */
226
+
wdog1: wdog@53f98000 {
231
227
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
232
228
reg = <0x53f98000 0x4000>;
233
229
interrupts = <58>;
234
230
clocks = <&clks 0>;
235
231
};
236
232
237
-
wdog@53f9c000 { /* WDOG2 */
233
+
wdog2: wdog@53f9c000 {
238
234
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
239
235
reg = <0x53f9c000 0x4000>;
240
236
interrupts = <59>;
···
242
238
status = "disabled";
243
239
};
244
240
245
-
iomuxc@53fa8000 {
241
+
iomuxc: iomuxc@53fa8000 {
246
242
compatible = "fsl,imx53-iomuxc";
247
243
reg = <0x53fa8000 0x4000>;
248
244
···
342
338
};
343
339
};
344
340
341
+
can1 {
342
+
pinctrl_can1_1: can1grp-1 {
343
+
fsl,pins = <
344
+
847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
345
+
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
346
+
>;
347
+
};
348
+
};
349
+
350
+
can2 {
351
+
pinctrl_can2_1: can2grp-1 {
352
+
fsl,pins = <
353
+
67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
354
+
74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
355
+
>;
356
+
};
357
+
};
358
+
345
359
i2c1 {
346
360
pinctrl_i2c1_1: i2c1grp-1 {
347
361
fsl,pins = <
···
374
352
fsl,pins = <
375
353
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
376
354
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
355
+
>;
356
+
};
357
+
};
358
+
359
+
i2c3 {
360
+
pinctrl_i2c3_1: i2c3grp-1 {
361
+
fsl,pins = <
362
+
1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
363
+
1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
377
364
>;
378
365
};
379
366
};
···
422
391
>;
423
392
};
424
393
};
394
+
395
+
uart4 {
396
+
pinctrl_uart4_1: uart4grp-1 {
397
+
fsl,pins = <
398
+
11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
399
+
18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
400
+
>;
401
+
};
402
+
};
403
+
404
+
uart5 {
405
+
pinctrl_uart5_1: uart5grp-1 {
406
+
fsl,pins = <
407
+
24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
408
+
31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
409
+
>;
410
+
};
411
+
};
412
+
425
413
};
426
414
427
415
pwm1: pwm@53fb4000 {
···
534
484
#interrupt-cells = <2>;
535
485
};
536
486
537
-
i2c@53fec000 { /* I2C3 */
487
+
i2c3: i2c@53fec000 {
538
488
#address-cells = <1>;
539
489
#size-cells = <0>;
540
490
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
···
570
520
status = "disabled";
571
521
};
572
522
573
-
ecspi@63fac000 { /* ECSPI2 */
523
+
ecspi2: ecspi@63fac000 {
574
524
#address-cells = <1>;
575
525
#size-cells = <0>;
576
526
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
···
581
531
status = "disabled";
582
532
};
583
533
584
-
sdma@63fb0000 {
534
+
sdma: sdma@63fb0000 {
585
535
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
586
536
reg = <0x63fb0000 0x4000>;
587
537
interrupts = <6>;
···
590
540
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
591
541
};
592
542
593
-
cspi@63fc0000 {
543
+
cspi: cspi@63fc0000 {
594
544
#address-cells = <1>;
595
545
#size-cells = <0>;
596
546
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
···
601
551
status = "disabled";
602
552
};
603
553
604
-
i2c@63fc4000 { /* I2C2 */
554
+
i2c2: i2c@63fc4000 {
605
555
#address-cells = <1>;
606
556
#size-cells = <0>;
607
557
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
···
611
561
status = "disabled";
612
562
};
613
563
614
-
i2c@63fc8000 { /* I2C1 */
564
+
i2c1: i2c@63fc8000 {
615
565
#address-cells = <1>;
616
566
#size-cells = <0>;
617
567
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
···
631
581
status = "disabled";
632
582
};
633
583
634
-
audmux@63fd0000 {
584
+
audmux: audmux@63fd0000 {
635
585
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
636
586
reg = <0x63fd0000 0x4000>;
637
587
status = "disabled";
638
588
};
639
589
640
-
nand@63fdb000 {
590
+
nfc: nand@63fdb000 {
641
591
compatible = "fsl,imx53-nand";
642
592
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
643
593
interrupts = <8>;
···
655
605
status = "disabled";
656
606
};
657
607
658
-
ethernet@63fec000 {
608
+
fec: ethernet@63fec000 {
659
609
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
660
610
reg = <0x63fec000 0x4000>;
661
611
interrupts = <87>;
+64
arch/arm/boot/dts/imx6q-sabreauto.dts
+64
arch/arm/boot/dts/imx6q-sabreauto.dts
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
* Copyright 2011 Linaro Ltd.
4
+
*
5
+
* The code contained herein is licensed under the GNU General Public
6
+
* License. You may obtain a copy of the GNU General Public License
7
+
* Version 2 or later at the following locations:
8
+
*
9
+
* http://www.opensource.org/licenses/gpl-license.html
10
+
* http://www.gnu.org/copyleft/gpl.html
11
+
*/
12
+
13
+
/dts-v1/;
14
+
/include/ "imx6q.dtsi"
15
+
16
+
/ {
17
+
model = "Freescale i.MX6 Quad SABRE Automotive Board";
18
+
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
+
20
+
memory {
21
+
reg = <0x10000000 0x80000000>;
22
+
};
23
+
24
+
soc {
25
+
aips-bus@02000000 { /* AIPS1 */
26
+
iomuxc@020e0000 {
27
+
pinctrl-names = "default";
28
+
pinctrl-0 = <&pinctrl_hog>;
29
+
30
+
hog {
31
+
pinctrl_hog: hoggrp {
32
+
fsl,pins = <
33
+
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34
+
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35
+
>;
36
+
};
37
+
};
38
+
};
39
+
};
40
+
41
+
aips-bus@02100000 { /* AIPS2 */
42
+
uart4: serial@021f0000 {
43
+
pinctrl-names = "default";
44
+
pinctrl-0 = <&pinctrl_uart4_1>;
45
+
status = "okay";
46
+
};
47
+
48
+
ethernet@02188000 {
49
+
pinctrl-names = "default";
50
+
pinctrl-0 = <&pinctrl_enet_2>;
51
+
phy-mode = "rgmii";
52
+
status = "okay";
53
+
};
54
+
55
+
usdhc@02198000 { /* uSDHC3 */
56
+
pinctrl-names = "default";
57
+
pinctrl-0 = <&pinctrl_usdhc3_1>;
58
+
cd-gpios = <&gpio6 15 0>;
59
+
wp-gpios = <&gpio1 13 0>;
60
+
status = "okay";
61
+
};
62
+
};
63
+
};
64
+
};
+18
arch/arm/boot/dts/imx6q-sabresd.dts
+18
arch/arm/boot/dts/imx6q-sabresd.dts
···
38
38
hog {
39
39
pinctrl_hog: hoggrp {
40
40
fsl,pins = <
41
+
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42
+
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
41
43
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
42
44
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
43
45
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
···
73
71
wp-gpios = <&gpio2 1 0>;
74
72
status = "okay";
75
73
};
74
+
};
75
+
};
76
+
77
+
gpio-keys {
78
+
compatible = "gpio-keys";
79
+
80
+
volume-up {
81
+
label = "Volume Up";
82
+
gpios = <&gpio1 4 0>;
83
+
linux,code = <115>; /* KEY_VOLUMEUP */
84
+
};
85
+
86
+
volume-down {
87
+
label = "Volume Down";
88
+
gpios = <&gpio1 5 0>;
89
+
linux,code = <114>; /* KEY_VOLUMEDOWN */
76
90
};
77
91
};
78
92
};
+67
-47
arch/arm/boot/dts/imx6q.dtsi
+67
-47
arch/arm/boot/dts/imx6q.dtsi
···
36
36
compatible = "arm,cortex-a9";
37
37
reg = <0>;
38
38
next-level-cache = <&L2>;
39
+
operating-points = <
40
+
/* kHz uV */
41
+
792000 1100000
42
+
396000 950000
43
+
198000 850000
44
+
>;
45
+
clock-latency = <61036>; /* two CLK32 periods */
46
+
cpu0-supply = <®_cpu>;
39
47
};
40
48
41
49
cpu@1 {
···
108
100
clocks = <&clks 106>;
109
101
};
110
102
111
-
gpmi-nand@00112000 {
103
+
nfc: gpmi-nand@00112000 {
112
104
compatible = "fsl,imx6q-gpmi-nand";
113
105
#address-cells = <1>;
114
106
#size-cells = <1>;
···
152
144
reg = <0x02000000 0x40000>;
153
145
ranges;
154
146
155
-
spdif@02004000 {
147
+
spdif: spdif@02004000 {
156
148
reg = <0x02004000 0x4000>;
157
149
interrupts = <0 52 0x04>;
158
150
};
159
151
160
-
ecspi@02008000 { /* eCSPI1 */
152
+
ecspi1: ecspi@02008000 {
161
153
#address-cells = <1>;
162
154
#size-cells = <0>;
163
155
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
···
168
160
status = "disabled";
169
161
};
170
162
171
-
ecspi@0200c000 { /* eCSPI2 */
163
+
ecspi2: ecspi@0200c000 {
172
164
#address-cells = <1>;
173
165
#size-cells = <0>;
174
166
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
···
179
171
status = "disabled";
180
172
};
181
173
182
-
ecspi@02010000 { /* eCSPI3 */
174
+
ecspi3: ecspi@02010000 {
183
175
#address-cells = <1>;
184
176
#size-cells = <0>;
185
177
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
···
190
182
status = "disabled";
191
183
};
192
184
193
-
ecspi@02014000 { /* eCSPI4 */
185
+
ecspi4: ecspi@02014000 {
194
186
#address-cells = <1>;
195
187
#size-cells = <0>;
196
188
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
···
201
193
status = "disabled";
202
194
};
203
195
204
-
ecspi@02018000 { /* eCSPI5 */
196
+
ecspi5: ecspi@02018000 {
205
197
#address-cells = <1>;
206
198
#size-cells = <0>;
207
199
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
···
221
213
status = "disabled";
222
214
};
223
215
224
-
esai@02024000 {
216
+
esai: esai@02024000 {
225
217
reg = <0x02024000 0x4000>;
226
218
interrupts = <0 51 0x04>;
227
219
};
···
256
248
status = "disabled";
257
249
};
258
250
259
-
asrc@02034000 {
251
+
asrc: asrc@02034000 {
260
252
reg = <0x02034000 0x4000>;
261
253
interrupts = <0 50 0x04>;
262
254
};
···
266
258
};
267
259
};
268
260
269
-
vpu@02040000 {
261
+
vpu: vpu@02040000 {
270
262
reg = <0x02040000 0x3c000>;
271
263
interrupts = <0 3 0x04 0 12 0x04>;
272
264
};
···
275
267
reg = <0x0207c000 0x4000>;
276
268
};
277
269
278
-
pwm@02080000 { /* PWM1 */
270
+
pwm1: pwm@02080000 {
279
271
#pwm-cells = <2>;
280
272
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
281
273
reg = <0x02080000 0x4000>;
···
284
276
clock-names = "ipg", "per";
285
277
};
286
278
287
-
pwm@02084000 { /* PWM2 */
279
+
pwm2: pwm@02084000 {
288
280
#pwm-cells = <2>;
289
281
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
290
282
reg = <0x02084000 0x4000>;
···
293
285
clock-names = "ipg", "per";
294
286
};
295
287
296
-
pwm@02088000 { /* PWM3 */
288
+
pwm3: pwm@02088000 {
297
289
#pwm-cells = <2>;
298
290
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
299
291
reg = <0x02088000 0x4000>;
···
302
294
clock-names = "ipg", "per";
303
295
};
304
296
305
-
pwm@0208c000 { /* PWM4 */
297
+
pwm4: pwm@0208c000 {
306
298
#pwm-cells = <2>;
307
299
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
308
300
reg = <0x0208c000 0x4000>;
···
311
303
clock-names = "ipg", "per";
312
304
};
313
305
314
-
flexcan@02090000 { /* CAN1 */
306
+
can1: flexcan@02090000 {
315
307
reg = <0x02090000 0x4000>;
316
308
interrupts = <0 110 0x04>;
317
309
};
318
310
319
-
flexcan@02094000 { /* CAN2 */
311
+
can2: flexcan@02094000 {
320
312
reg = <0x02094000 0x4000>;
321
313
interrupts = <0 111 0x04>;
322
314
};
323
315
324
-
gpt@02098000 {
316
+
gpt: gpt@02098000 {
325
317
compatible = "fsl,imx6q-gpt";
326
318
reg = <0x02098000 0x4000>;
327
319
interrupts = <0 55 0x04>;
···
397
389
#interrupt-cells = <2>;
398
390
};
399
391
400
-
kpp@020b8000 {
392
+
kpp: kpp@020b8000 {
401
393
reg = <0x020b8000 0x4000>;
402
394
interrupts = <0 82 0x04>;
403
395
};
404
396
405
-
wdog@020bc000 { /* WDOG1 */
397
+
wdog1: wdog@020bc000 {
406
398
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
407
399
reg = <0x020bc000 0x4000>;
408
400
interrupts = <0 80 0x04>;
409
401
clocks = <&clks 0>;
410
402
};
411
403
412
-
wdog@020c0000 { /* WDOG2 */
404
+
wdog2: wdog@020c0000 {
413
405
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
414
406
reg = <0x020c0000 0x4000>;
415
407
interrupts = <0 81 0x04>;
···
471
463
anatop-max-voltage = <2750000>;
472
464
};
473
465
474
-
regulator-vddcore@140 {
466
+
reg_cpu: regulator-vddcore@140 {
475
467
compatible = "fsl,anatop-regulator";
476
468
regulator-name = "cpu";
477
469
regulator-min-microvolt = <725000>;
···
529
521
};
530
522
531
523
snvs@020cc000 {
532
-
reg = <0x020cc000 0x4000>;
533
-
interrupts = <0 19 0x04 0 20 0x04>;
524
+
compatible = "fsl,sec-v4.0-mon", "simple-bus";
525
+
#address-cells = <1>;
526
+
#size-cells = <1>;
527
+
ranges = <0 0x020cc000 0x4000>;
528
+
529
+
snvs-rtc-lp@34 {
530
+
compatible = "fsl,sec-v4.0-mon-rtc-lp";
531
+
reg = <0x34 0x58>;
532
+
interrupts = <0 19 0x04 0 20 0x04>;
533
+
};
534
534
};
535
535
536
-
epit@020d0000 { /* EPIT1 */
536
+
epit1: epit@020d0000 { /* EPIT1 */
537
537
reg = <0x020d0000 0x4000>;
538
538
interrupts = <0 56 0x04>;
539
539
};
540
540
541
-
epit@020d4000 { /* EPIT2 */
541
+
epit2: epit@020d4000 { /* EPIT2 */
542
542
reg = <0x020d4000 0x4000>;
543
543
interrupts = <0 57 0x04>;
544
544
};
545
545
546
-
src@020d8000 {
546
+
src: src@020d8000 {
547
547
compatible = "fsl,imx6q-src";
548
548
reg = <0x020d8000 0x4000>;
549
549
interrupts = <0 91 0x04 0 96 0x04>;
550
550
};
551
551
552
-
gpc@020dc000 {
552
+
gpc: gpc@020dc000 {
553
553
compatible = "fsl,imx6q-gpc";
554
554
reg = <0x020dc000 0x4000>;
555
555
interrupts = <0 89 0x04 0 90 0x04>;
···
568
552
reg = <0x020e0000 0x38>;
569
553
};
570
554
571
-
iomuxc@020e0000 {
555
+
iomuxc: iomuxc@020e0000 {
572
556
compatible = "fsl,imx6q-iomuxc";
573
557
reg = <0x020e0000 0x4000>;
574
558
···
781
765
};
782
766
};
783
767
784
-
dcic@020e4000 { /* DCIC1 */
768
+
dcic1: dcic@020e4000 {
785
769
reg = <0x020e4000 0x4000>;
786
770
interrupts = <0 124 0x04>;
787
771
};
788
772
789
-
dcic@020e8000 { /* DCIC2 */
773
+
dcic2: dcic@020e8000 {
790
774
reg = <0x020e8000 0x4000>;
791
775
interrupts = <0 125 0x04>;
792
776
};
793
777
794
-
sdma@020ec000 {
778
+
sdma: sdma@020ec000 {
795
779
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
796
780
reg = <0x020ec000 0x4000>;
797
781
interrupts = <0 2 0x04>;
···
817
801
reg = <0x0217c000 0x4000>;
818
802
};
819
803
820
-
usb@02184000 { /* USB OTG */
804
+
usbotg: usb@02184000 {
821
805
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
822
806
reg = <0x02184000 0x200>;
823
807
interrupts = <0 43 0x04>;
···
827
811
status = "disabled";
828
812
};
829
813
830
-
usb@02184200 { /* USB1 */
814
+
usbh1: usb@02184200 {
831
815
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
832
816
reg = <0x02184200 0x200>;
833
817
interrupts = <0 40 0x04>;
···
837
821
status = "disabled";
838
822
};
839
823
840
-
usb@02184400 { /* USB2 */
824
+
usbh2: usb@02184400 {
841
825
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
842
826
reg = <0x02184400 0x200>;
843
827
interrupts = <0 41 0x04>;
···
846
830
status = "disabled";
847
831
};
848
832
849
-
usb@02184600 { /* USB3 */
833
+
usbh3: usb@02184600 {
850
834
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
851
835
reg = <0x02184600 0x200>;
852
836
interrupts = <0 42 0x04>;
···
855
839
status = "disabled";
856
840
};
857
841
858
-
usbmisc: usbmisc@02184800 {
842
+
usbmisc: usbmisc: usbmisc@02184800 {
859
843
#index-cells = <1>;
860
844
compatible = "fsl,imx6q-usbmisc";
861
845
reg = <0x02184800 0x200>;
862
846
clocks = <&clks 162>;
863
847
};
864
848
865
-
ethernet@02188000 {
849
+
fec: ethernet@02188000 {
866
850
compatible = "fsl,imx6q-fec";
867
851
reg = <0x02188000 0x4000>;
868
852
interrupts = <0 118 0x04 0 119 0x04>;
···
876
860
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
877
861
};
878
862
879
-
usdhc@02190000 { /* uSDHC1 */
863
+
usdhc1: usdhc@02190000 {
880
864
compatible = "fsl,imx6q-usdhc";
881
865
reg = <0x02190000 0x4000>;
882
866
interrupts = <0 22 0x04>;
883
867
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
884
868
clock-names = "ipg", "ahb", "per";
869
+
bus-width = <4>;
885
870
status = "disabled";
886
871
};
887
872
888
-
usdhc@02194000 { /* uSDHC2 */
873
+
usdhc2: usdhc@02194000 {
889
874
compatible = "fsl,imx6q-usdhc";
890
875
reg = <0x02194000 0x4000>;
891
876
interrupts = <0 23 0x04>;
892
877
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
893
878
clock-names = "ipg", "ahb", "per";
879
+
bus-width = <4>;
894
880
status = "disabled";
895
881
};
896
882
897
-
usdhc@02198000 { /* uSDHC3 */
883
+
usdhc3: usdhc@02198000 {
898
884
compatible = "fsl,imx6q-usdhc";
899
885
reg = <0x02198000 0x4000>;
900
886
interrupts = <0 24 0x04>;
901
887
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
902
888
clock-names = "ipg", "ahb", "per";
889
+
bus-width = <4>;
903
890
status = "disabled";
904
891
};
905
892
906
-
usdhc@0219c000 { /* uSDHC4 */
893
+
usdhc4: usdhc@0219c000 {
907
894
compatible = "fsl,imx6q-usdhc";
908
895
reg = <0x0219c000 0x4000>;
909
896
interrupts = <0 25 0x04>;
910
897
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
911
898
clock-names = "ipg", "ahb", "per";
899
+
bus-width = <4>;
912
900
status = "disabled";
913
901
};
914
902
915
-
i2c@021a0000 { /* I2C1 */
903
+
i2c1: i2c@021a0000 {
916
904
#address-cells = <1>;
917
905
#size-cells = <0>;
918
906
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
···
926
906
status = "disabled";
927
907
};
928
908
929
-
i2c@021a4000 { /* I2C2 */
909
+
i2c2: i2c@021a4000 {
930
910
#address-cells = <1>;
931
911
#size-cells = <0>;
932
912
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
···
936
916
status = "disabled";
937
917
};
938
918
939
-
i2c@021a8000 { /* I2C3 */
919
+
i2c3: i2c@021a8000 {
940
920
#address-cells = <1>;
941
921
#size-cells = <0>;
942
922
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
···
950
930
reg = <0x021ac000 0x4000>;
951
931
};
952
932
953
-
mmdc@021b0000 { /* MMDC0 */
933
+
mmdc0: mmdc@021b0000 { /* MMDC0 */
954
934
compatible = "fsl,imx6q-mmdc";
955
935
reg = <0x021b0000 0x4000>;
956
936
};
957
937
958
-
mmdc@021b4000 { /* MMDC1 */
938
+
mmdc1: mmdc@021b4000 { /* MMDC1 */
959
939
reg = <0x021b4000 0x4000>;
960
940
};
961
941
···
983
963
interrupts = <0 109 0x04>;
984
964
};
985
965
986
-
audmux@021d8000 {
966
+
audmux: audmux@021d8000 {
987
967
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
988
968
reg = <0x021d8000 0x4000>;
989
969
status = "disabled";
+44
arch/arm/boot/dts/kirkwood-6281.dtsi
+44
arch/arm/boot/dts/kirkwood-6281.dtsi
···
1
+
/ {
2
+
ocp@f1000000 {
3
+
pinctrl: pinctrl@10000 {
4
+
compatible = "marvell,88f6281-pinctrl";
5
+
reg = <0x10000 0x20>;
6
+
7
+
pmx_nand: pmx-nand {
8
+
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9
+
"mpp4", "mpp5", "mpp18",
10
+
"mpp19";
11
+
marvell,function = "nand";
12
+
};
13
+
pmx_sata0: pmx-sata0 {
14
+
marvell,pins = "mpp5", "mpp21", "mpp23";
15
+
marvell,function = "sata0";
16
+
};
17
+
pmx_sata1: pmx-sata1 {
18
+
marvell,pins = "mpp4", "mpp20", "mpp22";
19
+
marvell,function = "sata1";
20
+
};
21
+
pmx_spi: pmx-spi {
22
+
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
23
+
marvell,function = "spi";
24
+
};
25
+
pmx_twsi0: pmx-twsi0 {
26
+
marvell,pins = "mpp8", "mpp9";
27
+
marvell,function = "twsi0";
28
+
};
29
+
pmx_uart0: pmx-uart0 {
30
+
marvell,pins = "mpp10", "mpp11";
31
+
marvell,function = "uart0";
32
+
};
33
+
pmx_uart1: pmx-uart1 {
34
+
marvell,pins = "mpp13", "mpp14";
35
+
marvell,function = "uart1";
36
+
};
37
+
pmx_sdio: pmx-sdio {
38
+
marvell,pins = "mpp12", "mpp13", "mpp14",
39
+
"mpp15", "mpp16", "mpp17";
40
+
marvell,function = "sdio";
41
+
};
42
+
};
43
+
};
44
+
};
+45
arch/arm/boot/dts/kirkwood-6282.dtsi
+45
arch/arm/boot/dts/kirkwood-6282.dtsi
···
1
+
/ {
2
+
ocp@f1000000 {
3
+
4
+
pinctrl: pinctrl@10000 {
5
+
compatible = "marvell,88f6282-pinctrl";
6
+
reg = <0x10000 0x20>;
7
+
8
+
pmx_sata0: pmx-sata0 {
9
+
marvell,pins = "mpp5", "mpp21", "mpp23";
10
+
marvell,function = "sata0";
11
+
};
12
+
pmx_sata1: pmx-sata1 {
13
+
marvell,pins = "mpp4", "mpp20", "mpp22";
14
+
marvell,function = "sata1";
15
+
};
16
+
pmx_spi: pmx-spi {
17
+
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
18
+
marvell,function = "spi";
19
+
};
20
+
pmx_twsi0: pmx-twsi0 {
21
+
marvell,pins = "mpp8", "mpp9";
22
+
marvell,function = "twsi0";
23
+
};
24
+
pmx_uart0: pmx-uart0 {
25
+
marvell,pins = "mpp10", "mpp11";
26
+
marvell,function = "uart0";
27
+
};
28
+
29
+
pmx_uart1: pmx-uart1 {
30
+
marvell,pins = "mpp13", "mpp14";
31
+
marvell,function = "uart1";
32
+
};
33
+
};
34
+
35
+
i2c@11100 {
36
+
compatible = "marvell,mv64xxx-i2c";
37
+
reg = <0x11100 0x20>;
38
+
#address-cells = <1>;
39
+
#size-cells = <0>;
40
+
interrupts = <32>;
41
+
clock-frequency = <100000>;
42
+
status = "disabled";
43
+
};
44
+
};
45
+
};
+31
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
+31
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
···
1
+
/ {
2
+
ocp@f1000000 {
3
+
pinctrl: pinctrl@10000 {
4
+
compatible = "marvell,98dx4122-pinctrl";
5
+
reg = <0x10000 0x20>;
6
+
7
+
pmx_nand: pmx-nand {
8
+
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9
+
"mpp4", "mpp5", "mpp18",
10
+
"mpp19";
11
+
marvell,function = "nand";
12
+
};
13
+
pmx_spi: pmx-spi {
14
+
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
15
+
marvell,function = "spi";
16
+
};
17
+
pmx_twsi0: pmx-twsi0 {
18
+
marvell,pins = "mpp8", "mpp9";
19
+
marvell,function = "twsi0";
20
+
};
21
+
pmx_uart0: pmx-uart0 {
22
+
marvell,pins = "mpp10", "mpp11";
23
+
marvell,function = "uart0";
24
+
};
25
+
pmx_uart1: pmx-uart1 {
26
+
marvell,pins = "mpp13", "mpp14";
27
+
marvell,function = "uart1";
28
+
};
29
+
};
30
+
};
31
+
};
+140
arch/arm/boot/dts/kirkwood-dnskw.dtsi
+140
arch/arm/boot/dts/kirkwood-dnskw.dtsi
···
1
1
/include/ "kirkwood.dtsi"
2
+
/include/ "kirkwood-6281.dtsi"
2
3
3
4
/ {
4
5
model = "D-Link DNS NASes (kirkwood-based)";
···
36
35
6000 2>;
37
36
};
38
37
38
+
gpio_poweroff {
39
+
compatible = "gpio-poweroff";
40
+
gpios = <&gpio1 4 0>;
41
+
};
42
+
39
43
ocp@f1000000 {
44
+
pinctrl: pinctrl@10000 {
45
+
46
+
pinctrl-0 = < &pmx_nand &pmx_uart1
47
+
&pmx_sata0 &pmx_sata1
48
+
&pmx_led_power
49
+
&pmx_led_red_right_hdd
50
+
&pmx_led_red_left_hdd
51
+
&pmx_led_red_usb_325
52
+
&pmx_button_power
53
+
&pmx_led_red_usb_320
54
+
&pmx_power_off &pmx_power_back_on
55
+
&pmx_power_sata0 &pmx_power_sata1
56
+
&pmx_present_sata0 &pmx_present_sata1
57
+
&pmx_led_white_usb &pmx_fan_tacho
58
+
&pmx_fan_high_speed &pmx_fan_low_speed
59
+
&pmx_button_unmount &pmx_button_reset
60
+
&pmx_temp_alarm >;
61
+
pinctrl-names = "default";
62
+
63
+
pmx_sata0: pmx-sata0 {
64
+
marvell,pins = "mpp20";
65
+
marvell,function = "sata1";
66
+
};
67
+
pmx_sata1: pmx-sata1 {
68
+
marvell,pins = "mpp21";
69
+
marvell,function = "sata0";
70
+
};
71
+
pmx_led_power: pmx-led-power {
72
+
marvell,pins = "mpp26";
73
+
marvell,function = "gpio";
74
+
};
75
+
pmx_led_red_right_hdd: pmx-led-red-right-hdd {
76
+
marvell,pins = "mpp27";
77
+
marvell,function = "gpio";
78
+
};
79
+
pmx_led_red_left_hdd: pmx-led-red-left-hdd {
80
+
marvell,pins = "mpp28";
81
+
marvell,function = "gpio";
82
+
};
83
+
pmx_led_red_usb_325: pmx-led-red-usb-325 {
84
+
marvell,pins = "mpp29";
85
+
marvell,function = "gpio";
86
+
};
87
+
pmx_button_power: pmx-button-power {
88
+
marvell,pins = "mpp34";
89
+
marvell,function = "gpio";
90
+
};
91
+
pmx_led_red_usb_320: pmx-led-red-usb-320 {
92
+
marvell,pins = "mpp35";
93
+
marvell,function = "gpio";
94
+
};
95
+
pmx_power_off: pmx-power-off {
96
+
marvell,pins = "mpp36";
97
+
marvell,function = "gpio";
98
+
};
99
+
pmx_power_back_on: pmx-power-back-on {
100
+
marvell,pins = "mpp37";
101
+
marvell,function = "gpio";
102
+
};
103
+
pmx_power_sata0: pmx-power-sata0 {
104
+
marvell,pins = "mpp39";
105
+
marvell,function = "gpio";
106
+
};
107
+
pmx_power_sata1: pmx-power-sata1 {
108
+
marvell,pins = "mpp40";
109
+
marvell,function = "gpio";
110
+
};
111
+
pmx_present_sata0: pmx-present-sata0 {
112
+
marvell,pins = "mpp41";
113
+
marvell,function = "gpio";
114
+
};
115
+
pmx_present_sata1: pmx-present-sata1 {
116
+
marvell,pins = "mpp42";
117
+
marvell,function = "gpio";
118
+
};
119
+
pmx_led_white_usb: pmx-led-white-usb {
120
+
marvell,pins = "mpp43";
121
+
marvell,function = "gpio";
122
+
};
123
+
pmx_fan_tacho: pmx-fan-tacho {
124
+
marvell,pins = "mpp44";
125
+
marvell,function = "gpio";
126
+
};
127
+
pmx_fan_high_speed: pmx-fan-high-speed {
128
+
marvell,pins = "mpp45";
129
+
marvell,function = "gpio";
130
+
};
131
+
pmx_fan_low_speed: pmx-fan-low-speed {
132
+
marvell,pins = "mpp46";
133
+
marvell,function = "gpio";
134
+
};
135
+
pmx_button_unmount: pmx-button-unmount {
136
+
marvell,pins = "mpp47";
137
+
marvell,function = "gpio";
138
+
};
139
+
pmx_button_reset: pmx-button-reset {
140
+
marvell,pins = "mpp48";
141
+
marvell,function = "gpio";
142
+
};
143
+
pmx_temp_alarm: pmx-temp-alarm {
144
+
marvell,pins = "mpp49";
145
+
marvell,function = "gpio";
146
+
};
147
+
};
40
148
sata@80000 {
41
149
status = "okay";
42
150
nr-ports = <2>;
···
153
43
154
44
nand@3000000 {
155
45
status = "okay";
46
+
chip-delay = <35>;
156
47
157
48
partition@0 {
158
49
label = "u-boot";
···
185
74
label = "config";
186
75
reg = <0x7b00000 0x500000>;
187
76
};
77
+
};
78
+
};
79
+
80
+
regulators {
81
+
compatible = "simple-bus";
82
+
#address-cells = <1>;
83
+
#size-cells = <0>;
84
+
85
+
sata0_power: regulator@1 {
86
+
compatible = "regulator-fixed";
87
+
reg = <1>;
88
+
regulator-name = "SATA0 Power";
89
+
regulator-min-microvolt = <5000000>;
90
+
regulator-max-microvolt = <5000000>;
91
+
enable-active-high;
92
+
regulator-always-on;
93
+
regulator-boot-on;
94
+
gpio = <&gpio1 7 0>;
95
+
};
96
+
sata1_power: regulator@2 {
97
+
compatible = "regulator-fixed";
98
+
reg = <2>;
99
+
regulator-name = "SATA1 Power";
100
+
regulator-min-microvolt = <5000000>;
101
+
regulator-max-microvolt = <5000000>;
102
+
enable-active-high;
103
+
regulator-always-on;
104
+
regulator-boot-on;
105
+
gpio = <&gpio1 8 0>;
188
106
};
189
107
};
190
108
};
+37
arch/arm/boot/dts/kirkwood-dockstar.dts
+37
arch/arm/boot/dts/kirkwood-dockstar.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "Seagate FreeAgent Dockstar";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_usb_power_enable
22
+
&pmx_led_green &pmx_led_orange >;
23
+
pinctrl-names = "default";
24
+
25
+
pmx_usb_power_enable: pmx-usb-power-enable {
26
+
marvell,pins = "mpp29";
27
+
marvell,function = "gpio";
28
+
};
29
+
pmx_led_green: pmx-led-green {
30
+
marvell,pins = "mpp46";
31
+
marvell,function = "gpio";
32
+
};
33
+
pmx_led_orange: pmx-led-orange {
34
+
marvell,pins = "mpp47";
35
+
marvell,function = "gpio";
36
+
};
37
+
};
20
38
serial@12000 {
21
39
clock-frequency = <200000000>;
22
40
status = "ok";
···
72
52
fault {
73
53
label = "status:orange:fault";
74
54
gpios = <&gpio1 15 1>;
55
+
};
56
+
};
57
+
regulators {
58
+
compatible = "simple-bus";
59
+
#address-cells = <1>;
60
+
#size-cells = <0>;
61
+
62
+
usb_power: regulator@1 {
63
+
compatible = "regulator-fixed";
64
+
reg = <1>;
65
+
regulator-name = "USB Power";
66
+
regulator-min-microvolt = <5000000>;
67
+
regulator-max-microvolt = <5000000>;
68
+
enable-active-high;
69
+
regulator-always-on;
70
+
regulator-boot-on;
71
+
gpio = <&gpio0 29 0>;
75
72
};
76
73
};
77
74
};
+21
arch/arm/boot/dts/kirkwood-dreamplug.dts
+21
arch/arm/boot/dts/kirkwood-dreamplug.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "Globalscale Technologies Dreamplug";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_spi
22
+
&pmx_led_bluetooth &pmx_led_wifi
23
+
&pmx_led_wifi_ap >;
24
+
pinctrl-names = "default";
25
+
26
+
pmx_led_bluetooth: pmx-led-bluetooth {
27
+
marvell,pins = "mpp47";
28
+
marvell,function = "gpio";
29
+
};
30
+
pmx_led_wifi: pmx-led-wifi {
31
+
marvell,pins = "mpp48";
32
+
marvell,function = "gpio";
33
+
};
34
+
pmx_led_wifi_ap: pmx-led-wifi-ap {
35
+
marvell,pins = "mpp49";
36
+
marvell,function = "gpio";
37
+
};
38
+
};
20
39
serial@12000 {
21
40
clock-frequency = <200000000>;
22
41
status = "ok";
+73
arch/arm/boot/dts/kirkwood-goflexnet.dts
+73
arch/arm/boot/dts/kirkwood-goflexnet.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "Seagate GoFlex Net";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
22
+
&pmx_led_left_cap_0 &pmx_led_left_cap_1
23
+
&pmx_led_left_cap_2 &pmx_led_left_cap_3
24
+
&pmx_led_right_cap_0 &pmx_led_right_cap_1
25
+
&pmx_led_right_cap_2 &pmx_led_right_cap_3
26
+
>;
27
+
pinctrl-names = "default";
28
+
29
+
pmx_usb_power_enable: pmx-usb-power-enable {
30
+
marvell,pins = "mpp29";
31
+
marvell,function = "gpio";
32
+
};
33
+
pmx_led_right_cap_0: pmx-led_right_cap_0 {
34
+
marvell,pins = "mpp38";
35
+
marvell,function = "gpio";
36
+
};
37
+
pmx_led_right_cap_1: pmx-led_right_cap_1 {
38
+
marvell,pins = "mpp39";
39
+
marvell,function = "gpio";
40
+
};
41
+
pmx_led_right_cap_2: pmx-led_right_cap_2 {
42
+
marvell,pins = "mpp40";
43
+
marvell,function = "gpio";
44
+
};
45
+
pmx_led_right_cap_3: pmx-led_right_cap_3 {
46
+
marvell,pins = "mpp41";
47
+
marvell,function = "gpio";
48
+
};
49
+
pmx_led_left_cap_0: pmx-led_left_cap_0 {
50
+
marvell,pins = "mpp42";
51
+
marvell,function = "gpio";
52
+
};
53
+
pmx_led_left_cap_1: pmx-led_left_cap_1 {
54
+
marvell,pins = "mpp43";
55
+
marvell,function = "gpio";
56
+
};
57
+
pmx_led_left_cap_2: pmx-led_left_cap_2 {
58
+
marvell,pins = "mpp44";
59
+
marvell,function = "gpio";
60
+
};
61
+
pmx_led_left_cap_3: pmx-led_left_cap_3 {
62
+
marvell,pins = "mpp45";
63
+
marvell,function = "gpio";
64
+
};
65
+
pmx_led_green: pmx-led_green {
66
+
marvell,pins = "mpp46";
67
+
marvell,function = "gpio";
68
+
};
69
+
pmx_led_orange: pmx-led_orange {
70
+
marvell,pins = "mpp47";
71
+
marvell,function = "gpio";
72
+
};
73
+
};
20
74
serial@12000 {
21
75
clock-frequency = <200000000>;
22
76
status = "ok";
···
150
94
right3 {
151
95
label = "status:white:right3";
152
96
gpios = <&gpio1 9 0>;
97
+
};
98
+
};
99
+
regulators {
100
+
compatible = "simple-bus";
101
+
#address-cells = <1>;
102
+
#size-cells = <0>;
103
+
104
+
usb_power: regulator@1 {
105
+
compatible = "regulator-fixed";
106
+
reg = <1>;
107
+
regulator-name = "USB Power";
108
+
regulator-min-microvolt = <5000000>;
109
+
regulator-max-microvolt = <5000000>;
110
+
enable-active-high;
111
+
regulator-always-on;
112
+
regulator-boot-on;
113
+
gpio = <&gpio0 29 0>;
153
114
};
154
115
};
155
116
};
+40
arch/arm/boot/dts/kirkwood-ib62x0.dts
+40
arch/arm/boot/dts/kirkwood-ib62x0.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_nand
22
+
&pmx_led_os_red &pmx_power_off
23
+
&pmx_led_os_green &pmx_led_usb_transfer
24
+
&pmx_button_reset &pmx_button_usb_copy >;
25
+
pinctrl-names = "default";
26
+
27
+
pmx_led_os_red: pmx-led-os-red {
28
+
marvell,pins = "mpp22";
29
+
marvell,function = "gpio";
30
+
};
31
+
pmx_power_off: pmx-power-off {
32
+
marvell,pins = "mpp24";
33
+
marvell,function = "gpio";
34
+
};
35
+
pmx_led_os_green: pmx-led-os-green {
36
+
marvell,pins = "mpp25";
37
+
marvell,function = "gpio";
38
+
};
39
+
pmx_led_usb_transfer: pmx-led-usb-transfer {
40
+
marvell,pins = "mpp27";
41
+
marvell,function = "gpio";
42
+
};
43
+
pmx_button_reset: pmx-button-reset {
44
+
marvell,pins = "mpp28";
45
+
marvell,function = "gpio";
46
+
};
47
+
pmx_button_usb_copy: pmx-button-usb-copy {
48
+
marvell,pins = "mpp29";
49
+
marvell,function = "gpio";
50
+
};
51
+
};
20
52
serial@12000 {
21
53
clock-frequency = <200000000>;
22
54
status = "okay";
···
113
79
gpios = <&gpio0 27 0>;
114
80
};
115
81
};
82
+
gpio_poweroff {
83
+
compatible = "gpio-poweroff";
84
+
gpios = <&gpio0 24 0>;
85
+
};
86
+
87
+
116
88
};
+51
arch/arm/boot/dts/kirkwood-iconnect.dts
+51
arch/arm/boot/dts/kirkwood-iconnect.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "Iomega Iconnect";
···
19
18
};
20
19
21
20
ocp@f1000000 {
21
+
pinctrl: pinctrl@10000 {
22
+
23
+
pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
24
+
&pmx_gpio_41 &pmx_gpio_42
25
+
&pmx_gpio_43 &pmx_gpio_44
26
+
&pmx_gpio_45 &pmx_gpio_46
27
+
&pmx_gpio_47 &pmx_gpio_48 >;
28
+
pinctrl-names = "default";
29
+
30
+
pmx_gpio_12: pmx-gpio-12 {
31
+
marvell,pins = "mpp12";
32
+
marvell,function = "gpio";
33
+
};
34
+
pmx_gpio_35: pmx-gpio-35 {
35
+
marvell,pins = "mpp35";
36
+
marvell,function = "gpio";
37
+
};
38
+
pmx_gpio_41: pmx-gpio-41 {
39
+
marvell,pins = "mpp41";
40
+
marvell,function = "gpio";
41
+
};
42
+
pmx_gpio_42: pmx-gpio-42 {
43
+
marvell,pins = "mpp42";
44
+
marvell,function = "gpio";
45
+
};
46
+
pmx_gpio_43: pmx-gpio-43 {
47
+
marvell,pins = "mpp43";
48
+
marvell,function = "gpio";
49
+
};
50
+
pmx_gpio_44: pmx-gpio-44 {
51
+
marvell,pins = "mpp44";
52
+
marvell,function = "gpio";
53
+
};
54
+
pmx_gpio_45: pmx-gpio-45 {
55
+
marvell,pins = "mpp45";
56
+
marvell,function = "gpio";
57
+
};
58
+
pmx_gpio_46: pmx-gpio-46 {
59
+
marvell,pins = "mpp46";
60
+
marvell,function = "gpio";
61
+
};
62
+
pmx_gpio_47: pmx-gpio-47 {
63
+
marvell,pins = "mpp47";
64
+
marvell,function = "gpio";
65
+
};
66
+
pmx_gpio_48: pmx-gpio-48 {
67
+
marvell,pins = "mpp48";
68
+
marvell,function = "gpio";
69
+
};
70
+
};
22
71
i2c@11000 {
23
72
status = "okay";
24
73
+89
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+89
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "Iomega StorCenter ix2-200";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_button_reset &pmx_button_power
22
+
&pmx_led_backup &pmx_led_power
23
+
&pmx_button_otb &pmx_led_rebuild
24
+
&pmx_led_health
25
+
&pmx_led_sata_brt_ctrl_1
26
+
&pmx_led_sata_brt_ctrl_2
27
+
&pmx_led_backup_brt_ctrl_1
28
+
&pmx_led_backup_brt_ctrl_2
29
+
&pmx_led_power_brt_ctrl_1
30
+
&pmx_led_power_brt_ctrl_2
31
+
&pmx_led_health_brt_ctrl_1
32
+
&pmx_led_health_brt_ctrl_2
33
+
&pmx_led_rebuild_brt_ctrl_1
34
+
&pmx_led_rebuild_brt_ctrl_2 >;
35
+
pinctrl-names = "default";
36
+
37
+
pmx_button_reset: pmx-button-reset {
38
+
marvell,pins = "mpp12";
39
+
marvell,function = "gpio";
40
+
};
41
+
pmx_button_power: pmx-button-power {
42
+
marvell,pins = "mpp14";
43
+
marvell,function = "gpio";
44
+
};
45
+
pmx_led_backup: pmx-led-backup {
46
+
marvell,pins = "mpp15";
47
+
marvell,function = "gpio";
48
+
};
49
+
pmx_led_power: pmx-led-power {
50
+
marvell,pins = "mpp16";
51
+
marvell,function = "gpio";
52
+
};
53
+
pmx_button_otb: pmx-button-otb {
54
+
marvell,pins = "mpp35";
55
+
marvell,function = "gpio";
56
+
};
57
+
pmx_led_rebuild: pmx-led-rebuild {
58
+
marvell,pins = "mpp36";
59
+
marvell,function = "gpio";
60
+
};
61
+
pmx_led_health: pmx-led_health {
62
+
marvell,pins = "mpp37";
63
+
marvell,function = "gpio";
64
+
};
65
+
pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
66
+
marvell,pins = "mpp38";
67
+
marvell,function = "gpio";
68
+
};
69
+
pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
70
+
marvell,pins = "mpp39";
71
+
marvell,function = "gpio";
72
+
};
73
+
pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
74
+
marvell,pins = "mpp40";
75
+
marvell,function = "gpio";
76
+
};
77
+
pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
78
+
marvell,pins = "mpp41";
79
+
marvell,function = "gpio";
80
+
};
81
+
pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
82
+
marvell,pins = "mpp42";
83
+
marvell,function = "gpio";
84
+
};
85
+
pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
86
+
marvell,pins = "mpp43";
87
+
marvell,function = "gpio";
88
+
};
89
+
pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
90
+
marvell,pins = "mpp44";
91
+
marvell,function = "gpio";
92
+
};
93
+
pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
94
+
marvell,pins = "mpp45";
95
+
marvell,function = "gpio";
96
+
};
97
+
pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
98
+
marvell,pins = "mpp44";
99
+
marvell,function = "gpio";
100
+
};
101
+
pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
102
+
marvell,pins = "mpp45";
103
+
marvell,function = "gpio";
104
+
};
105
+
106
+
};
20
107
i2c@11000 {
21
108
status = "okay";
22
109
+17
arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+17
arch/arm/boot/dts/kirkwood-km_kirkwood.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-98dx4122.dtsi"
4
5
5
6
/ {
6
7
model = "Keymile Kirkwood Reference Design";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
22
+
&pmx_i2c_gpio_scl >;
23
+
pinctrl-names = "default";
24
+
25
+
pmx_i2c_gpio_sda: pmx-gpio-sda {
26
+
marvell,pins = "mpp8";
27
+
marvell,function = "gpio";
28
+
};
29
+
pmx_i2c_gpio_scl: pmx-gpio-scl {
30
+
marvell,pins = "mpp9";
31
+
marvell,function = "gpio";
32
+
};
33
+
};
34
+
20
35
serial@12000 {
21
36
clock-frequency = <200000000>;
22
37
status = "ok";
+95
arch/arm/boot/dts/kirkwood-lsxl.dtsi
+95
arch/arm/boot/dts/kirkwood-lsxl.dtsi
···
1
1
/include/ "kirkwood.dtsi"
2
+
/include/ "kirkwood-6281.dtsi"
2
3
3
4
/ {
4
5
chosen {
···
7
6
};
8
7
9
8
ocp@f1000000 {
9
+
pinctrl: pinctrl@10000 {
10
+
11
+
pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
12
+
&pmx_fan_low &pmx_fan_high
13
+
&pmx_led_function_red &pmx_led_alarm
14
+
&pmx_led_info &pmx_led_power
15
+
&pmx_fan_lock &pmx_button_function
16
+
&pmx_power_switch &pmx_power_auto_switch
17
+
&pmx_led_function_blue >;
18
+
pinctrl-names = "default";
19
+
20
+
pmx_power_hdd: pmx-power-hdd {
21
+
marvell,pins = "mpp10";
22
+
marvell,function = "gpo";
23
+
};
24
+
pmx_usb_vbus: pmx-usb-vbus {
25
+
marvell,pins = "mpp11";
26
+
marvell,function = "gpio";
27
+
};
28
+
pmx_fan_high: pmx-fan-high {
29
+
marvell,pins = "mpp18";
30
+
marvell,function = "gpo";
31
+
};
32
+
pmx_fan_low: pmx-fan-low {
33
+
marvell,pins = "mpp19";
34
+
marvell,function = "gpo";
35
+
};
36
+
pmx_led_function_blue: pmx-led-function-blue {
37
+
marvell,pins = "mpp36";
38
+
marvell,function = "gpio";
39
+
};
40
+
pmx_led_alarm: pmx-led-alarm {
41
+
marvell,pins = "mpp37";
42
+
marvell,function = "gpio";
43
+
};
44
+
pmx_led_info: pmx-led-info {
45
+
marvell,pins = "mpp38";
46
+
marvell,function = "gpio";
47
+
};
48
+
pmx_led_power: pmx-led-power {
49
+
marvell,pins = "mpp39";
50
+
marvell,function = "gpio";
51
+
};
52
+
pmx_fan_lock: pmx-fan-lock {
53
+
marvell,pins = "mpp40";
54
+
marvell,function = "gpio";
55
+
};
56
+
pmx_button_function: pmx-button-function {
57
+
marvell,pins = "mpp41";
58
+
marvell,function = "gpio";
59
+
};
60
+
pmx_power_switch: pmx-power-switch {
61
+
marvell,pins = "mpp42";
62
+
marvell,function = "gpio";
63
+
};
64
+
pmx_power_auto_switch: pmx-power-auto-switch {
65
+
marvell,pins = "mpp43";
66
+
marvell,function = "gpio";
67
+
};
68
+
pmx_led_function_red: pmx-led-function_red {
69
+
marvell,pins = "mpp48";
70
+
marvell,function = "gpio";
71
+
};
72
+
73
+
};
10
74
sata@80000 {
11
75
status = "okay";
12
76
nr-ports = <1>;
···
170
104
3250 1
171
105
5000 0>;
172
106
alarm-gpios = <&gpio1 8 0>;
107
+
};
108
+
109
+
regulators {
110
+
compatible = "simple-bus";
111
+
#address-cells = <1>;
112
+
#size-cells = <0>;
113
+
114
+
usb_power: regulator@1 {
115
+
compatible = "regulator-fixed";
116
+
reg = <1>;
117
+
regulator-name = "USB Power";
118
+
regulator-min-microvolt = <5000000>;
119
+
regulator-max-microvolt = <5000000>;
120
+
enable-active-high;
121
+
regulator-always-on;
122
+
regulator-boot-on;
123
+
gpio = <&gpio0 11 0>;
124
+
};
125
+
hdd_power: regulator@2 {
126
+
compatible = "regulator-fixed";
127
+
reg = <2>;
128
+
regulator-name = "HDD Power";
129
+
regulator-min-microvolt = <5000000>;
130
+
regulator-max-microvolt = <5000000>;
131
+
enable-active-high;
132
+
regulator-always-on;
133
+
regulator-boot-on;
134
+
gpio = <&gpio0 10 0>;
135
+
};
173
136
};
174
137
};
+59
arch/arm/boot/dts/kirkwood-mplcec4.dts
+59
arch/arm/boot/dts/kirkwood-mplcec4.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
6
7
model = "MPL CEC4";
···
17
16
};
18
17
19
18
ocp@f1000000 {
19
+
pinctrl: pinctrl@10000 {
20
+
21
+
pinctrl-0 = < &pmx_nand &pmx_uart0
22
+
&pmx_led_health &pmx_sdio
23
+
&pmx_sata0 &pmx_sata1
24
+
&pmx_led_user1o
25
+
&pmx_led_user1g &pmx_led_user0o
26
+
&pmx_led_user0g &pmx_led_misc
27
+
&pmx_sdio_cd
28
+
>;
29
+
pinctrl-names = "default";
30
+
31
+
pmx_led_health: pmx-led-health {
32
+
marvell,pins = "mpp7";
33
+
marvell,function = "gpo";
34
+
};
35
+
36
+
pmx_sata1: pmx-sata1 {
37
+
marvell,pins = "mpp34";
38
+
marvell,function = "sata1";
39
+
};
40
+
41
+
pmx_sata0: pmx-sata0 {
42
+
marvell,pins = "mpp35";
43
+
marvell,function = "sata0";
44
+
};
45
+
46
+
pmx_led_user1o: pmx-led-user1o {
47
+
marvell,pins = "mpp40";
48
+
marvell,function = "gpio";
49
+
};
50
+
51
+
pmx_led_user1g: pmx-led-user1g {
52
+
marvell,pins = "mpp41";
53
+
marvell,function = "gpio";
54
+
};
55
+
56
+
pmx_led_user0o: pmx-led-user0o {
57
+
marvell,pins = "mpp44";
58
+
marvell,function = "gpio";
59
+
};
60
+
61
+
pmx_led_user0g: pmx-led-user0g {
62
+
marvell,pins = "mpp45";
63
+
marvell,function = "gpio";
64
+
};
65
+
66
+
pmx_led_misc: pmx-led-misc {
67
+
marvell,pins = "mpp46";
68
+
marvell,function = "gpio";
69
+
};
70
+
71
+
pmx_sdio_cd: pmx-sdio-cd {
72
+
marvell,pins = "mpp47";
73
+
marvell,function = "gpio";
74
+
};
75
+
};
76
+
20
77
i2c@11000 {
21
78
status = "okay";
22
79
+59
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+59
arch/arm/boot/dts/kirkwood-openblocks_a6.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood.dtsi"
4
+
/include/ "kirkwood-6282.dtsi"
4
5
5
6
/ {
6
7
model = "Plat'Home OpenBlocksA6";
···
30
29
nand@3000000 {
31
30
chip-delay = <25>;
32
31
status = "okay";
32
+
33
+
partition@0 {
34
+
label = "uboot";
35
+
reg = <0x0 0x90000>;
36
+
};
37
+
38
+
partition@90000 {
39
+
label = "env";
40
+
reg = <0x90000 0x44000>;
41
+
};
42
+
43
+
partition@d4000 {
44
+
label = "test";
45
+
reg = <0xd4000 0x24000>;
46
+
};
47
+
48
+
partition@f4000 {
49
+
label = "conf";
50
+
reg = <0xf4000 0x400000>;
51
+
};
52
+
53
+
partition@4f4000 {
54
+
label = "linux";
55
+
reg = <0x4f4000 0x1d20000>;
56
+
};
57
+
58
+
partition@2214000 {
59
+
label = "user";
60
+
reg = <0x2214000 0x1dec000>;
61
+
};
33
62
};
34
63
35
64
sata@80000 {
36
65
nr-ports = <1>;
37
66
status = "okay";
38
67
};
68
+
69
+
i2c@11100 {
70
+
status = "okay";
71
+
72
+
s35390a: s35390a@30 {
73
+
compatible = "s35390a";
74
+
reg = <0x30>;
75
+
};
76
+
};
39
77
};
78
+
79
+
gpio-leds {
80
+
compatible = "gpio-leds";
81
+
82
+
led-red {
83
+
label = "obsa6:red:stat";
84
+
gpios = <&gpio1 9 1>;
85
+
};
86
+
87
+
led-green {
88
+
label = "obsa6:green:stat";
89
+
gpios = <&gpio1 10 1>;
90
+
};
91
+
92
+
led-yellow {
93
+
label = "obsa6:yellow:stat";
94
+
gpios = <&gpio1 11 1>;
95
+
};
96
+
};
40
97
};
+31
arch/arm/boot/dts/kirkwood-ts219-6281.dts
+31
arch/arm/boot/dts/kirkwood-ts219-6281.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood-ts219.dtsi"
4
+
/include/ "kirkwood-6281.dtsi"
4
5
5
6
/ {
7
+
ocp@f1000000 {
8
+
pinctrl: pinctrl@10000 {
9
+
10
+
pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11
+
&pmx_twsi0 &pmx_sata0 &pmx_sata1
12
+
&pmx_ram_size &pmx_reset_button
13
+
&pmx_USB_copy_button &pmx_board_id>;
14
+
pinctrl-names = "default";
15
+
16
+
pmx_ram_size: pmx-ram-size {
17
+
/* RAM: 0: 256 MB, 1: 512 MB */
18
+
marvell,pins = "mpp36";
19
+
marvell,function = "gpio";
20
+
};
21
+
pmx_USB_copy_button: pmx-USB-copy-button {
22
+
marvell,pins = "mpp15";
23
+
marvell,function = "gpio";
24
+
};
25
+
pmx_reset_button: pmx-reset-button {
26
+
marvell,pins = "mpp16";
27
+
marvell,function = "gpio";
28
+
};
29
+
pmx_board_id: pmx-board-id {
30
+
/* 0: TS-11x, 1: TS-21x */
31
+
marvell,pins = "mpp44";
32
+
marvell,function = "gpio";
33
+
};
34
+
};
35
+
};
36
+
6
37
gpio_keys {
7
38
compatible = "gpio-keys";
8
39
#address-cells = <1>;
+31
arch/arm/boot/dts/kirkwood-ts219-6282.dts
+31
arch/arm/boot/dts/kirkwood-ts219-6282.dts
···
1
1
/dts-v1/;
2
2
3
3
/include/ "kirkwood-ts219.dtsi"
4
+
/include/ "kirkwood-6282.dtsi"
4
5
5
6
/ {
7
+
ocp@f1000000 {
8
+
pinctrl: pinctrl@10000 {
9
+
10
+
pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11
+
&pmx_twsi0 &pmx_sata0 &pmx_sata1
12
+
&pmx_ram_size &pmx_reset_button
13
+
&pmx_USB_copy_button &pmx_board_id>;
14
+
pinctrl-names = "default";
15
+
16
+
pmx_ram_size: pmx-ram-size {
17
+
/* RAM: 0: 256 MB, 1: 512 MB */
18
+
marvell,pins = "mpp36";
19
+
marvell,function = "gpio";
20
+
};
21
+
pmx_reset_button: pmx-reset-button {
22
+
marvell,pins = "mpp37";
23
+
marvell,function = "gpio";
24
+
};
25
+
pmx_USB_copy_button: pmx-USB-copy-button {
26
+
marvell,pins = "mpp43";
27
+
marvell,function = "gpio";
28
+
};
29
+
pmx_board_id: pmx-board-id {
30
+
/* 0: TS-11x, 1: TS-21x */
31
+
marvell,pins = "mpp44";
32
+
marvell,function = "gpio";
33
+
};
34
+
};
35
+
};
36
+
6
37
gpio_keys {
7
38
compatible = "gpio-keys";
8
39
#address-cells = <1>;
+15
-2
arch/arm/boot/dts/kirkwood.dtsi
+15
-2
arch/arm/boot/dts/kirkwood.dtsi
···
4
4
compatible = "marvell,kirkwood";
5
5
interrupt-parent = <&intc>;
6
6
7
+
aliases {
8
+
gpio0 = &gpio0;
9
+
gpio1 = &gpio1;
10
+
};
7
11
intc: interrupt-controller {
8
12
compatible = "marvell,orion-intc", "marvell,intc";
9
13
interrupt-controller;
···
28
24
#gpio-cells = <2>;
29
25
gpio-controller;
30
26
reg = <0x10100 0x40>;
31
-
ngpio = <32>;
27
+
ngpios = <32>;
28
+
interrupt-controller;
32
29
interrupts = <35>, <36>, <37>, <38>;
33
30
};
34
31
···
38
33
#gpio-cells = <2>;
39
34
gpio-controller;
40
35
reg = <0x10140 0x40>;
41
-
ngpio = <18>;
36
+
ngpios = <18>;
37
+
interrupt-controller;
42
38
interrupts = <39>, <40>, <41>;
43
39
};
44
40
···
80
74
wdt@20300 {
81
75
compatible = "marvell,orion-wdt";
82
76
reg = <0x20300 0x28>;
77
+
status = "okay";
78
+
};
79
+
80
+
ehci@50000 {
81
+
compatible = "marvell,orion-ehci";
82
+
reg = <0x50000 0x1000>;
83
+
interrupts = <19>;
83
84
status = "okay";
84
85
};
85
86
+7
arch/arm/boot/dts/lpc32xx.dtsi
+7
arch/arm/boot/dts/lpc32xx.dtsi
···
182
182
pnx,timeout = <0x64>;
183
183
};
184
184
185
+
mpwm: mpwm@400E8000 {
186
+
compatible = "nxp,lpc3220-motor-pwm";
187
+
reg = <0x400E8000 0x78>;
188
+
status = "disabled";
189
+
#pwm-cells = <2>;
190
+
};
191
+
185
192
i2cusb: i2c@31020300 {
186
193
compatible = "nxp,pnx-i2c";
187
194
reg = <0x31020300 0x100>;
+136
-4
arch/arm/boot/dts/snowball.dts
+136
-4
arch/arm/boot/dts/snowball.dts
···
14
14
15
15
/ {
16
16
model = "Calao Systems Snowball platform with device tree";
17
-
compatible = "calaosystems,snowball-a9500";
17
+
compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
18
18
19
19
memory {
20
20
reg = <0x00000000 0x20000000>;
···
147
147
};
148
148
149
149
// External Micro SD slot
150
-
sdi@80126000 {
150
+
sdi0_per1@80126000 {
151
151
arm,primecell-periphid = <0x10480180>;
152
152
max-frequency = <50000000>;
153
-
bus-width = <8>;
153
+
bus-width = <4>;
154
154
mmc-cap-mmc-highspeed;
155
155
vmmc-supply = <&ab8500_ldo_aux3_reg>;
156
156
···
161
161
};
162
162
163
163
// On-board eMMC
164
-
sdi@80114000 {
164
+
sdi4_per2@80114000 {
165
165
arm,primecell-periphid = <0x10480180>;
166
166
max-frequency = <50000000>;
167
167
bus-width = <8>;
···
213
213
214
214
cpufreq-cooling {
215
215
status = "okay";
216
+
};
217
+
218
+
prcmu@80157000 {
219
+
db8500-prcmu-regulators {
220
+
db8500_vape_reg: db8500_vape {
221
+
regulator-name = "db8500-vape";
222
+
};
223
+
224
+
db8500_varm_reg: db8500_varm {
225
+
regulator-name = "db8500-varm";
226
+
};
227
+
228
+
db8500_vmodem_reg: db8500_vmodem {
229
+
regulator-name = "db8500-vmodem";
230
+
};
231
+
232
+
db8500_vpll_reg: db8500_vpll {
233
+
regulator-name = "db8500-vpll";
234
+
};
235
+
236
+
db8500_vsmps1_reg: db8500_vsmps1 {
237
+
regulator-name = "db8500-vsmps1";
238
+
};
239
+
240
+
db8500_vsmps2_reg: db8500_vsmps2 {
241
+
regulator-name = "db8500-vsmps2";
242
+
};
243
+
244
+
db8500_vsmps3_reg: db8500_vsmps3 {
245
+
regulator-name = "db8500-vsmps3";
246
+
};
247
+
248
+
db8500_vrf1_reg: db8500_vrf1 {
249
+
regulator-name = "db8500-vrf1";
250
+
};
251
+
252
+
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
253
+
regulator-name = "db8500-sva-mmdsp";
254
+
};
255
+
256
+
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
257
+
regulator-name = "db8500-sva-mmdsp-ret";
258
+
};
259
+
260
+
db8500_sva_pipe_reg: db8500_sva_pipe {
261
+
regulator-name = "db8500_sva_pipe";
262
+
};
263
+
264
+
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
265
+
regulator-name = "db8500_sia_mmdsp";
266
+
};
267
+
268
+
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
269
+
regulator-name = "db8500-sia-mmdsp-ret";
270
+
};
271
+
272
+
db8500_sia_pipe_reg: db8500_sia_pipe {
273
+
regulator-name = "db8500-sia-pipe";
274
+
};
275
+
276
+
db8500_sga_reg: db8500_sga {
277
+
regulator-name = "db8500-sga";
278
+
};
279
+
280
+
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
281
+
regulator-name = "db8500-b2r2-mcde";
282
+
};
283
+
284
+
db8500_esram12_reg: db8500_esram12 {
285
+
regulator-name = "db8500-esram12";
286
+
};
287
+
288
+
db8500_esram12_ret_reg: db8500_esram12_ret {
289
+
regulator-name = "db8500-esram12-ret";
290
+
};
291
+
292
+
db8500_esram34_reg: db8500_esram34 {
293
+
regulator-name = "db8500-esram34";
294
+
};
295
+
296
+
db8500_esram34_ret_reg: db8500_esram34_ret {
297
+
regulator-name = "db8500-esram34-ret";
298
+
};
299
+
};
300
+
301
+
ab8500@5 {
302
+
ab8500-regulators {
303
+
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
304
+
regulator-name = "V-DISPLAY";
305
+
};
306
+
307
+
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
308
+
regulator-name = "V-eMMC1";
309
+
};
310
+
311
+
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
312
+
regulator-name = "V-MMC-SD";
313
+
};
314
+
315
+
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
316
+
regulator-name = "V-INTCORE";
317
+
};
318
+
319
+
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
320
+
regulator-name = "V-TVOUT";
321
+
};
322
+
323
+
ab8500_ldo_usb_reg: ab8500_ldo_usb {
324
+
regulator-name = "dummy";
325
+
};
326
+
327
+
ab8500_ldo_audio_reg: ab8500_ldo_audio {
328
+
regulator-name = "V-AUD";
329
+
};
330
+
331
+
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
332
+
regulator-name = "V-AMIC1";
333
+
};
334
+
335
+
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
336
+
regulator-name = "V-AMIC2";
337
+
};
338
+
339
+
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
340
+
regulator-name = "V-DMIC";
341
+
};
342
+
343
+
ab8500_ldo_ana_reg: ab8500_ldo_ana {
344
+
regulator-name = "V-CSI/DSI";
345
+
};
346
+
};
347
+
};
216
348
};
217
349
};
218
350
};
+78
arch/arm/boot/dts/stuib.dtsi
+78
arch/arm/boot/dts/stuib.dtsi
···
1
+
/*
2
+
* Copyright 2012 ST-Ericsson AB
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/ {
13
+
soc-u9500 {
14
+
i2c@80004000 {
15
+
stmpe1601: stmpe1601@40 {
16
+
compatible = "st,stmpe1601";
17
+
reg = <0x40>;
18
+
interrupts = <26 0x1>;
19
+
interrupt-parent = <&gpio6>;
20
+
interrupt-controller;
21
+
22
+
wakeup-source;
23
+
st,autosleep-timeout = <1024>;
24
+
25
+
stmpe_keypad {
26
+
compatible = "st,stmpe-keypad";
27
+
28
+
debounce-interval = <64>;
29
+
st,scan-count = <8>;
30
+
st,no-autorepeat;
31
+
32
+
linux,keymap = <0x205006b
33
+
0x4010074
34
+
0x3050072
35
+
0x1030004
36
+
0x502006a
37
+
0x500000a
38
+
0x5008b
39
+
0x706001c
40
+
0x405000b
41
+
0x6070003
42
+
0x3040067
43
+
0x303006c
44
+
0x60400e7
45
+
0x602009e
46
+
0x4020073
47
+
0x5050002
48
+
0x4030069
49
+
0x3020008>;
50
+
};
51
+
};
52
+
};
53
+
54
+
i2c@80110000 {
55
+
bu21013_tp@0x5c {
56
+
compatible = "rhom,bu21013_tp";
57
+
reg = <0x5c>;
58
+
touch-gpio = <&gpio2 20 0x4>;
59
+
avdd-supply = <&ab8500_ldo_aux1_reg>;
60
+
61
+
rhom,touch-max-x = <384>;
62
+
rhom,touch-max-y = <704>;
63
+
rhom,flip-y;
64
+
};
65
+
66
+
bu21013_tp@0x5d {
67
+
compatible = "rhom,bu21013_tp";
68
+
reg = <0x5d>;
69
+
touch-gpio = <&gpio2 20 0x4>;
70
+
avdd-supply = <&ab8500_ldo_aux1_reg>;
71
+
72
+
rhom,touch-max-x = <384>;
73
+
rhom,touch-max-y = <704>;
74
+
rhom,flip-y;
75
+
};
76
+
};
77
+
};
78
+
};
+21
-4
arch/arm/boot/dts/tegra20-harmony.dts
+21
-4
arch/arm/boot/dts/tegra20-harmony.dts
···
10
10
reg = <0x00000000 0x40000000>;
11
11
};
12
12
13
+
host1x {
14
+
hdmi {
15
+
status = "okay";
16
+
17
+
vdd-supply = <&hdmi_vdd_reg>;
18
+
pll-supply = <&hdmi_pll_reg>;
19
+
20
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21
+
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22
+
};
23
+
};
24
+
13
25
pinmux {
14
26
pinctrl-names = "default";
15
27
pinctrl-0 = <&state_default>;
···
274
262
};
275
263
};
276
264
277
-
i2c@7000c400 {
265
+
hdmi_ddc: i2c@7000c400 {
278
266
status = "okay";
279
-
clock-frequency = <400000>;
267
+
clock-frequency = <100000>;
280
268
};
281
269
282
270
i2c@7000c500 {
···
381
369
regulator-max-microvolt = <1800000>;
382
370
};
383
371
384
-
ldo7 {
372
+
hdmi_vdd_reg: ldo7 {
385
373
regulator-name = "vdd_ldo7,avdd_hdmi";
386
374
regulator-min-microvolt = <3300000>;
387
375
regulator-max-microvolt = <3300000>;
388
376
};
389
377
390
-
ldo8 {
378
+
hdmi_pll_reg: ldo8 {
391
379
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
392
380
regulator-min-microvolt = <1800000>;
393
381
regulator-max-microvolt = <1800000>;
···
407
395
regulator-always-on;
408
396
};
409
397
};
398
+
};
399
+
400
+
temperature-sensor@4c {
401
+
compatible = "adi,adt7461";
402
+
reg = <0x4c>;
410
403
};
411
404
};
412
405
+6
arch/arm/boot/dts/tegra20-plutux.dts
+6
arch/arm/boot/dts/tegra20-plutux.dts
+6
arch/arm/boot/dts/tegra20-seaboard.dts
+6
arch/arm/boot/dts/tegra20-seaboard.dts
+81
-7
arch/arm/boot/dts/tegra20-tamonten.dtsi
+81
-7
arch/arm/boot/dts/tegra20-tamonten.dtsi
···
8
8
reg = <0x00000000 0x20000000>;
9
9
};
10
10
11
+
host1x {
12
+
hdmi {
13
+
vdd-supply = <&hdmi_vdd_reg>;
14
+
pll-supply = <&hdmi_pll_reg>;
15
+
16
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17
+
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18
+
};
19
+
};
20
+
11
21
pinmux {
12
22
pinctrl-names = "default";
13
23
pinctrl-0 = <&state_default>;
···
72
62
nvidia,pins = "dap4";
73
63
nvidia,function = "dap4";
74
64
};
75
-
ddc {
76
-
nvidia,pins = "ddc";
77
-
nvidia,function = "i2c2";
78
-
};
79
65
dta {
80
66
nvidia,pins = "dta", "dtd";
81
67
nvidia,function = "sdio2";
···
97
91
nvidia,function = "pcie";
98
92
};
99
93
hdint {
100
-
nvidia,pins = "hdint", "pta";
94
+
nvidia,pins = "hdint";
101
95
nvidia,function = "hdmi";
102
96
};
103
97
i2cp {
···
236
230
nvidia,pull = <1>;
237
231
};
238
232
};
233
+
234
+
state_i2cmux_ddc: pinmux_i2cmux_ddc {
235
+
ddc {
236
+
nvidia,pins = "ddc";
237
+
nvidia,function = "i2c2";
238
+
};
239
+
pta {
240
+
nvidia,pins = "pta";
241
+
nvidia,function = "rsvd4";
242
+
};
243
+
};
244
+
245
+
state_i2cmux_pta: pinmux_i2cmux_pta {
246
+
ddc {
247
+
nvidia,pins = "ddc";
248
+
nvidia,function = "rsvd4";
249
+
};
250
+
pta {
251
+
nvidia,pins = "pta";
252
+
nvidia,function = "i2c2";
253
+
};
254
+
};
255
+
256
+
state_i2cmux_idle: pinmux_i2cmux_idle {
257
+
ddc {
258
+
nvidia,pins = "ddc";
259
+
nvidia,function = "rsvd4";
260
+
};
261
+
pta {
262
+
nvidia,pins = "pta";
263
+
nvidia,function = "rsvd4";
264
+
};
265
+
};
239
266
};
240
267
241
268
i2s@70002800 {
···
283
244
i2c@7000c000 {
284
245
clock-frequency = <400000>;
285
246
status = "okay";
247
+
};
248
+
249
+
i2c@7000c400 {
250
+
clock-frequency = <100000>;
251
+
status = "okay";
252
+
};
253
+
254
+
i2cmux {
255
+
compatible = "i2c-mux-pinctrl";
256
+
#address-cells = <1>;
257
+
#size-cells = <0>;
258
+
259
+
i2c-parent = <&{/i2c@7000c400}>;
260
+
261
+
pinctrl-names = "ddc", "pta", "idle";
262
+
pinctrl-0 = <&state_i2cmux_ddc>;
263
+
pinctrl-1 = <&state_i2cmux_pta>;
264
+
pinctrl-2 = <&state_i2cmux_idle>;
265
+
266
+
hdmi_ddc: i2c@0 {
267
+
reg = <0>;
268
+
#address-cells = <1>;
269
+
#size-cells = <0>;
270
+
};
271
+
272
+
i2c@1 {
273
+
reg = <1>;
274
+
#address-cells = <1>;
275
+
#size-cells = <0>;
276
+
};
286
277
};
287
278
288
279
i2c@7000d000 {
···
417
348
regulator-max-microvolt = <2850000>;
418
349
};
419
350
420
-
ldo7 {
351
+
hdmi_vdd_reg: ldo7 {
421
352
regulator-name = "vdd_ldo7,avdd_hdmi";
422
353
regulator-min-microvolt = <3300000>;
423
354
regulator-max-microvolt = <3300000>;
424
355
};
425
356
426
-
ldo8 {
357
+
hdmi_pll_reg: ldo8 {
427
358
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
428
359
regulator-min-microvolt = <1800000>;
429
360
regulator-max-microvolt = <1800000>;
···
449
380
regulator-always-on;
450
381
};
451
382
};
383
+
};
384
+
385
+
temperature-sensor@4c {
386
+
compatible = "onnn,nct1008";
387
+
reg = <0x4c>;
452
388
};
453
389
};
454
390
+6
-3
arch/arm/boot/dts/tegra20-tec.dts
+6
-3
arch/arm/boot/dts/tegra20-tec.dts
···
6
6
model = "Avionic Design Tamonten Evaluation Carrier";
7
7
compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
8
9
-
i2c@7000c000 {
10
-
clock-frequency = <400000>;
11
-
status = "okay";
9
+
host1x {
10
+
hdmi {
11
+
status = "okay";
12
+
};
13
+
};
12
14
15
+
i2c@7000c000 {
13
16
wm8903: wm8903@1a {
14
17
compatible = "wlf,wm8903";
15
18
reg = <0x1a>;
+50
-4
arch/arm/boot/dts/tegra20-trimslice.dts
+50
-4
arch/arm/boot/dts/tegra20-trimslice.dts
···
10
10
reg = <0x00000000 0x40000000>;
11
11
};
12
12
13
+
host1x {
14
+
hdmi {
15
+
status = "okay";
16
+
17
+
vdd-supply = <&hdmi_vdd_reg>;
18
+
pll-supply = <&hdmi_pll_reg>;
19
+
20
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21
+
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22
+
};
23
+
};
24
+
13
25
pinmux {
14
26
pinctrl-names = "default";
15
27
pinctrl-0 = <&state_default>;
···
261
249
clock-frequency = <216000000>;
262
250
};
263
251
264
-
i2c@7000c000 {
252
+
dvi_ddc: i2c@7000c000 {
265
253
status = "okay";
266
-
clock-frequency = <400000>;
254
+
clock-frequency = <100000>;
267
255
};
268
256
269
-
i2c@7000c400 {
257
+
spi@7000c380 {
270
258
status = "okay";
271
-
clock-frequency = <400000>;
259
+
spi-max-frequency = <48000000>;
260
+
spi-flash@0 {
261
+
compatible = "winbond,w25q80bl";
262
+
reg = <0>;
263
+
spi-max-frequency = <48000000>;
264
+
};
265
+
};
266
+
267
+
hdmi_ddc: i2c@7000c400 {
268
+
status = "okay";
269
+
clock-frequency = <100000>;
272
270
};
273
271
274
272
i2c@7000c500 {
···
320
298
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
321
299
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
322
300
bus-width = <4>;
301
+
};
302
+
303
+
regulators {
304
+
compatible = "simple-bus";
305
+
#address-cells = <1>;
306
+
#size-cells = <0>;
307
+
308
+
hdmi_vdd_reg: regulator@0 {
309
+
compatible = "regulator-fixed";
310
+
reg = <0>;
311
+
regulator-name = "avdd_hdmi";
312
+
regulator-min-microvolt = <3300000>;
313
+
regulator-max-microvolt = <3300000>;
314
+
regulator-always-on;
315
+
};
316
+
317
+
hdmi_pll_reg: regulator@1 {
318
+
compatible = "regulator-fixed";
319
+
reg = <1>;
320
+
regulator-name = "avdd_hdmi_pll";
321
+
regulator-min-microvolt = <1800000>;
322
+
regulator-max-microvolt = <1800000>;
323
+
regulator-always-on;
324
+
};
323
325
};
324
326
325
327
sound {
+84
-6
arch/arm/boot/dts/tegra20-ventana.dts
+84
-6
arch/arm/boot/dts/tegra20-ventana.dts
···
64
64
nvidia,pins = "dap4";
65
65
nvidia,function = "dap4";
66
66
};
67
-
ddc {
68
-
nvidia,pins = "ddc", "owc", "spdi", "spdo",
69
-
"uac";
70
-
nvidia,function = "rsvd2";
71
-
};
72
67
dta {
73
68
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74
69
nvidia,function = "vi";
···
93
98
nvidia,function = "pcie";
94
99
};
95
100
hdint {
96
-
nvidia,pins = "hdint", "pta";
101
+
nvidia,pins = "hdint";
97
102
nvidia,function = "hdmi";
98
103
};
99
104
i2cp {
···
123
128
"lpw2", "lsc0", "lsc1", "lsck", "lsda",
124
129
"lspi", "lvp1", "lvs";
125
130
nvidia,function = "displaya";
131
+
};
132
+
owc {
133
+
nvidia,pins = "owc", "spdi", "spdo", "uac";
134
+
nvidia,function = "rsvd2";
126
135
};
127
136
pmc {
128
137
nvidia,pins = "pmc";
···
236
237
"ld23_22";
237
238
nvidia,pull = <1>;
238
239
};
240
+
drive_sdio1 {
241
+
nvidia,pins = "drive_sdio1";
242
+
nvidia,high-speed-mode = <0>;
243
+
nvidia,schmitt = <1>;
244
+
nvidia,low-power-mode = <3>;
245
+
nvidia,pull-down-strength = <31>;
246
+
nvidia,pull-up-strength = <31>;
247
+
nvidia,slew-rate-rising = <3>;
248
+
nvidia,slew-rate-falling = <3>;
249
+
};
250
+
};
251
+
252
+
state_i2cmux_ddc: pinmux_i2cmux_ddc {
253
+
ddc {
254
+
nvidia,pins = "ddc";
255
+
nvidia,function = "i2c2";
256
+
};
257
+
pta {
258
+
nvidia,pins = "pta";
259
+
nvidia,function = "rsvd4";
260
+
};
261
+
};
262
+
263
+
state_i2cmux_pta: pinmux_i2cmux_pta {
264
+
ddc {
265
+
nvidia,pins = "ddc";
266
+
nvidia,function = "rsvd4";
267
+
};
268
+
pta {
269
+
nvidia,pins = "pta";
270
+
nvidia,function = "i2c2";
271
+
};
272
+
};
273
+
274
+
state_i2cmux_idle: pinmux_i2cmux_idle {
275
+
ddc {
276
+
nvidia,pins = "ddc";
277
+
nvidia,function = "rsvd4";
278
+
};
279
+
pta {
280
+
nvidia,pins = "pta";
281
+
nvidia,function = "rsvd4";
282
+
};
239
283
};
240
284
};
241
285
···
321
279
i2c@7000c400 {
322
280
status = "okay";
323
281
clock-frequency = <400000>;
282
+
};
283
+
284
+
i2cmux {
285
+
compatible = "i2c-mux-pinctrl";
286
+
#address-cells = <1>;
287
+
#size-cells = <0>;
288
+
289
+
i2c-parent = <&{/i2c@7000c400}>;
290
+
291
+
pinctrl-names = "ddc", "pta", "idle";
292
+
pinctrl-0 = <&state_i2cmux_ddc>;
293
+
pinctrl-1 = <&state_i2cmux_pta>;
294
+
pinctrl-2 = <&state_i2cmux_idle>;
295
+
296
+
i2c@0 {
297
+
reg = <0>;
298
+
#address-cells = <1>;
299
+
#size-cells = <0>;
300
+
};
301
+
302
+
i2c@1 {
303
+
reg = <1>;
304
+
#address-cells = <1>;
305
+
#size-cells = <0>;
306
+
};
324
307
};
325
308
326
309
i2c@7000c500 {
···
473
406
};
474
407
};
475
408
};
409
+
410
+
temperature-sensor@4c {
411
+
compatible = "onnn,nct1008";
412
+
reg = <0x4c>;
413
+
};
476
414
};
477
415
478
416
pmc {
···
495
423
496
424
usb@c5008000 {
497
425
status = "okay";
426
+
};
427
+
428
+
sdhci@c8000000 {
429
+
status = "okay";
430
+
power-gpios = <&gpio 86 0>; /* gpio PK6 */
431
+
bus-width = <4>;
498
432
};
499
433
500
434
sdhci@c8000400 {
+19
-2
arch/arm/boot/dts/tegra20-whistler.dts
+19
-2
arch/arm/boot/dts/tegra20-whistler.dts
···
10
10
reg = <0x00000000 0x20000000>;
11
11
};
12
12
13
+
host1x {
14
+
hdmi {
15
+
status = "okay";
16
+
17
+
vdd-supply = <&hdmi_vdd_reg>;
18
+
pll-supply = <&hdmi_pll_reg>;
19
+
20
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21
+
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22
+
};
23
+
};
24
+
13
25
pinmux {
14
26
pinctrl-names = "default";
15
27
pinctrl-0 = <&state_default>;
···
258
246
clock-frequency = <216000000>;
259
247
};
260
248
249
+
hdmi_ddc: i2c@7000c400 {
250
+
status = "okay";
251
+
clock-frequency = <100000>;
252
+
};
253
+
261
254
i2c@7000d000 {
262
255
status = "okay";
263
256
clock-frequency = <100000>;
···
373
356
regulator-always-on;
374
357
};
375
358
376
-
ldo6 {
359
+
hdmi_pll_reg: ldo6 {
377
360
regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
378
361
regulator-min-microvolt = <1800000>;
379
362
regulator-max-microvolt = <1800000>;
···
405
388
regulator-always-on;
406
389
};
407
390
408
-
ldo11 {
391
+
hdmi_vdd_reg: ldo11 {
409
392
regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
410
393
regulator-min-microvolt = <3300000>;
411
394
regulator-max-microvolt = <3300000>;
+137
arch/arm/boot/dts/tegra20.dtsi
+137
arch/arm/boot/dts/tegra20.dtsi
···
4
4
compatible = "nvidia,tegra20";
5
5
interrupt-parent = <&intc>;
6
6
7
+
host1x {
8
+
compatible = "nvidia,tegra20-host1x", "simple-bus";
9
+
reg = <0x50000000 0x00024000>;
10
+
interrupts = <0 65 0x04 /* mpcore syncpt */
11
+
0 67 0x04>; /* mpcore general */
12
+
13
+
#address-cells = <1>;
14
+
#size-cells = <1>;
15
+
16
+
ranges = <0x54000000 0x54000000 0x04000000>;
17
+
18
+
mpe {
19
+
compatible = "nvidia,tegra20-mpe";
20
+
reg = <0x54040000 0x00040000>;
21
+
interrupts = <0 68 0x04>;
22
+
};
23
+
24
+
vi {
25
+
compatible = "nvidia,tegra20-vi";
26
+
reg = <0x54080000 0x00040000>;
27
+
interrupts = <0 69 0x04>;
28
+
};
29
+
30
+
epp {
31
+
compatible = "nvidia,tegra20-epp";
32
+
reg = <0x540c0000 0x00040000>;
33
+
interrupts = <0 70 0x04>;
34
+
};
35
+
36
+
isp {
37
+
compatible = "nvidia,tegra20-isp";
38
+
reg = <0x54100000 0x00040000>;
39
+
interrupts = <0 71 0x04>;
40
+
};
41
+
42
+
gr2d {
43
+
compatible = "nvidia,tegra20-gr2d";
44
+
reg = <0x54140000 0x00040000>;
45
+
interrupts = <0 72 0x04>;
46
+
};
47
+
48
+
gr3d {
49
+
compatible = "nvidia,tegra20-gr3d";
50
+
reg = <0x54180000 0x00040000>;
51
+
};
52
+
53
+
dc@54200000 {
54
+
compatible = "nvidia,tegra20-dc";
55
+
reg = <0x54200000 0x00040000>;
56
+
interrupts = <0 73 0x04>;
57
+
58
+
rgb {
59
+
status = "disabled";
60
+
};
61
+
};
62
+
63
+
dc@54240000 {
64
+
compatible = "nvidia,tegra20-dc";
65
+
reg = <0x54240000 0x00040000>;
66
+
interrupts = <0 74 0x04>;
67
+
68
+
rgb {
69
+
status = "disabled";
70
+
};
71
+
};
72
+
73
+
hdmi {
74
+
compatible = "nvidia,tegra20-hdmi";
75
+
reg = <0x54280000 0x00040000>;
76
+
interrupts = <0 75 0x04>;
77
+
status = "disabled";
78
+
};
79
+
80
+
tvo {
81
+
compatible = "nvidia,tegra20-tvo";
82
+
reg = <0x542c0000 0x00040000>;
83
+
interrupts = <0 76 0x04>;
84
+
status = "disabled";
85
+
};
86
+
87
+
dsi {
88
+
compatible = "nvidia,tegra20-dsi";
89
+
reg = <0x54300000 0x00040000>;
90
+
status = "disabled";
91
+
};
92
+
};
93
+
7
94
cache-controller@50043000 {
8
95
compatible = "arm,pl310-cache";
9
96
reg = <0x50043000 0x1000>;
···
234
147
status = "disabled";
235
148
};
236
149
150
+
spi@7000c380 {
151
+
compatible = "nvidia,tegra20-sflash";
152
+
reg = <0x7000c380 0x80>;
153
+
interrupts = <0 39 0x04>;
154
+
nvidia,dma-request-selector = <&apbdma 11>;
155
+
#address-cells = <1>;
156
+
#size-cells = <0>;
157
+
status = "disabled";
158
+
};
159
+
237
160
i2c@7000c400 {
238
161
compatible = "nvidia,tegra20-i2c";
239
162
reg = <0x7000c400 0x100>;
···
266
169
compatible = "nvidia,tegra20-i2c-dvc";
267
170
reg = <0x7000d000 0x200>;
268
171
interrupts = <0 53 0x04>;
172
+
#address-cells = <1>;
173
+
#size-cells = <0>;
174
+
status = "disabled";
175
+
};
176
+
177
+
spi@7000d400 {
178
+
compatible = "nvidia,tegra20-slink";
179
+
reg = <0x7000d400 0x200>;
180
+
interrupts = <0 59 0x04>;
181
+
nvidia,dma-request-selector = <&apbdma 15>;
182
+
#address-cells = <1>;
183
+
#size-cells = <0>;
184
+
status = "disabled";
185
+
};
186
+
187
+
spi@7000d600 {
188
+
compatible = "nvidia,tegra20-slink";
189
+
reg = <0x7000d600 0x200>;
190
+
interrupts = <0 82 0x04>;
191
+
nvidia,dma-request-selector = <&apbdma 16>;
192
+
#address-cells = <1>;
193
+
#size-cells = <0>;
194
+
status = "disabled";
195
+
};
196
+
197
+
spi@7000d800 {
198
+
compatible = "nvidia,tegra20-slink";
199
+
reg = <0x7000d480 0x200>;
200
+
interrupts = <0 83 0x04>;
201
+
nvidia,dma-request-selector = <&apbdma 17>;
202
+
#address-cells = <1>;
203
+
#size-cells = <0>;
204
+
status = "disabled";
205
+
};
206
+
207
+
spi@7000da00 {
208
+
compatible = "nvidia,tegra20-slink";
209
+
reg = <0x7000da00 0x200>;
210
+
interrupts = <0 93 0x04>;
211
+
nvidia,dma-request-selector = <&apbdma 18>;
269
212
#address-cells = <1>;
270
213
#size-cells = <0>;
271
214
status = "disabled";
+6
arch/arm/boot/dts/tegra30-cardhu-a02.dts
+6
arch/arm/boot/dts/tegra30-cardhu-a02.dts
+6
arch/arm/boot/dts/tegra30-cardhu-a04.dts
+6
arch/arm/boot/dts/tegra30-cardhu-a04.dts
+37
arch/arm/boot/dts/tegra30-cardhu.dtsi
+37
arch/arm/boot/dts/tegra30-cardhu.dtsi
···
52
52
nvidia,pull = <2>;
53
53
nvidia,tristate = <0>;
54
54
};
55
+
sdmmc3_clk_pa6 {
56
+
nvidia,pins = "sdmmc3_clk_pa6";
57
+
nvidia,function = "sdmmc3";
58
+
nvidia,pull = <0>;
59
+
nvidia,tristate = <0>;
60
+
};
61
+
sdmmc3_cmd_pa7 {
62
+
nvidia,pins = "sdmmc3_cmd_pa7",
63
+
"sdmmc3_dat0_pb7",
64
+
"sdmmc3_dat1_pb6",
65
+
"sdmmc3_dat2_pb5",
66
+
"sdmmc3_dat3_pb4";
67
+
nvidia,function = "sdmmc3";
68
+
nvidia,pull = <2>;
69
+
nvidia,tristate = <0>;
70
+
};
55
71
sdmmc4_clk_pcc4 {
56
72
nvidia,pins = "sdmmc4_clk_pcc4",
57
73
"sdmmc4_rst_n_pcc3";
···
96
80
nvidia,function = "i2s1";
97
81
nvidia,pull = <0>;
98
82
nvidia,tristate = <0>;
83
+
};
84
+
sdio3 {
85
+
nvidia,pins = "drive_sdio3";
86
+
nvidia,high-speed-mode = <0>;
87
+
nvidia,schmitt = <0>;
88
+
nvidia,pull-down-strength = <46>;
89
+
nvidia,pull-up-strength = <42>;
90
+
nvidia,slew-rate-rising = <1>;
91
+
nvidia,slew-rate-falling = <1>;
99
92
};
100
93
};
101
94
};
···
275
250
};
276
251
};
277
252
253
+
spi@7000da00 {
254
+
status = "okay";
255
+
spi-max-frequency = <25000000>;
256
+
spi-flash@1 {
257
+
compatible = "winbond,w25q32";
258
+
reg = <1>;
259
+
spi-max-frequency = <20000000>;
260
+
};
261
+
};
262
+
278
263
ahub {
279
264
i2s@70080400 {
280
265
status = "okay";
···
419
384
regulator-name = "vdd_com";
420
385
regulator-min-microvolt = <3300000>;
421
386
regulator-max-microvolt = <3300000>;
387
+
regulator-always-on;
388
+
regulator-boot-on;
422
389
enable-active-high;
423
390
gpio = <&gpio 24 0>; /* gpio PD0 */
424
391
vin-supply = <&sys_3v3_reg>;
+147
arch/arm/boot/dts/tegra30.dtsi
+147
arch/arm/boot/dts/tegra30.dtsi
···
4
4
compatible = "nvidia,tegra30";
5
5
interrupt-parent = <&intc>;
6
6
7
+
host1x {
8
+
compatible = "nvidia,tegra30-host1x", "simple-bus";
9
+
reg = <0x50000000 0x00024000>;
10
+
interrupts = <0 65 0x04 /* mpcore syncpt */
11
+
0 67 0x04>; /* mpcore general */
12
+
13
+
#address-cells = <1>;
14
+
#size-cells = <1>;
15
+
16
+
ranges = <0x54000000 0x54000000 0x04000000>;
17
+
18
+
mpe {
19
+
compatible = "nvidia,tegra30-mpe";
20
+
reg = <0x54040000 0x00040000>;
21
+
interrupts = <0 68 0x04>;
22
+
};
23
+
24
+
vi {
25
+
compatible = "nvidia,tegra30-vi";
26
+
reg = <0x54080000 0x00040000>;
27
+
interrupts = <0 69 0x04>;
28
+
};
29
+
30
+
epp {
31
+
compatible = "nvidia,tegra30-epp";
32
+
reg = <0x540c0000 0x00040000>;
33
+
interrupts = <0 70 0x04>;
34
+
};
35
+
36
+
isp {
37
+
compatible = "nvidia,tegra30-isp";
38
+
reg = <0x54100000 0x00040000>;
39
+
interrupts = <0 71 0x04>;
40
+
};
41
+
42
+
gr2d {
43
+
compatible = "nvidia,tegra30-gr2d";
44
+
reg = <0x54140000 0x00040000>;
45
+
interrupts = <0 72 0x04>;
46
+
};
47
+
48
+
gr3d {
49
+
compatible = "nvidia,tegra30-gr3d";
50
+
reg = <0x54180000 0x00040000>;
51
+
};
52
+
53
+
dc@54200000 {
54
+
compatible = "nvidia,tegra30-dc";
55
+
reg = <0x54200000 0x00040000>;
56
+
interrupts = <0 73 0x04>;
57
+
58
+
rgb {
59
+
status = "disabled";
60
+
};
61
+
};
62
+
63
+
dc@54240000 {
64
+
compatible = "nvidia,tegra30-dc";
65
+
reg = <0x54240000 0x00040000>;
66
+
interrupts = <0 74 0x04>;
67
+
68
+
rgb {
69
+
status = "disabled";
70
+
};
71
+
};
72
+
73
+
hdmi {
74
+
compatible = "nvidia,tegra30-hdmi";
75
+
reg = <0x54280000 0x00040000>;
76
+
interrupts = <0 75 0x04>;
77
+
status = "disabled";
78
+
};
79
+
80
+
tvo {
81
+
compatible = "nvidia,tegra30-tvo";
82
+
reg = <0x542c0000 0x00040000>;
83
+
interrupts = <0 76 0x04>;
84
+
status = "disabled";
85
+
};
86
+
87
+
dsi {
88
+
compatible = "nvidia,tegra30-dsi";
89
+
reg = <0x54300000 0x00040000>;
90
+
status = "disabled";
91
+
};
92
+
};
93
+
7
94
cache-controller@50043000 {
8
95
compatible = "arm,pl310-cache";
9
96
reg = <0x50043000 0x1000>;
···
259
172
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
260
173
reg = <0x7000d000 0x100>;
261
174
interrupts = <0 53 0x04>;
175
+
#address-cells = <1>;
176
+
#size-cells = <0>;
177
+
status = "disabled";
178
+
};
179
+
180
+
spi@7000d400 {
181
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
182
+
reg = <0x7000d400 0x200>;
183
+
interrupts = <0 59 0x04>;
184
+
nvidia,dma-request-selector = <&apbdma 15>;
185
+
#address-cells = <1>;
186
+
#size-cells = <0>;
187
+
status = "disabled";
188
+
};
189
+
190
+
spi@7000d600 {
191
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
192
+
reg = <0x7000d600 0x200>;
193
+
interrupts = <0 82 0x04>;
194
+
nvidia,dma-request-selector = <&apbdma 16>;
195
+
#address-cells = <1>;
196
+
#size-cells = <0>;
197
+
status = "disabled";
198
+
};
199
+
200
+
spi@7000d800 {
201
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
202
+
reg = <0x7000d480 0x200>;
203
+
interrupts = <0 83 0x04>;
204
+
nvidia,dma-request-selector = <&apbdma 17>;
205
+
#address-cells = <1>;
206
+
#size-cells = <0>;
207
+
status = "disabled";
208
+
};
209
+
210
+
spi@7000da00 {
211
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
212
+
reg = <0x7000da00 0x200>;
213
+
interrupts = <0 93 0x04>;
214
+
nvidia,dma-request-selector = <&apbdma 18>;
215
+
#address-cells = <1>;
216
+
#size-cells = <0>;
217
+
status = "disabled";
218
+
};
219
+
220
+
spi@7000dc00 {
221
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
222
+
reg = <0x7000dc00 0x200>;
223
+
interrupts = <0 94 0x04>;
224
+
nvidia,dma-request-selector = <&apbdma 27>;
225
+
#address-cells = <1>;
226
+
#size-cells = <0>;
227
+
status = "disabled";
228
+
};
229
+
230
+
spi@7000de00 {
231
+
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
232
+
reg = <0x7000de00 0x200>;
233
+
interrupts = <0 79 0x04>;
234
+
nvidia,dma-request-selector = <&apbdma 28>;
262
235
#address-cells = <1>;
263
236
#size-cells = <0>;
264
237
status = "disabled";
+72
arch/arm/boot/dts/u9540.dts
+72
arch/arm/boot/dts/u9540.dts
···
1
+
/*
2
+
* Copyright 2012 ST-Ericsson AB
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "dbx5x0.dtsi"
14
+
15
+
/ {
16
+
model = "ST-Ericsson U9540 platform with Device Tree";
17
+
compatible = "st-ericsson,u9540";
18
+
19
+
memory {
20
+
reg = <0x00000000 0x20000000>;
21
+
};
22
+
23
+
soc-u9500 {
24
+
uart@80120000 {
25
+
status = "okay";
26
+
};
27
+
28
+
uart@80121000 {
29
+
status = "okay";
30
+
};
31
+
32
+
uart@80007000 {
33
+
status = "okay";
34
+
};
35
+
36
+
// External Micro SD slot
37
+
sdi0_per1@80126000 {
38
+
arm,primecell-periphid = <0x10480180>;
39
+
max-frequency = <100000000>;
40
+
bus-width = <4>;
41
+
mmc-cap-sd-highspeed;
42
+
mmc-cap-mmc-highspeed;
43
+
vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
+
45
+
cd-gpios = <&gpio7 6 0x4>; // 230
46
+
cd-inverted;
47
+
48
+
status = "okay";
49
+
};
50
+
51
+
52
+
// WLAN SDIO channel
53
+
sdi1_per2@80118000 {
54
+
arm,primecell-periphid = <0x10480180>;
55
+
max-frequency = <50000000>;
56
+
bus-width = <4>;
57
+
58
+
status = "okay";
59
+
};
60
+
61
+
// On-board eMMC
62
+
sdi4_per2@80114000 {
63
+
arm,primecell-periphid = <0x10480180>;
64
+
max-frequency = <100000000>;
65
+
bus-width = <8>;
66
+
mmc-cap-mmc-highspeed;
67
+
vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
+
69
+
status = "okay";
70
+
};
71
+
};
72
+
};
+166
arch/arm/boot/dts/zynq-7000.dtsi
+166
arch/arm/boot/dts/zynq-7000.dtsi
···
1
+
/*
2
+
* Copyright (C) 2011 Xilinx
3
+
*
4
+
* This software is licensed under the terms of the GNU General Public
5
+
* License version 2, as published by the Free Software Foundation, and
6
+
* may be copied, distributed, and modified under those terms.
7
+
*
8
+
* This program is distributed in the hope that it will be useful,
9
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
+
* GNU General Public License for more details.
12
+
*/
13
+
/include/ "skeleton.dtsi"
14
+
15
+
/ {
16
+
compatible = "xlnx,zynq-7000";
17
+
18
+
amba {
19
+
compatible = "simple-bus";
20
+
#address-cells = <1>;
21
+
#size-cells = <1>;
22
+
interrupt-parent = <&intc>;
23
+
ranges;
24
+
25
+
intc: interrupt-controller@f8f01000 {
26
+
compatible = "arm,cortex-a9-gic";
27
+
#interrupt-cells = <3>;
28
+
#address-cells = <1>;
29
+
interrupt-controller;
30
+
reg = <0xF8F01000 0x1000>,
31
+
<0xF8F00100 0x100>;
32
+
};
33
+
34
+
L2: cache-controller {
35
+
compatible = "arm,pl310-cache";
36
+
reg = <0xF8F02000 0x1000>;
37
+
arm,data-latency = <2 3 2>;
38
+
arm,tag-latency = <2 3 2>;
39
+
cache-unified;
40
+
cache-level = <2>;
41
+
};
42
+
43
+
uart0: uart@e0000000 {
44
+
compatible = "xlnx,xuartps";
45
+
reg = <0xE0000000 0x1000>;
46
+
interrupts = <0 27 4>;
47
+
clock = <50000000>;
48
+
};
49
+
50
+
uart1: uart@e0001000 {
51
+
compatible = "xlnx,xuartps";
52
+
reg = <0xE0001000 0x1000>;
53
+
interrupts = <0 50 4>;
54
+
clock = <50000000>;
55
+
};
56
+
57
+
slcr: slcr@f8000000 {
58
+
compatible = "xlnx,zynq-slcr";
59
+
reg = <0xF8000000 0x1000>;
60
+
61
+
clocks {
62
+
#address-cells = <1>;
63
+
#size-cells = <0>;
64
+
65
+
ps_clk: ps_clk {
66
+
#clock-cells = <0>;
67
+
compatible = "fixed-clock";
68
+
/* clock-frequency set in board-specific file */
69
+
clock-output-names = "ps_clk";
70
+
};
71
+
armpll: armpll {
72
+
#clock-cells = <0>;
73
+
compatible = "xlnx,zynq-pll";
74
+
clocks = <&ps_clk>;
75
+
reg = <0x100 0x110>;
76
+
clock-output-names = "armpll";
77
+
};
78
+
ddrpll: ddrpll {
79
+
#clock-cells = <0>;
80
+
compatible = "xlnx,zynq-pll";
81
+
clocks = <&ps_clk>;
82
+
reg = <0x104 0x114>;
83
+
clock-output-names = "ddrpll";
84
+
};
85
+
iopll: iopll {
86
+
#clock-cells = <0>;
87
+
compatible = "xlnx,zynq-pll";
88
+
clocks = <&ps_clk>;
89
+
reg = <0x108 0x118>;
90
+
clock-output-names = "iopll";
91
+
};
92
+
uart_clk: uart_clk {
93
+
#clock-cells = <1>;
94
+
compatible = "xlnx,zynq-periph-clock";
95
+
clocks = <&iopll &armpll &ddrpll>;
96
+
reg = <0x154>;
97
+
clock-output-names = "uart0_ref_clk",
98
+
"uart1_ref_clk";
99
+
};
100
+
cpu_clk: cpu_clk {
101
+
#clock-cells = <1>;
102
+
compatible = "xlnx,zynq-cpu-clock";
103
+
clocks = <&iopll &armpll &ddrpll>;
104
+
reg = <0x120 0x1C4>;
105
+
clock-output-names = "cpu_6x4x",
106
+
"cpu_3x2x",
107
+
"cpu_2x",
108
+
"cpu_1x";
109
+
};
110
+
};
111
+
};
112
+
113
+
ttc0: ttc0@f8001000 {
114
+
#address-cells = <1>;
115
+
#size-cells = <0>;
116
+
compatible = "xlnx,ttc";
117
+
reg = <0xF8001000 0x1000>;
118
+
clocks = <&cpu_clk 3>;
119
+
clock-names = "cpu_1x";
120
+
clock-ranges;
121
+
122
+
ttc0_0: ttc0.0 {
123
+
status = "disabled";
124
+
reg = <0>;
125
+
interrupts = <0 10 4>;
126
+
};
127
+
ttc0_1: ttc0.1 {
128
+
status = "disabled";
129
+
reg = <1>;
130
+
interrupts = <0 11 4>;
131
+
};
132
+
ttc0_2: ttc0.2 {
133
+
status = "disabled";
134
+
reg = <2>;
135
+
interrupts = <0 12 4>;
136
+
};
137
+
};
138
+
139
+
ttc1: ttc1@f8002000 {
140
+
#interrupt-parent = <&intc>;
141
+
#address-cells = <1>;
142
+
#size-cells = <0>;
143
+
compatible = "xlnx,ttc";
144
+
reg = <0xF8002000 0x1000>;
145
+
clocks = <&cpu_clk 3>;
146
+
clock-names = "cpu_1x";
147
+
clock-ranges;
148
+
149
+
ttc1_0: ttc1.0 {
150
+
status = "disabled";
151
+
reg = <0>;
152
+
interrupts = <0 37 4>;
153
+
};
154
+
ttc1_1: ttc1.1 {
155
+
status = "disabled";
156
+
reg = <1>;
157
+
interrupts = <0 38 4>;
158
+
};
159
+
ttc1_2: ttc1.2 {
160
+
status = "disabled";
161
+
reg = <2>;
162
+
interrupts = <0 39 4>;
163
+
};
164
+
};
165
+
};
166
+
};
-63
arch/arm/boot/dts/zynq-ep107.dts
-63
arch/arm/boot/dts/zynq-ep107.dts
···
1
-
/*
2
-
* Copyright (C) 2011 Xilinx
3
-
*
4
-
* This software is licensed under the terms of the GNU General Public
5
-
* License version 2, as published by the Free Software Foundation, and
6
-
* may be copied, distributed, and modified under those terms.
7
-
*
8
-
* This program is distributed in the hope that it will be useful,
9
-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10
-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11
-
* GNU General Public License for more details.
12
-
*/
13
-
14
-
/dts-v1/;
15
-
/ {
16
-
model = "Xilinx Zynq EP107";
17
-
compatible = "xlnx,zynq-ep107";
18
-
#address-cells = <1>;
19
-
#size-cells = <1>;
20
-
interrupt-parent = <&intc>;
21
-
22
-
memory {
23
-
device_type = "memory";
24
-
reg = <0x0 0x10000000>;
25
-
};
26
-
27
-
chosen {
28
-
bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
29
-
linux,stdout-path = &uart0;
30
-
};
31
-
32
-
amba {
33
-
compatible = "simple-bus";
34
-
#address-cells = <1>;
35
-
#size-cells = <1>;
36
-
ranges;
37
-
38
-
intc: interrupt-controller@f8f01000 {
39
-
compatible = "arm,cortex-a9-gic";
40
-
#interrupt-cells = <3>;
41
-
#address-cells = <1>;
42
-
interrupt-controller;
43
-
reg = <0xF8F01000 0x1000>,
44
-
<0xF8F00100 0x100>;
45
-
};
46
-
47
-
L2: cache-controller {
48
-
compatible = "arm,pl310-cache";
49
-
reg = <0xF8F02000 0x1000>;
50
-
arm,data-latency = <2 3 2>;
51
-
arm,tag-latency = <2 3 2>;
52
-
cache-unified;
53
-
cache-level = <2>;
54
-
};
55
-
56
-
uart0: uart@e0000000 {
57
-
compatible = "xlnx,xuartps";
58
-
reg = <0xE0000000 0x1000>;
59
-
interrupts = <0 27 4>;
60
-
clock = <50000000>;
61
-
};
62
-
};
63
-
};
+44
arch/arm/boot/dts/zynq-zc702.dts
+44
arch/arm/boot/dts/zynq-zc702.dts
···
1
+
/*
2
+
* Copyright (C) 2011 Xilinx
3
+
* Copyright (C) 2012 National Instruments Corp.
4
+
*
5
+
* This software is licensed under the terms of the GNU General Public
6
+
* License version 2, as published by the Free Software Foundation, and
7
+
* may be copied, distributed, and modified under those terms.
8
+
*
9
+
* This program is distributed in the hope that it will be useful,
10
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
+
* GNU General Public License for more details.
13
+
*/
14
+
/dts-v1/;
15
+
/include/ "zynq-7000.dtsi"
16
+
17
+
/ {
18
+
model = "Zynq ZC702 Development Board";
19
+
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
+
21
+
memory {
22
+
device_type = "memory";
23
+
reg = <0x0 0x40000000>;
24
+
};
25
+
26
+
chosen {
27
+
bootargs = "console=ttyPS1,115200 earlyprintk";
28
+
};
29
+
30
+
};
31
+
32
+
&ps_clk {
33
+
clock-frequency = <33333330>;
34
+
};
35
+
36
+
&ttc0_0 {
37
+
status = "ok";
38
+
compatible = "xlnx,ttc-counter-clocksource";
39
+
};
40
+
41
+
&ttc0_1 {
42
+
status = "ok";
43
+
compatible = "xlnx,ttc-counter-clockevent";
44
+
};
+6
arch/arm/configs/mxs_defconfig
+6
arch/arm/configs/mxs_defconfig
···
61
61
CONFIG_NETDEVICES=y
62
62
CONFIG_NET_ETHERNET=y
63
63
CONFIG_ENC28J60=y
64
+
CONFIG_USB_USBNET=y
65
+
CONFIG_USB_NET_SMSC95XX=y
64
66
# CONFIG_NETDEV_1000 is not set
65
67
# CONFIG_NETDEV_10000 is not set
66
68
# CONFIG_WLAN is not set
···
160
158
CONFIG_NFS_V3_ACL=y
161
159
CONFIG_NFS_V4=y
162
160
CONFIG_ROOT_NFS=y
161
+
CONFIG_NLS_CODEPAGE_437=y
162
+
CONFIG_NLS_CODEPAGE_850=y
163
+
CONFIG_NLS_ISO8859_1=y
164
+
CONFIG_NLS_ISO8859_15=y
163
165
CONFIG_PRINTK_TIME=y
164
166
CONFIG_FRAME_WARN=2048
165
167
CONFIG_MAGIC_SYSRQ=y
+1
arch/arm/configs/u8500_defconfig
+1
arch/arm/configs/u8500_defconfig
+16
-4
arch/arm/include/debug/imx.S
+16
-4
arch/arm/include/debug/imx.S
···
10
10
* published by the Free Software Foundation.
11
11
*
12
12
*/
13
+
#define IMX6Q_UART1_BASE_ADDR 0x02020000
14
+
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
15
+
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
16
+
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
17
+
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
18
+
19
+
/*
20
+
* IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
21
+
* of IMX6Q_UART##n##_BASE_ADDR.
22
+
*/
23
+
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
24
+
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
25
+
#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
26
+
13
27
#ifdef CONFIG_DEBUG_IMX1_UART
14
28
#define UART_PADDR 0x00206000
15
29
#elif defined (CONFIG_DEBUG_IMX25_UART)
···
36
22
#define UART_PADDR 0x73fbc000
37
23
#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
38
24
#define UART_PADDR 0x53fbc000
39
-
#elif defined (CONFIG_DEBUG_IMX6Q_UART2)
40
-
#define UART_PADDR 0x021e8000
41
-
#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
42
-
#define UART_PADDR 0x021f0000
25
+
#elif defined (CONFIG_DEBUG_IMX6Q_UART)
26
+
#define UART_PADDR IMX6Q_DEBUG_UART_BASE
43
27
#endif
44
28
45
29
/*
-2
arch/arm/mach-davinci/Makefile.boot
-2
arch/arm/mach-davinci/Makefile.boot
+1
arch/arm/mach-exynos/Kconfig
+1
arch/arm/mach-exynos/Kconfig
-1
arch/arm/mach-exynos/Makefile
-1
arch/arm/mach-exynos/Makefile
···
52
52
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53
53
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
54
54
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
55
-
obj-$(CONFIG_EXYNOS_DEV_DRM) += dev-drm.o
56
55
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
57
56
58
57
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
+4
arch/arm/mach-exynos/clock-exynos4.c
+4
arch/arm/mach-exynos/clock-exynos4.c
···
576
576
.enable = exynos4_clk_ip_peril_ctrl,
577
577
.ctrlbit = (1 << 15),
578
578
}, {
579
+
.name = "tmu_apbif",
580
+
.enable = exynos4_clk_ip_perir_ctrl,
581
+
.ctrlbit = (1 << 17),
582
+
}, {
579
583
.name = "keypad",
580
584
.enable = exynos4_clk_ip_perir_ctrl,
581
585
.ctrlbit = (1 << 16),
+18
-3
arch/arm/mach-exynos/clock-exynos5.c
+18
-3
arch/arm/mach-exynos/clock-exynos5.c
···
196
196
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
197
197
}
198
198
199
+
static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
200
+
{
201
+
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
202
+
}
203
+
199
204
/* Core list of CMU_CPU side */
200
205
201
206
static struct clksrc_clk exynos5_clk_mout_apll = {
···
621
616
.enable = exynos5_clk_ip_peric_ctrl,
622
617
.ctrlbit = (1 << 24),
623
618
}, {
619
+
.name = "tmu_apbif",
620
+
.parent = &exynos5_clk_aclk_66.clk,
621
+
.enable = exynos5_clk_ip_peris_ctrl,
622
+
.ctrlbit = (1 << 21),
623
+
}, {
624
624
.name = "rtc",
625
625
.parent = &exynos5_clk_aclk_66.clk,
626
626
.enable = exynos5_clk_ip_peris_ctrl,
···
674
664
.ctrlbit = (1 << 25),
675
665
}, {
676
666
.name = "mfc",
677
-
.devname = "s5p-mfc",
667
+
.devname = "s5p-mfc-v6",
678
668
.enable = exynos5_clk_ip_mfc_ctrl,
679
669
.ctrlbit = (1 << 0),
680
670
}, {
681
671
.name = "hdmi",
682
-
.devname = "exynos4-hdmi",
672
+
.devname = "exynos5-hdmi",
683
673
.enable = exynos5_clk_ip_disp1_ctrl,
684
674
.ctrlbit = (1 << 6),
685
675
}, {
676
+
.name = "hdmiphy",
677
+
.devname = "exynos5-hdmi",
678
+
.enable = exynos5_clk_hdmiphy_ctrl,
679
+
.ctrlbit = (1 << 0),
680
+
}, {
686
681
.name = "mixer",
687
-
.devname = "s5p-mixer",
682
+
.devname = "exynos5-mixer",
688
683
.enable = exynos5_clk_ip_disp1_ctrl,
689
684
.ctrlbit = (1 << 5),
690
685
}, {
+5
-2
arch/arm/mach-exynos/common.c
+5
-2
arch/arm/mach-exynos/common.c
···
1020
1020
* platforms switch over to using the pinctrl driver, the wakeup
1021
1021
* interrupt support code here can be completely removed.
1022
1022
*/
1023
+
static const struct of_device_id exynos_pinctrl_ids[] = {
1024
+
{ .compatible = "samsung,pinctrl-exynos4210", },
1025
+
{ .compatible = "samsung,pinctrl-exynos4x12", },
1026
+
};
1023
1027
struct device_node *pctrl_np, *wkup_np;
1024
-
const char *pctrl_compat = "samsung,pinctrl-exynos4210";
1025
1028
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1026
1029
1027
-
for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
1030
+
for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
1028
1031
if (of_device_is_available(pctrl_np)) {
1029
1032
wkup_np = of_find_compatible_node(pctrl_np, NULL,
1030
1033
wkup_compat);
-29
arch/arm/mach-exynos/dev-drm.c
-29
arch/arm/mach-exynos/dev-drm.c
···
1
-
/*
2
-
* linux/arch/arm/mach-exynos/dev-drm.c
3
-
*
4
-
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
5
-
* http://www.samsung.com
6
-
*
7
-
* EXYNOS - core DRM device
8
-
*
9
-
* This program is free software; you can redistribute it and/or modify
10
-
* it under the terms of the GNU General Public License as published by
11
-
* the Free Software Foundation; either version 2 of the License, or
12
-
* (at your option) any later version.
13
-
*/
14
-
15
-
#include <linux/kernel.h>
16
-
#include <linux/dma-mapping.h>
17
-
#include <linux/platform_device.h>
18
-
19
-
#include <plat/devs.h>
20
-
21
-
static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
22
-
23
-
struct platform_device exynos_device_drm = {
24
-
.name = "exynos-drm",
25
-
.dev = {
26
-
.dma_mask = &exynos_drm_dma_mask,
27
-
.coherent_dma_mask = DMA_BIT_MASK(32),
28
-
}
29
-
};
+3
arch/arm/mach-exynos/include/mach/irqs.h
+3
arch/arm/mach-exynos/include/mach/irqs.h
···
136
136
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
137
137
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
138
138
139
+
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
140
+
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
141
+
139
142
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
140
143
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
141
144
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
+2
arch/arm/mach-exynos/include/mach/map.h
+2
arch/arm/mach-exynos/include/mach/map.h
+4
arch/arm/mach-exynos/mach-exynos4-dt.c
+4
arch/arm/mach-exynos/mach-exynos4-dt.c
···
78
78
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
79
79
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
80
80
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
81
+
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
82
+
"exynos-tmu", NULL),
81
83
{},
82
84
};
83
85
···
97
95
98
96
static char const *exynos4_dt_compat[] __initdata = {
99
97
"samsung,exynos4210",
98
+
"samsung,exynos4212",
99
+
"samsung,exynos4412",
100
100
NULL
101
101
};
102
102
+42
arch/arm/mach-exynos/mach-exynos5-dt.c
+42
arch/arm/mach-exynos/mach-exynos5-dt.c
···
12
12
#include <linux/of_platform.h>
13
13
#include <linux/of_fdt.h>
14
14
#include <linux/serial_core.h>
15
+
#include <linux/memblock.h>
16
+
#include <linux/of_fdt.h>
15
17
16
18
#include <asm/mach/arch.h>
17
19
#include <asm/hardware/gic.h>
···
21
19
22
20
#include <plat/cpu.h>
23
21
#include <plat/regs-serial.h>
22
+
#include <plat/mfc.h>
24
23
25
24
#include "common.h"
26
25
···
51
48
"s3c2440-i2c.0", NULL),
52
49
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
53
50
"s3c2440-i2c.1", NULL),
51
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
52
+
"s3c2440-i2c.2", NULL),
53
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
54
+
"s3c2440-i2c.3", NULL),
55
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
56
+
"s3c2440-i2c.4", NULL),
57
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
58
+
"s3c2440-i2c.5", NULL),
59
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
60
+
"s3c2440-i2c.6", NULL),
61
+
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
62
+
"s3c2440-i2c.7", NULL),
63
+
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
64
+
"s3c2440-hdmiphy-i2c", NULL),
54
65
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
55
66
"dw_mmc.0", NULL),
56
67
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
···
79
62
"exynos4210-spi.1", NULL),
80
63
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
81
64
"exynos4210-spi.2", NULL),
65
+
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
66
+
"exynos5-sata", NULL),
67
+
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
68
+
"exynos5-sata-phy", NULL),
69
+
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
70
+
"exynos5-sata-phy-i2c", NULL),
82
71
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
83
72
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
84
73
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
···
96
73
"exynos-gsc.2", NULL),
97
74
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
98
75
"exynos-gsc.3", NULL),
76
+
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
77
+
"exynos5-hdmi", NULL),
78
+
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
79
+
"exynos5-mixer", NULL),
80
+
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
81
+
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
82
+
"exynos-tmu", NULL),
99
83
{},
100
84
};
101
85
···
138
108
NULL
139
109
};
140
110
111
+
static void __init exynos5_reserve(void)
112
+
{
113
+
struct s5p_mfc_dt_meminfo mfc_mem;
114
+
115
+
/* Reserve memory for MFC only if it's available */
116
+
mfc_mem.compatible = "samsung,mfc-v6";
117
+
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
118
+
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
119
+
mfc_mem.lsize);
120
+
}
121
+
141
122
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
142
123
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
143
124
.init_irq = exynos5_init_irq,
···
160
119
.timer = &exynos4_timer,
161
120
.dt_compat = exynos5_dt_compat,
162
121
.restart = exynos5_restart,
122
+
.reserve = exynos5_reserve,
163
123
MACHINE_END
-3
arch/arm/mach-exynos/mach-nuri.c
-3
arch/arm/mach-exynos/mach-nuri.c
-3
arch/arm/mach-exynos/mach-origen.c
-3
arch/arm/mach-exynos/mach-origen.c
-3
arch/arm/mach-exynos/mach-smdk4x12.c
-3
arch/arm/mach-exynos/mach-smdk4x12.c
-3
arch/arm/mach-exynos/mach-smdkv310.c
-3
arch/arm/mach-exynos/mach-smdkv310.c
-3
arch/arm/mach-exynos/mach-universal_c210.c
-3
arch/arm/mach-exynos/mach-universal_c210.c
+89
-4
arch/arm/mach-exynos/pm_domains.c
+89
-4
arch/arm/mach-exynos/pm_domains.c
···
19
19
#include <linux/pm_domain.h>
20
20
#include <linux/delay.h>
21
21
#include <linux/of_address.h>
22
+
#include <linux/of_platform.h>
23
+
#include <linux/sched.h>
22
24
23
25
#include <mach/regs-pmu.h>
24
26
#include <plat/devs.h>
···
85
83
}
86
84
87
85
#ifdef CONFIG_OF
86
+
static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
87
+
struct device *dev)
88
+
{
89
+
int ret;
90
+
91
+
dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
92
+
93
+
while (1) {
94
+
ret = pm_genpd_add_device(&pd->pd, dev);
95
+
if (ret != -EAGAIN)
96
+
break;
97
+
cond_resched();
98
+
}
99
+
100
+
pm_genpd_dev_need_restore(dev, true);
101
+
}
102
+
103
+
static void exynos_remove_device_from_domain(struct device *dev)
104
+
{
105
+
struct generic_pm_domain *genpd = dev_to_genpd(dev);
106
+
int ret;
107
+
108
+
dev_dbg(dev, "removing from power domain %s\n", genpd->name);
109
+
110
+
while (1) {
111
+
ret = pm_genpd_remove_device(genpd, dev);
112
+
if (ret != -EAGAIN)
113
+
break;
114
+
cond_resched();
115
+
}
116
+
}
117
+
118
+
static void exynos_read_domain_from_dt(struct device *dev)
119
+
{
120
+
struct platform_device *pd_pdev;
121
+
struct exynos_pm_domain *pd;
122
+
struct device_node *node;
123
+
124
+
node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
125
+
if (!node)
126
+
return;
127
+
pd_pdev = of_find_device_by_node(node);
128
+
if (!pd_pdev)
129
+
return;
130
+
pd = platform_get_drvdata(pd_pdev);
131
+
exynos_add_device_to_domain(pd, dev);
132
+
}
133
+
134
+
static int exynos_pm_notifier_call(struct notifier_block *nb,
135
+
unsigned long event, void *data)
136
+
{
137
+
struct device *dev = data;
138
+
139
+
switch (event) {
140
+
case BUS_NOTIFY_BIND_DRIVER:
141
+
if (dev->of_node)
142
+
exynos_read_domain_from_dt(dev);
143
+
144
+
break;
145
+
146
+
case BUS_NOTIFY_UNBOUND_DRIVER:
147
+
exynos_remove_device_from_domain(dev);
148
+
149
+
break;
150
+
}
151
+
return NOTIFY_DONE;
152
+
}
153
+
154
+
static struct notifier_block platform_nb = {
155
+
.notifier_call = exynos_pm_notifier_call,
156
+
};
157
+
88
158
static __init int exynos_pm_dt_parse_domains(void)
89
159
{
160
+
struct platform_device *pdev;
90
161
struct device_node *np;
91
162
92
163
for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
93
164
struct exynos_pm_domain *pd;
165
+
int on;
166
+
167
+
pdev = of_find_device_by_node(np);
94
168
95
169
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
96
170
if (!pd) {
···
175
97
return -ENOMEM;
176
98
}
177
99
178
-
if (of_get_property(np, "samsung,exynos4210-pd-off", NULL))
179
-
pd->is_off = true;
180
-
pd->name = np->name;
100
+
pd->pd.name = kstrdup(np->name, GFP_KERNEL);
101
+
pd->name = pd->pd.name;
181
102
pd->base = of_iomap(np, 0);
182
103
pd->pd.power_off = exynos_pd_power_off;
183
104
pd->pd.power_on = exynos_pd_power_on;
184
105
pd->pd.of_node = np;
185
-
pm_genpd_init(&pd->pd, NULL, false);
106
+
107
+
platform_set_drvdata(pdev, pd);
108
+
109
+
on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
110
+
111
+
pm_genpd_init(&pd->pd, NULL, !on);
186
112
}
113
+
114
+
bus_register_notifier(&platform_bus_type, &platform_nb);
115
+
187
116
return 0;
188
117
}
189
118
#else
+18
arch/arm/mach-imx/Kconfig
+18
arch/arm/mach-imx/Kconfig
···
272
272
273
273
endchoice
274
274
275
+
config MACH_IMX25_DT
276
+
bool "Support i.MX25 platforms from device tree"
277
+
select SOC_IMX25
278
+
help
279
+
Include support for Freescale i.MX25 based platforms
280
+
using the device tree for discovery
281
+
275
282
comment "MX27 platforms:"
276
283
277
284
config MACH_MX27ADS
···
838
831
839
832
config SOC_IMX6Q
840
833
bool "i.MX6 Quad support"
834
+
select ARCH_HAS_CPUFREQ
835
+
select ARCH_HAS_OPP
841
836
select ARM_CPU_SUSPEND if PM
837
+
select ARM_ERRATA_743622
838
+
select ARM_ERRATA_751472
839
+
select ARM_ERRATA_754322
840
+
select ARM_ERRATA_764369 if SMP
841
+
select ARM_ERRATA_775420
842
842
select ARM_GIC
843
843
select COMMON_CLK
844
844
select CPU_V7
···
857
843
select MFD_SYSCON
858
844
select PINCTRL
859
845
select PINCTRL_IMX6Q
846
+
select PL310_ERRATA_588369 if CACHE_PL310
847
+
select PL310_ERRATA_727915 if CACHE_PL310
848
+
select PL310_ERRATA_769419 if CACHE_PL310
849
+
select PM_OPP if PM
860
850
861
851
help
862
852
This enables support for Freescale i.MX6 Quad processor.
+1
arch/arm/mach-imx/Makefile
+1
arch/arm/mach-imx/Makefile
···
50
50
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
51
51
obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o
52
52
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
53
+
obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
53
54
54
55
# i.MX27 based machines
55
56
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
+107
-12
arch/arm/mach-imx/clk-imx25.c
+107
-12
arch/arm/mach-imx/clk-imx25.c
···
23
23
#include <linux/io.h>
24
24
#include <linux/clkdev.h>
25
25
#include <linux/err.h>
26
+
#include <linux/of.h>
27
+
#include <linux/of_address.h>
28
+
#include <linux/of_irq.h>
26
29
27
30
#include "clk.h"
28
31
#include "common.h"
···
58
55
59
56
#define ccm(x) (CRM_BASE + (x))
60
57
58
+
static struct clk_onecell_data clk_data;
59
+
61
60
static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
62
61
static const char *per_sel_clks[] = { "ahb", "upll", };
63
62
···
69
64
per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
70
65
per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
71
66
per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
72
-
csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
73
-
lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
74
-
csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
75
-
usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
76
-
cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
77
-
kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
78
-
ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
79
-
uart4_ipg, uart5_ipg, wdt_ipg, clk_max
67
+
csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
68
+
gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
69
+
pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
70
+
uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
71
+
esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
72
+
reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
73
+
cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
74
+
reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
75
+
gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
76
+
iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
77
+
pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
78
+
sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
79
+
uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
80
+
wdt_ipg, clk_max
80
81
};
81
82
82
83
static struct clk *clk[clk_max];
83
84
84
-
int __init mx25_clocks_init(void)
85
+
static int __init __mx25_clocks_init(unsigned long osc_rate)
85
86
{
86
87
int i;
87
88
88
89
clk[dummy] = imx_clk_fixed("dummy", 0);
89
-
clk[osc] = imx_clk_fixed("osc", 24000000);
90
+
clk[osc] = imx_clk_fixed("osc", osc_rate);
90
91
clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
91
92
clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
92
93
clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
···
134
123
clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
135
124
clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
136
125
clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
126
+
clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1);
127
+
clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2);
137
128
clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
138
129
clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
139
130
clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
140
131
clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
141
132
clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
142
133
clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
134
+
clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9);
135
+
clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10);
136
+
clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11);
137
+
clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12);
143
138
clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
144
139
clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
145
140
clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
141
+
clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
142
+
/* CCM_CGCR0(17): reserved */
146
143
clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
144
+
clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
145
+
clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
147
146
clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
148
147
clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
149
148
clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
150
149
clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
150
+
clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
151
151
clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
152
+
clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
152
153
clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
154
+
/* CCM_CGCR0(29-31): reserved */
155
+
/* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
153
156
clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
154
157
clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
155
158
clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
···
171
146
clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
172
147
clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
173
148
clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
149
+
clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9);
150
+
clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10);
151
+
clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11);
152
+
/* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
174
153
clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
175
154
clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
176
155
clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
156
+
/* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
157
+
/* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
158
+
/* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
159
+
clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
160
+
clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
161
+
clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
162
+
clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
163
+
/* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
164
+
/* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
165
+
/* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
177
166
clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
167
+
/* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
168
+
/* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
178
169
clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
179
170
clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
171
+
/* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
180
172
clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
181
173
clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
182
174
clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
183
175
clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
176
+
clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3);
177
+
/* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
178
+
clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5);
184
179
clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
180
+
clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7);
181
+
clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8);
182
+
clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9);
183
+
clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10);
185
184
clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
186
185
clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
187
186
clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
···
214
165
clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
215
166
clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
216
167
clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
168
+
/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
217
169
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
218
170
219
171
for (i = 0; i < ARRAY_SIZE(clk); i++)
220
172
if (IS_ERR(clk[i]))
221
173
pr_err("i.MX25 clk %d: register failed with %ld\n",
222
174
i, PTR_ERR(clk[i]));
175
+
176
+
clk_prepare_enable(clk[emi_ahb]);
177
+
178
+
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
179
+
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
180
+
181
+
return 0;
182
+
}
183
+
184
+
int __init mx25_clocks_init(void)
185
+
{
186
+
__mx25_clocks_init(24000000);
223
187
224
188
/* i.mx25 has the i.mx21 type uart */
225
189
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
···
245
183
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
246
184
clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
247
185
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
248
-
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
249
-
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
250
186
clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
251
187
clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
252
188
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
···
302
242
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
303
243
304
244
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
245
+
246
+
return 0;
247
+
}
248
+
249
+
int __init mx25_clocks_init_dt(void)
250
+
{
251
+
struct device_node *np;
252
+
void __iomem *base;
253
+
int irq;
254
+
unsigned long osc_rate = 24000000;
255
+
256
+
/* retrieve the freqency of fixed clocks from device tree */
257
+
for_each_compatible_node(np, NULL, "fixed-clock") {
258
+
u32 rate;
259
+
if (of_property_read_u32(np, "clock-frequency", &rate))
260
+
continue;
261
+
262
+
if (of_device_is_compatible(np, "fsl,imx-osc"))
263
+
osc_rate = rate;
264
+
}
265
+
266
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
267
+
clk_data.clks = clk;
268
+
clk_data.clk_num = ARRAY_SIZE(clk);
269
+
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
270
+
271
+
__mx25_clocks_init(osc_rate);
272
+
273
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
274
+
base = of_iomap(np, 0);
275
+
WARN_ON(!base);
276
+
irq = irq_of_parse_and_map(np, 0);
277
+
278
+
mxc_timer_init(base, irq);
279
+
305
280
return 0;
306
281
}
+1
arch/arm/mach-imx/clk-imx6q.c
+1
arch/arm/mach-imx/clk-imx6q.c
···
424
424
clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
425
425
clk_register_clkdev(clk[ahb], "ahb", NULL);
426
426
clk_register_clkdev(clk[cko1], "cko1", NULL);
427
+
clk_register_clkdev(clk[arm], NULL, "cpu0");
427
428
428
429
/*
429
430
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
+1
arch/arm/mach-imx/common.h
+1
arch/arm/mach-imx/common.h
···
66
66
unsigned long ckih1, unsigned long ckih2);
67
67
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
68
68
unsigned long ckih1, unsigned long ckih2);
69
+
extern int mx25_clocks_init_dt(void);
69
70
extern int mx27_clocks_init_dt(void);
70
71
extern int mx31_clocks_init_dt(void);
71
72
extern int mx51_clocks_init_dt(void);
+48
arch/arm/mach-imx/imx25-dt.c
+48
arch/arm/mach-imx/imx25-dt.c
···
1
+
/*
2
+
* Copyright 2012 Sascha Hauer, Pengutronix
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/irq.h>
13
+
#include <linux/of_irq.h>
14
+
#include <linux/of_platform.h>
15
+
#include <asm/mach/arch.h>
16
+
#include <asm/mach/time.h>
17
+
#include "common.h"
18
+
#include "mx25.h"
19
+
20
+
static void __init imx25_dt_init(void)
21
+
{
22
+
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23
+
}
24
+
25
+
static void __init imx25_timer_init(void)
26
+
{
27
+
mx25_clocks_init_dt();
28
+
}
29
+
30
+
static struct sys_timer imx25_timer = {
31
+
.init = imx25_timer_init,
32
+
};
33
+
34
+
static const char * const imx25_dt_board_compat[] __initconst = {
35
+
"fsl,imx25",
36
+
NULL
37
+
};
38
+
39
+
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
40
+
.map_io = mx25_map_io,
41
+
.init_early = imx25_init_early,
42
+
.init_irq = mx25_init_irq,
43
+
.handle_irq = imx25_handle_irq,
44
+
.timer = &imx25_timer,
45
+
.init_machine = imx25_dt_init,
46
+
.dt_compat = imx25_dt_board_compat,
47
+
.restart = mxc_restart,
48
+
MACHINE_END
+18
-10
arch/arm/mach-imx/lluart.c
+18
-10
arch/arm/mach-imx/lluart.c
···
17
17
18
18
#include "hardware.h"
19
19
20
+
#define IMX6Q_UART1_BASE_ADDR 0x02020000
21
+
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
22
+
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
23
+
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
24
+
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
25
+
26
+
/*
27
+
* IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
28
+
* of IMX6Q_UART##n##_BASE_ADDR.
29
+
*/
30
+
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
31
+
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
32
+
#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
33
+
20
34
static struct map_desc imx_lluart_desc = {
21
-
#ifdef CONFIG_DEBUG_IMX6Q_UART2
22
-
.virtual = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR),
23
-
.pfn = __phys_to_pfn(MX6Q_UART2_BASE_ADDR),
24
-
.length = MX6Q_UART2_SIZE,
25
-
.type = MT_DEVICE,
26
-
#endif
27
-
#ifdef CONFIG_DEBUG_IMX6Q_UART4
28
-
.virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
29
-
.pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
30
-
.length = MX6Q_UART4_SIZE,
35
+
#ifdef CONFIG_DEBUG_IMX6Q_UART
36
+
.virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
37
+
.pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
38
+
.length = 0x4000,
31
39
.type = MT_DEVICE,
32
40
#endif
33
41
};
+35
arch/arm/mach-imx/mach-imx6q.c
+35
arch/arm/mach-imx/mach-imx6q.c
···
38
38
#include "cpuidle.h"
39
39
#include "hardware.h"
40
40
41
+
#define IMX6Q_ANALOG_DIGPROG 0x260
42
+
43
+
static int imx6q_revision(void)
44
+
{
45
+
struct device_node *np;
46
+
void __iomem *base;
47
+
static u32 rev;
48
+
49
+
if (!rev) {
50
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
51
+
if (!np)
52
+
return IMX_CHIP_REVISION_UNKNOWN;
53
+
base = of_iomap(np, 0);
54
+
if (!base) {
55
+
of_node_put(np);
56
+
return IMX_CHIP_REVISION_UNKNOWN;
57
+
}
58
+
rev = readl_relaxed(base + IMX6Q_ANALOG_DIGPROG);
59
+
iounmap(base);
60
+
of_node_put(np);
61
+
}
62
+
63
+
switch (rev & 0xff) {
64
+
case 0:
65
+
return IMX_CHIP_REVISION_1_0;
66
+
case 1:
67
+
return IMX_CHIP_REVISION_1_1;
68
+
case 2:
69
+
return IMX_CHIP_REVISION_1_2;
70
+
default:
71
+
return IMX_CHIP_REVISION_UNKNOWN;
72
+
}
73
+
}
74
+
41
75
void imx6q_restart(char mode, const char *cmd)
42
76
{
43
77
struct device_node *np;
···
238
204
{
239
205
mx6q_clocks_init();
240
206
twd_local_timer_of_register();
207
+
imx_print_silicon_rev("i.MX6Q", imx6q_revision());
241
208
}
242
209
243
210
static struct sys_timer imx6q_timer = {
-4
arch/arm/mach-imx/mx6q.h
-4
arch/arm/mach-imx/mx6q.h
···
27
27
#define MX6Q_CCM_SIZE 0x4000
28
28
#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29
29
#define MX6Q_ANATOP_SIZE 0x1000
30
-
#define MX6Q_UART2_BASE_ADDR 0x021e8000
31
-
#define MX6Q_UART2_SIZE 0x4000
32
-
#define MX6Q_UART4_BASE_ADDR 0x021f0000
33
-
#define MX6Q_UART4_SIZE 0x4000
34
30
35
31
#endif /* __MACH_MX6Q_H__ */
+5
arch/arm/mach-kirkwood/Kconfig
+5
arch/arm/mach-kirkwood/Kconfig
···
46
46
47
47
config ARCH_KIRKWOOD_DT
48
48
bool "Marvell Kirkwood Flattened Device Tree"
49
+
select POWER_SUPPLY
50
+
select POWER_RESET
51
+
select POWER_RESET_GPIO
52
+
select REGULATOR
53
+
select REGULATOR_FIXED_VOLTAGE
49
54
select USE_OF
50
55
help
51
56
Say 'Y' here if you want your kernel to support the
-54
arch/arm/mach-kirkwood/board-dnskw.c
-54
arch/arm/mach-kirkwood/board-dnskw.c
···
17
17
#include <linux/mv643xx_eth.h>
18
18
#include <linux/gpio.h>
19
19
#include "common.h"
20
-
#include "mpp.h"
21
20
22
21
static struct mv643xx_eth_platform_data dnskw_ge00_data = {
23
22
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
24
23
};
25
-
26
-
static unsigned int dnskw_mpp_config[] __initdata = {
27
-
MPP13_UART1_TXD, /* Custom ... */
28
-
MPP14_UART1_RXD, /* ... Controller (DNS-320 only) */
29
-
MPP20_SATA1_ACTn, /* LED: White Right HDD */
30
-
MPP21_SATA0_ACTn, /* LED: White Left HDD */
31
-
MPP24_GPIO,
32
-
MPP25_GPIO,
33
-
MPP26_GPIO, /* LED: Power */
34
-
MPP27_GPIO, /* LED: Red Right HDD */
35
-
MPP28_GPIO, /* LED: Red Left HDD */
36
-
MPP29_GPIO, /* LED: Red USB (DNS-325 only) */
37
-
MPP30_GPIO,
38
-
MPP31_GPIO,
39
-
MPP32_GPIO,
40
-
MPP33_GPO,
41
-
MPP34_GPIO, /* Button: Front power */
42
-
MPP35_GPIO, /* LED: Red USB (DNS-320 only) */
43
-
MPP36_GPIO, /* Power: Turn off board */
44
-
MPP37_GPIO, /* Power: Turn back on after power failure */
45
-
MPP38_GPIO,
46
-
MPP39_GPIO, /* Power: SATA0 */
47
-
MPP40_GPIO, /* Power: SATA1 */
48
-
MPP41_GPIO, /* SATA0 present */
49
-
MPP42_GPIO, /* SATA1 present */
50
-
MPP43_GPIO, /* LED: White USB */
51
-
MPP44_GPIO, /* Fan: Tachometer Pin */
52
-
MPP45_GPIO, /* Fan: high speed */
53
-
MPP46_GPIO, /* Fan: low speed */
54
-
MPP47_GPIO, /* Button: Back unmount */
55
-
MPP48_GPIO, /* Button: Back reset */
56
-
MPP49_GPIO, /* Temp Alarm (DNS-325) Pin of U5 (DNS-320) */
57
-
0
58
-
};
59
-
60
-
static void dnskw_power_off(void)
61
-
{
62
-
gpio_set_value(36, 1);
63
-
}
64
24
65
25
/* Register any GPIO for output and set the value */
66
26
static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
···
36
76
37
77
void __init dnskw_init(void)
38
78
{
39
-
kirkwood_mpp_conf(dnskw_mpp_config);
40
-
41
-
kirkwood_ehci_init();
42
79
kirkwood_ge00_init(&dnskw_ge00_data);
43
-
44
-
/* Register power-off GPIO. */
45
-
if (gpio_request(36, "dnskw:power:off") == 0
46
-
&& gpio_direction_output(36, 0) == 0)
47
-
pm_power_off = dnskw_power_off;
48
-
else
49
-
pr_err("dnskw: failed to configure power-off GPIO\n");
50
-
51
-
/* Ensure power is supplied to both HDDs */
52
-
dnskw_gpio_register(39, "dnskw:power:sata0", 1);
53
-
dnskw_gpio_register(40, "dnskw:power:sata1", 1);
54
80
55
81
/* Set NAS to turn back on after a power failure */
56
82
dnskw_gpio_register(37, "dnskw:power:recover", 1);
-16
arch/arm/mach-kirkwood/board-dockstar.c
-16
arch/arm/mach-kirkwood/board-dockstar.c
···
17
17
#include <linux/kernel.h>
18
18
#include <linux/init.h>
19
19
#include <linux/mv643xx_eth.h>
20
-
#include <linux/gpio.h>
21
20
#include "common.h"
22
-
#include "mpp.h"
23
21
24
22
static struct mv643xx_eth_platform_data dockstar_ge00_data = {
25
23
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
26
-
};
27
-
28
-
static unsigned int dockstar_mpp_config[] __initdata = {
29
-
MPP29_GPIO, /* USB Power Enable */
30
-
MPP46_GPIO, /* LED green */
31
-
MPP47_GPIO, /* LED orange */
32
-
0
33
24
};
34
25
35
26
void __init dockstar_dt_init(void)
···
28
37
/*
29
38
* Basic setup. Needs to be called early.
30
39
*/
31
-
kirkwood_mpp_conf(dockstar_mpp_config);
32
-
33
-
if (gpio_request(29, "USB Power Enable") != 0 ||
34
-
gpio_direction_output(29, 1) != 0)
35
-
pr_err("can't setup GPIO 29 (USB Power Enable)\n");
36
-
kirkwood_ehci_init();
37
-
38
40
kirkwood_ge00_init(&dockstar_ge00_data);
39
41
}
-15
arch/arm/mach-kirkwood/board-dreamplug.c
-15
arch/arm/mach-kirkwood/board-dreamplug.c
···
17
17
#include <linux/gpio.h>
18
18
#include <linux/platform_data/mmc-mvsdio.h>
19
19
#include "common.h"
20
-
#include "mpp.h"
21
20
22
21
static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
23
22
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
···
30
31
/* unfortunately the CD signal has not been connected */
31
32
};
32
33
33
-
static unsigned int dreamplug_mpp_config[] __initdata = {
34
-
MPP0_SPI_SCn,
35
-
MPP1_SPI_MOSI,
36
-
MPP2_SPI_SCK,
37
-
MPP3_SPI_MISO,
38
-
MPP47_GPIO, /* Bluetooth LED */
39
-
MPP48_GPIO, /* Wifi LED */
40
-
MPP49_GPIO, /* Wifi AP LED */
41
-
0
42
-
};
43
-
44
34
void __init dreamplug_init(void)
45
35
{
46
36
/*
47
37
* Basic setup. Needs to be called early.
48
38
*/
49
-
kirkwood_mpp_conf(dreamplug_mpp_config);
50
-
51
-
kirkwood_ehci_init();
52
39
kirkwood_ge00_init(&dreamplug_ge00_data);
53
40
kirkwood_ge01_init(&dreamplug_ge01_data);
54
41
kirkwood_sdio_init(&dreamplug_mvsdio_data);
-24
arch/arm/mach-kirkwood/board-goflexnet.c
-24
arch/arm/mach-kirkwood/board-goflexnet.c
···
19
19
#include <linux/kernel.h>
20
20
#include <linux/init.h>
21
21
#include <linux/mv643xx_eth.h>
22
-
#include <linux/gpio.h>
23
22
#include "common.h"
24
-
#include "mpp.h"
25
23
26
24
static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
27
25
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
28
-
};
29
-
30
-
static unsigned int goflexnet_mpp_config[] __initdata = {
31
-
MPP29_GPIO, /* USB Power Enable */
32
-
MPP47_GPIO, /* LED Orange */
33
-
MPP46_GPIO, /* LED Green */
34
-
MPP45_GPIO, /* LED Left Capacity 3 */
35
-
MPP44_GPIO, /* LED Left Capacity 2 */
36
-
MPP43_GPIO, /* LED Left Capacity 1 */
37
-
MPP42_GPIO, /* LED Left Capacity 0 */
38
-
MPP41_GPIO, /* LED Right Capacity 3 */
39
-
MPP40_GPIO, /* LED Right Capacity 2 */
40
-
MPP39_GPIO, /* LED Right Capacity 1 */
41
-
MPP38_GPIO, /* LED Right Capacity 0 */
42
-
0
43
26
};
44
27
45
28
void __init goflexnet_init(void)
···
30
47
/*
31
48
* Basic setup. Needs to be called early.
32
49
*/
33
-
kirkwood_mpp_conf(goflexnet_mpp_config);
34
-
35
-
if (gpio_request(29, "USB Power Enable") != 0 ||
36
-
gpio_direction_output(29, 1) != 0)
37
-
pr_err("can't setup GPIO 29 (USB Power Enable)\n");
38
-
kirkwood_ehci_init();
39
-
40
50
kirkwood_ge00_init(&goflexnet_ge00_data);
41
51
}
-35
arch/arm/mach-kirkwood/board-ib62x0.c
-35
arch/arm/mach-kirkwood/board-ib62x0.c
···
14
14
#include <linux/kernel.h>
15
15
#include <linux/init.h>
16
16
#include <linux/mv643xx_eth.h>
17
-
#include <linux/gpio.h>
18
17
#include <linux/input.h>
19
18
#include "common.h"
20
-
#include "mpp.h"
21
-
22
-
#define IB62X0_GPIO_POWER_OFF 24
23
19
24
20
static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
25
21
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
26
22
};
27
-
28
-
static unsigned int ib62x0_mpp_config[] __initdata = {
29
-
MPP0_NF_IO2,
30
-
MPP1_NF_IO3,
31
-
MPP2_NF_IO4,
32
-
MPP3_NF_IO5,
33
-
MPP4_NF_IO6,
34
-
MPP5_NF_IO7,
35
-
MPP18_NF_IO0,
36
-
MPP19_NF_IO1,
37
-
MPP22_GPIO, /* OS LED red */
38
-
MPP24_GPIO, /* Power off device */
39
-
MPP25_GPIO, /* OS LED green */
40
-
MPP27_GPIO, /* USB transfer LED */
41
-
MPP28_GPIO, /* Reset button */
42
-
MPP29_GPIO, /* USB Copy button */
43
-
0
44
-
};
45
-
46
-
static void ib62x0_power_off(void)
47
-
{
48
-
gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
49
-
}
50
23
51
24
void __init ib62x0_init(void)
52
25
{
53
26
/*
54
27
* Basic setup. Needs to be called early.
55
28
*/
56
-
kirkwood_mpp_conf(ib62x0_mpp_config);
57
-
58
-
kirkwood_ehci_init();
59
29
kirkwood_ge00_init(&ib62x0_ge00_data);
60
-
if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
61
-
gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
62
-
pm_power_off = ib62x0_power_off;
63
-
else
64
-
pr_err("board-ib62x0: failed to configure power-off GPIO\n");
65
30
}
-18
arch/arm/mach-kirkwood/board-iconnect.c
-18
arch/arm/mach-kirkwood/board-iconnect.c
···
13
13
#include <linux/of.h>
14
14
#include <linux/mv643xx_eth.h>
15
15
#include "common.h"
16
-
#include "mpp.h"
17
16
18
17
static struct mv643xx_eth_platform_data iconnect_ge00_data = {
19
18
.phy_addr = MV643XX_ETH_PHY_ADDR(11),
20
19
};
21
20
22
-
static unsigned int iconnect_mpp_config[] __initdata = {
23
-
MPP12_GPIO,
24
-
MPP35_GPIO,
25
-
MPP41_GPIO,
26
-
MPP42_GPIO,
27
-
MPP43_GPIO,
28
-
MPP44_GPIO,
29
-
MPP45_GPIO,
30
-
MPP46_GPIO,
31
-
MPP47_GPIO,
32
-
MPP48_GPIO,
33
-
0
34
-
};
35
-
36
21
void __init iconnect_init(void)
37
22
{
38
-
kirkwood_mpp_conf(iconnect_mpp_config);
39
-
40
-
kirkwood_ehci_init();
41
23
kirkwood_ge00_init(&iconnect_ge00_data);
42
24
}
43
25
-26
arch/arm/mach-kirkwood/board-iomega_ix2_200.c
-26
arch/arm/mach-kirkwood/board-iomega_ix2_200.c
···
13
13
#include <linux/mv643xx_eth.h>
14
14
#include <linux/ethtool.h>
15
15
#include "common.h"
16
-
#include "mpp.h"
17
16
18
17
static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
19
18
.phy_addr = MV643XX_ETH_PHY_NONE,
···
20
21
.duplex = DUPLEX_FULL,
21
22
};
22
23
23
-
static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
24
-
MPP12_GPIO, /* Reset Button */
25
-
MPP14_GPIO, /* Power Button */
26
-
MPP15_GPIO, /* Backup LED (blue) */
27
-
MPP16_GPIO, /* Power LED (white) */
28
-
MPP35_GPIO, /* OTB Button */
29
-
MPP36_GPIO, /* Rebuild LED (white) */
30
-
MPP37_GPIO, /* Health LED (red) */
31
-
MPP38_GPIO, /* SATA LED brightness control 1 */
32
-
MPP39_GPIO, /* SATA LED brightness control 2 */
33
-
MPP40_GPIO, /* Backup LED brightness control 1 */
34
-
MPP41_GPIO, /* Backup LED brightness control 2 */
35
-
MPP42_GPIO, /* Power LED brightness control 1 */
36
-
MPP43_GPIO, /* Power LED brightness control 2 */
37
-
MPP44_GPIO, /* Health LED brightness control 1 */
38
-
MPP45_GPIO, /* Health LED brightness control 2 */
39
-
MPP46_GPIO, /* Rebuild LED brightness control 1 */
40
-
MPP47_GPIO, /* Rebuild LED brightness control 2 */
41
-
0
42
-
};
43
-
44
24
void __init iomega_ix2_200_init(void)
45
25
{
46
26
/*
47
27
* Basic setup. Needs to be called early.
48
28
*/
49
-
kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
50
-
51
-
kirkwood_ehci_init();
52
-
53
29
kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
54
30
}
-13
arch/arm/mach-kirkwood/board-km_kirkwood.c
-13
arch/arm/mach-kirkwood/board-km_kirkwood.c
···
18
18
#include <linux/clk.h>
19
19
#include <linux/clk-private.h>
20
20
#include "common.h"
21
-
#include "mpp.h"
22
21
23
22
static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
24
23
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
25
24
};
26
25
27
-
static unsigned int km_kirkwood_mpp_config[] __initdata = {
28
-
MPP8_GPIO, /* I2C SDA */
29
-
MPP9_GPIO, /* I2C SCL */
30
-
0
31
-
};
32
-
33
26
void __init km_kirkwood_init(void)
34
27
{
35
28
struct clk *sata_clk;
36
-
/*
37
-
* Basic setup. Needs to be called early.
38
-
*/
39
-
kirkwood_mpp_conf(km_kirkwood_mpp_config);
40
-
41
29
/*
42
30
* Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
43
31
* SATA bits (14-15) of the Clock Gating Control Register. Since these
···
40
52
if (!IS_ERR(sata_clk))
41
53
sata_clk->flags |= CLK_IGNORE_UNUSED;
42
54
43
-
kirkwood_ehci_init();
44
55
kirkwood_ge00_init(&km_kirkwood_ge00_data);
45
56
}
-28
arch/arm/mach-kirkwood/board-lsxl.c
-28
arch/arm/mach-kirkwood/board-lsxl.c
···
15
15
#include <linux/init.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/mv643xx_eth.h>
18
-
#include <linux/gpio.h>
19
18
#include "common.h"
20
-
#include "mpp.h"
21
19
22
20
static struct mv643xx_eth_platform_data lsxl_ge00_data = {
23
21
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
···
23
25
24
26
static struct mv643xx_eth_platform_data lsxl_ge01_data = {
25
27
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
26
-
};
27
-
28
-
static unsigned int lsxl_mpp_config[] __initdata = {
29
-
MPP10_GPO, /* HDD Power Enable */
30
-
MPP11_GPIO, /* USB Vbus Enable */
31
-
MPP18_GPO, /* FAN High Enable# */
32
-
MPP19_GPO, /* FAN Low Enable# */
33
-
MPP36_GPIO, /* Function Blue LED */
34
-
MPP37_GPIO, /* Alarm LED */
35
-
MPP38_GPIO, /* Info LED */
36
-
MPP39_GPIO, /* Power LED */
37
-
MPP40_GPIO, /* Fan Lock */
38
-
MPP41_GPIO, /* Function Button */
39
-
MPP42_GPIO, /* Power Switch */
40
-
MPP43_GPIO, /* Power Auto Switch */
41
-
MPP48_GPIO, /* Function Red LED */
42
-
0
43
28
};
44
29
45
30
/*
···
38
57
kirkwood_restart('h', NULL);
39
58
}
40
59
41
-
#define LSXL_GPIO_HDD_POWER 10
42
-
#define LSXL_GPIO_USB_POWER 11
43
-
44
60
void __init lsxl_init(void)
45
61
{
46
62
/*
47
63
* Basic setup. Needs to be called early.
48
64
*/
49
-
kirkwood_mpp_conf(lsxl_mpp_config);
50
65
51
-
/* usb and sata power on */
52
-
gpio_set_value(LSXL_GPIO_USB_POWER, 1);
53
-
gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
54
-
55
-
kirkwood_ehci_init();
56
66
kirkwood_ge00_init(&lsxl_ge00_data);
57
67
kirkwood_ge01_init(&lsxl_ge01_data);
58
68
-36
arch/arm/mach-kirkwood/board-mplcec4.c
-36
arch/arm/mach-kirkwood/board-mplcec4.c
···
24
24
.phy_addr = MV643XX_ETH_PHY_ADDR(2),
25
25
};
26
26
27
-
static unsigned int mplcec4_mpp_config[] __initdata = {
28
-
MPP0_NF_IO2,
29
-
MPP1_NF_IO3,
30
-
MPP2_NF_IO4,
31
-
MPP3_NF_IO5,
32
-
MPP4_NF_IO6,
33
-
MPP5_NF_IO7,
34
-
MPP6_SYSRST_OUTn,
35
-
MPP7_GPO, /* Status LED Green High Active */
36
-
MPP10_UART0_TXD,
37
-
MPP11_UART0_RXD,
38
-
MPP12_SD_CLK,
39
-
MPP13_SD_CMD, /* Alt UART1_TXD */
40
-
MPP14_SD_D0, /* Alt UART1_RXD */
41
-
MPP15_SD_D1,
42
-
MPP16_SD_D2,
43
-
MPP17_SD_D3,
44
-
MPP18_NF_IO0,
45
-
MPP19_NF_IO1,
46
-
MPP28_GPIO, /* Input SYS_POR_DET (active High) */
47
-
MPP29_GPIO, /* Input SYS_RTC_INT (active High) */
48
-
MPP34_SATA1_ACTn,
49
-
MPP35_SATA0_ACTn,
50
-
MPP40_GPIO, /* LED User1 orange */
51
-
MPP41_GPIO, /* LED User1 green */
52
-
MPP44_GPIO, /* LED User0 orange */
53
-
MPP45_GPIO, /* LED User0 green */
54
-
MPP46_GPIO, /* Status LED Yellow High Active */
55
-
MPP47_GPIO, /* SD_CD# (in/IRQ)*/
56
-
0
57
-
};
58
-
59
-
60
27
static struct mvsdio_platform_data mplcec4_mvsdio_data = {
61
28
.gpio_card_detect = 47, /* MPP47 used as SD card detect */
62
29
};
63
-
64
30
65
31
66
32
void __init mplcec4_init(void)
···
34
68
/*
35
69
* Basic setup. Needs to be called early.
36
70
*/
37
-
kirkwood_mpp_conf(mplcec4_mpp_config);
38
-
kirkwood_ehci_init();
39
71
kirkwood_ge00_init(&mplcec4_ge00_data);
40
72
kirkwood_ge01_init(&mplcec4_ge01_data);
41
73
kirkwood_sdio_init(&mplcec4_mvsdio_data);
-1
arch/arm/mach-kirkwood/board-ns2.c
-1
arch/arm/mach-kirkwood/board-ns2.c
-4
arch/arm/mach-kirkwood/board-nsa310.c
-4
arch/arm/mach-kirkwood/board-nsa310.c
+2
-3
arch/arm/mach-kirkwood/board-openblocks_a6.c
+2
-3
arch/arm/mach-kirkwood/board-openblocks_a6.c
···
55
55
MPP38_GPIO, /* INIT */
56
56
MPP39_GPIO, /* USB OC */
57
57
MPP41_GPIO, /* LED: Red */
58
-
MPP42_GPIO, /* LED: Yellow */
59
-
MPP43_GPIO, /* LED: Green */
58
+
MPP42_GPIO, /* LED: Green */
59
+
MPP43_GPIO, /* LED: Yellow */
60
60
0,
61
61
};
62
62
···
66
66
* Basic setup. Needs to be called early.
67
67
*/
68
68
kirkwood_mpp_conf(openblocks_a6_mpp_config);
69
-
kirkwood_ehci_init();
70
69
kirkwood_ge00_init(&openblocks_ge00_data);
71
70
}
-26
arch/arm/mach-kirkwood/board-ts219.c
-26
arch/arm/mach-kirkwood/board-ts219.c
···
23
23
#include <asm/mach/arch.h>
24
24
#include <mach/kirkwood.h>
25
25
#include "common.h"
26
-
#include "mpp.h"
27
26
#include "tsx1x-common.h"
28
27
29
28
static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
30
29
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
31
30
};
32
31
33
-
static unsigned int qnap_ts219_mpp_config[] __initdata = {
34
-
MPP0_SPI_SCn,
35
-
MPP1_SPI_MOSI,
36
-
MPP2_SPI_SCK,
37
-
MPP3_SPI_MISO,
38
-
MPP4_SATA1_ACTn,
39
-
MPP5_SATA0_ACTn,
40
-
MPP8_TW0_SDA,
41
-
MPP9_TW0_SCK,
42
-
MPP10_UART0_TXD,
43
-
MPP11_UART0_RXD,
44
-
MPP13_UART1_TXD, /* PIC controller */
45
-
MPP14_UART1_RXD, /* PIC controller */
46
-
MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */
47
-
MPP16_GPIO, /* Reset button (on devices with 88F6281) */
48
-
MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
49
-
MPP37_GPIO, /* Reset button (on devices with 88F6282) */
50
-
MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */
51
-
MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
52
-
0
53
-
};
54
-
55
32
void __init qnap_dt_ts219_init(void)
56
33
{
57
34
u32 dev, rev;
58
-
59
-
kirkwood_mpp_conf(qnap_ts219_mpp_config);
60
35
61
36
kirkwood_pcie_id(&dev, &rev);
62
37
if (dev == MV88F6282_DEV_ID)
63
38
qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
64
39
65
40
kirkwood_ge00_init(&qnap_ts219_ge00_data);
66
-
kirkwood_ehci_init();
67
41
68
42
pm_power_off = qnap_tsx1x_power_off;
69
43
}
-1
arch/arm/mach-kirkwood/board-usi_topkick.c
-1
arch/arm/mach-kirkwood/board-usi_topkick.c
+56
arch/arm/mach-mxs/mach-mxs.c
+56
arch/arm/mach-mxs/mach-mxs.c
···
100
100
},
101
101
};
102
102
103
+
static struct fb_videomode apf28dev_video_modes[] = {
104
+
{
105
+
.name = "LW700",
106
+
.refresh = 60,
107
+
.xres = 800,
108
+
.yres = 480,
109
+
.pixclock = 30303, /* picosecond */
110
+
.left_margin = 96,
111
+
.right_margin = 96, /* at least 3 & 1 */
112
+
.upper_margin = 0x14,
113
+
.lower_margin = 0x15,
114
+
.hsync_len = 64,
115
+
.vsync_len = 4,
116
+
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
117
+
FB_SYNC_DATA_ENABLE_HIGH_ACT |
118
+
FB_SYNC_DOTCLK_FAILING_ACT,
119
+
},
120
+
};
121
+
103
122
static struct mxsfb_platform_data mxsfb_pdata __initdata;
104
123
105
124
/*
···
179
160
enum mac_oui {
180
161
OUI_FSL,
181
162
OUI_DENX,
163
+
OUI_CRYSTALFONTZ,
182
164
};
183
165
184
166
static void __init update_fec_mac_prop(enum mac_oui oui)
···
195
175
np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
196
176
if (!np)
197
177
return;
178
+
198
179
from = np;
180
+
181
+
if (of_get_property(np, "local-mac-address", NULL))
182
+
continue;
199
183
200
184
newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
201
185
if (!newmac)
···
228
204
macaddr[0] = 0xc0;
229
205
macaddr[1] = 0xe5;
230
206
macaddr[2] = 0x4e;
207
+
break;
208
+
case OUI_CRYSTALFONTZ:
209
+
macaddr[0] = 0x58;
210
+
macaddr[1] = 0xb9;
211
+
macaddr[2] = 0xe1;
231
212
break;
232
213
}
233
214
val = ocotp[i];
···
288
259
mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
289
260
mxsfb_pdata.default_bpp = 16;
290
261
mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
262
+
}
263
+
264
+
static void __init sc_sps1_init(void)
265
+
{
266
+
enable_clk_enet_out();
291
267
}
292
268
293
269
static int apx4devkit_phy_fixup(struct phy_device *phy)
···
389
355
pinctrl_put(pctl);
390
356
}
391
357
358
+
static void __init cfa10049_init(void)
359
+
{
360
+
enable_clk_enet_out();
361
+
update_fec_mac_prop(OUI_CRYSTALFONTZ);
362
+
}
363
+
364
+
static void __init apf28_init(void)
365
+
{
366
+
enable_clk_enet_out();
367
+
368
+
mxsfb_pdata.mode_list = apf28dev_video_modes;
369
+
mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
370
+
mxsfb_pdata.default_bpp = 16;
371
+
mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
372
+
}
373
+
392
374
static void __init mxs_machine_init(void)
393
375
{
394
376
if (of_machine_is_compatible("fsl,imx28-evk"))
···
415
365
m28evk_init();
416
366
else if (of_machine_is_compatible("bluegiga,apx4devkit"))
417
367
apx4devkit_init();
368
+
else if (of_machine_is_compatible("crystalfontz,cfa10049"))
369
+
cfa10049_init();
370
+
else if (of_machine_is_compatible("armadeus,imx28-apf28"))
371
+
apf28_init();
372
+
else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
373
+
sc_sps1_init();
418
374
419
375
of_platform_populate(NULL, of_default_bus_match_table,
420
376
mxs_auxdata_lookup, NULL);
+9
-1
arch/arm/mach-mxs/timer.c
+9
-1
arch/arm/mach-mxs/timer.c
···
29
29
#include <linux/of_irq.h>
30
30
31
31
#include <asm/mach/time.h>
32
+
#include <asm/sched_clock.h>
32
33
#include <mach/mxs.h>
33
34
#include <mach/common.h>
34
35
···
234
233
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
235
234
};
236
235
236
+
static u32 notrace mxs_read_sched_clock_v2(void)
237
+
{
238
+
return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
239
+
}
240
+
237
241
static int __init mxs_clocksource_init(struct clk *timer_clk)
238
242
{
239
243
unsigned int c = clk_get_rate(timer_clk);
240
244
241
245
if (timrot_is_v1())
242
246
clocksource_register_hz(&clocksource_mxs, c);
243
-
else
247
+
else {
244
248
clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
245
249
"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
250
+
setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
251
+
}
246
252
247
253
return 0;
248
254
}
-16
arch/arm/mach-ux500/board-mop500-audio.c
-16
arch/arm/mach-ux500/board-mop500-audio.c
···
149
149
},
150
150
};
151
151
152
-
/* Platform device for Ux500-PCM */
153
-
static struct platform_device ux500_pcm = {
154
-
.name = "ux500-pcm",
155
-
.id = 0,
156
-
.dev = {
157
-
.platform_data = NULL,
158
-
},
159
-
};
160
-
161
152
struct msp_i2s_platform_data msp2_platform_data = {
162
153
.id = MSP_I2S_2,
163
154
.msp_i2s_dma_rx = &msp2_dma_rx,
···
175
184
&msp2_platform_data);
176
185
db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
177
186
&msp3_platform_data);
178
-
}
179
-
180
-
/* Due for removal once the MSP driver has been fully DT:ed. */
181
-
void mop500_of_audio_init(struct device *parent)
182
-
{
183
-
pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
184
-
platform_device_register(&ux500_pcm);
185
187
}
+3
-19
arch/arm/mach-ux500/board-mop500-stuib.c
+3
-19
arch/arm/mach-ux500/board-mop500-stuib.c
···
162
162
.y_flip = true,
163
163
};
164
164
165
-
static struct bu21013_platform_device tsc_plat2_device = {
166
-
.cs_en = bu21013_gpio_board_init,
167
-
.cs_dis = bu21013_gpio_board_exit,
168
-
.irq_read_val = bu21013_read_pin_val,
169
-
.irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN),
170
-
.touch_x_max = TOUCH_XMAX,
171
-
.touch_y_max = TOUCH_YMAX,
172
-
.ext_clk = false,
173
-
.x_flip = false,
174
-
.y_flip = true,
175
-
};
176
-
177
165
static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
178
166
{
179
167
I2C_BOARD_INFO("bu21013_tp", 0x5C),
···
169
181
},
170
182
{
171
183
I2C_BOARD_INFO("bu21013_tp", 0x5D),
172
-
.platform_data = &tsc_plat2_device,
184
+
.platform_data = &tsc_plat_device,
173
185
},
174
186
175
187
};
176
188
177
189
void __init mop500_stuib_init(void)
178
190
{
179
-
if (machine_is_hrefv60()) {
191
+
if (machine_is_hrefv60())
180
192
tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
181
-
tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
182
-
} else {
193
+
else
183
194
tsc_plat_device.cs_pin = GPIO_BU21013_CS;
184
-
tsc_plat2_device.cs_pin = GPIO_BU21013_CS;
185
-
186
-
}
187
195
188
196
mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
189
197
ARRAY_SIZE(mop500_i2c0_devices_stuib));
+5
-141
arch/arm/mach-ux500/board-mop500.c
+5
-141
arch/arm/mach-ux500/board-mop500.c
···
33
33
#include <linux/smsc911x.h>
34
34
#include <linux/gpio_keys.h>
35
35
#include <linux/delay.h>
36
-
#include <linux/of.h>
37
-
#include <linux/of_platform.h>
38
36
#include <linux/leds.h>
39
37
#include <linux/pinctrl/consumer.h>
40
38
#include <linux/platform_data/pinctrl-nomadik.h>
···
523
525
};
524
526
#endif
525
527
526
-
static struct pl022_ssp_controller ssp0_plat = {
528
+
struct pl022_ssp_controller ssp0_plat = {
527
529
.bus_id = 0,
528
530
#ifdef CONFIG_STE_DMA40
529
531
.enable_dma = 1,
···
600
602
};
601
603
#endif
602
604
603
-
static struct amba_pl011_data uart0_plat = {
605
+
struct amba_pl011_data uart0_plat = {
604
606
#ifdef CONFIG_STE_DMA40
605
607
.dma_filter = stedma40_filter,
606
608
.dma_rx_param = &uart0_dma_cfg_rx,
···
608
610
#endif
609
611
};
610
612
611
-
static struct amba_pl011_data uart1_plat = {
613
+
struct amba_pl011_data uart1_plat = {
612
614
#ifdef CONFIG_STE_DMA40
613
615
.dma_filter = stedma40_filter,
614
616
.dma_rx_param = &uart1_dma_cfg_rx,
···
616
618
#endif
617
619
};
618
620
619
-
static struct amba_pl011_data uart2_plat = {
621
+
struct amba_pl011_data uart2_plat = {
620
622
#ifdef CONFIG_STE_DMA40
621
623
.dma_filter = stedma40_filter,
622
624
.dma_rx_param = &uart2_dma_cfg_rx,
···
679
681
680
682
/* This board has full regulator constraints */
681
683
regulator_has_full_constraints();
682
-
683
-
mop500_uib_init();
684
684
}
685
685
686
686
static void __init snowball_init_machine(void)
···
743
747
744
748
/* This board has full regulator constraints */
745
749
regulator_has_full_constraints();
746
-
747
-
mop500_uib_init();
748
750
}
749
751
750
752
MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
···
788
794
.timer = &ux500_timer,
789
795
.handle_irq = gic_handle_irq,
790
796
.init_machine = snowball_init_machine,
791
-
.init_late = ux500_init_late,
797
+
.init_late = NULL,
792
798
MACHINE_END
793
-
794
-
#ifdef CONFIG_MACH_UX500_DT
795
-
796
-
struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
797
-
/* Requires call-back bindings. */
798
-
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
799
-
/* Requires DMA and call-back bindings. */
800
-
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
801
-
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
802
-
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
803
-
/* Requires DMA bindings. */
804
-
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
805
-
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
806
-
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
807
-
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
808
-
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
809
-
/* Requires clock name bindings. */
810
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
811
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
812
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
813
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
814
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
815
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
816
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
817
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
818
-
OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
819
-
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
820
-
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
821
-
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
822
-
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
823
-
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
824
-
/* Requires device name bindings. */
825
-
OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
826
-
/* Requires clock name and DMA bindings. */
827
-
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
828
-
"ux500-msp-i2s.0", &msp0_platform_data),
829
-
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
830
-
"ux500-msp-i2s.1", &msp1_platform_data),
831
-
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
832
-
"ux500-msp-i2s.2", &msp2_platform_data),
833
-
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
834
-
"ux500-msp-i2s.3", &msp3_platform_data),
835
-
{},
836
-
};
837
-
838
-
static const struct of_device_id u8500_local_bus_nodes[] = {
839
-
/* only create devices below soc node */
840
-
{ .compatible = "stericsson,db8500", },
841
-
{ .compatible = "stericsson,db8500-prcmu", },
842
-
{ .compatible = "simple-bus"},
843
-
{ },
844
-
};
845
-
846
-
static void __init u8500_init_machine(void)
847
-
{
848
-
struct device *parent = NULL;
849
-
int i2c0_devs;
850
-
int i;
851
-
852
-
/* Pinmaps must be in place before devices register */
853
-
if (of_machine_is_compatible("st-ericsson,mop500"))
854
-
mop500_pinmaps_init();
855
-
else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
856
-
snowball_pinmaps_init();
857
-
else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
858
-
hrefv60_pinmaps_init();
859
-
860
-
parent = u8500_of_init_devices();
861
-
862
-
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
863
-
mop500_platform_devs[i]->dev.parent = parent;
864
-
865
-
/* automatically probe child nodes of db8500 device */
866
-
of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
867
-
868
-
if (of_machine_is_compatible("st-ericsson,mop500")) {
869
-
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
870
-
871
-
platform_add_devices(mop500_platform_devs,
872
-
ARRAY_SIZE(mop500_platform_devs));
873
-
874
-
mop500_sdi_init(parent);
875
-
mop500_audio_init(parent);
876
-
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
877
-
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
878
-
i2c_register_board_info(2, mop500_i2c2_devices,
879
-
ARRAY_SIZE(mop500_i2c2_devices));
880
-
881
-
mop500_uib_init();
882
-
883
-
} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
884
-
mop500_of_audio_init(parent);
885
-
} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
886
-
/*
887
-
* The HREFv60 board removed a GPIO expander and routed
888
-
* all these GPIO pins to the internal GPIO controller
889
-
* instead.
890
-
*/
891
-
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
892
-
platform_add_devices(mop500_platform_devs,
893
-
ARRAY_SIZE(mop500_platform_devs));
894
-
895
-
mop500_uib_init();
896
-
}
897
-
898
-
/* This board has full regulator constraints */
899
-
regulator_has_full_constraints();
900
-
}
901
-
902
-
static const char * u8500_dt_board_compat[] = {
903
-
"calaosystems,snowball-a9500",
904
-
"st-ericsson,hrefv60+",
905
-
"st-ericsson,u8500",
906
-
"st-ericsson,mop500",
907
-
NULL,
908
-
};
909
-
910
-
911
-
DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
912
-
.smp = smp_ops(ux500_smp_ops),
913
-
.map_io = u8500_map_io,
914
-
.init_irq = ux500_init_irq,
915
-
/* we re-use nomadik timer here */
916
-
.timer = &ux500_timer,
917
-
.handle_irq = gic_handle_irq,
918
-
.init_machine = u8500_init_machine,
919
-
.init_late = ux500_init_late,
920
-
.dt_compat = u8500_dt_board_compat,
921
-
MACHINE_END
922
-
#endif
+4
-6
arch/arm/mach-ux500/board-mop500.h
+4
-6
arch/arm/mach-ux500/board-mop500.h
···
89
89
extern struct msp_i2s_platform_data msp2_platform_data;
90
90
extern struct msp_i2s_platform_data msp3_platform_data;
91
91
extern struct arm_pmu_platdata db8500_pmu_platdata;
92
+
extern struct amba_pl011_data uart0_plat;
93
+
extern struct amba_pl011_data uart1_plat;
94
+
extern struct amba_pl011_data uart2_plat;
95
+
extern struct pl022_ssp_controller ssp0_plat;
92
96
93
97
extern void mop500_sdi_init(struct device *parent);
94
98
extern void snowball_sdi_init(struct device *parent);
···
104
100
void __init snowball_pinmaps_init(void);
105
101
void __init hrefv60_pinmaps_init(void);
106
102
void mop500_audio_init(struct device *parent);
107
-
/* Due for removal once the MSP driver has been fully DT:ed. */
108
-
void mop500_of_audio_init(struct device *parent);
109
103
110
104
int __init mop500_uib_init(void);
111
105
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
112
106
unsigned n);
113
-
114
-
/* TODO: Once all pieces are DT:ed, remove completely. */
115
-
struct device * __init u8500_of_init_devices(void);
116
-
117
107
#endif
+104
-7
arch/arm/mach-ux500/cpu-db8500.c
+104
-7
arch/arm/mach-ux500/cpu-db8500.c
···
17
17
#include <linux/platform_device.h>
18
18
#include <linux/io.h>
19
19
#include <linux/mfd/abx500/ab8500.h>
20
-
#include <linux/platform_data/usb-musb-ux500.h>
21
-
#include <linux/platform_data/pinctrl-nomadik.h>
20
+
#include <linux/mfd/dbx500-prcmu.h>
21
+
#include <linux/of.h>
22
+
#include <linux/of_platform.h>
23
+
#include <linux/regulator/machine.h>
22
24
#include <linux/random.h>
23
25
24
26
#include <asm/pmu.h>
25
27
#include <asm/mach/map.h>
28
+
#include <asm/mach/arch.h>
29
+
#include <asm/hardware/gic.h>
26
30
#include <mach/hardware.h>
27
31
#include <mach/setup.h>
28
32
#include <mach/devices.h>
···
34
30
35
31
#include "devices-db8500.h"
36
32
#include "ste-dma40-db8500.h"
33
+
#include "board-mop500.h"
37
34
38
35
/* minimum static i/o mapping required to boot U8500 platforms */
39
36
static struct map_desc u8500_uart_io_desc[] __initdata = {
···
232
227
return parent;
233
228
}
234
229
235
-
/* TODO: Once all pieces are DT:ed, remove completely. */
236
-
struct device * __init u8500_of_init_devices(void)
237
-
{
238
-
struct device *parent;
230
+
#ifdef CONFIG_MACH_UX500_DT
239
231
240
-
parent = db8500_soc_device_init();
232
+
/* TODO: Once all pieces are DT:ed, remove completely. */
233
+
static struct device * __init u8500_of_init_devices(void)
234
+
{
235
+
struct device *parent = db8500_soc_device_init();
241
236
242
237
db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
243
238
···
253
248
254
249
return parent;
255
250
}
251
+
252
+
static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
253
+
/* Requires call-back bindings. */
254
+
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
255
+
/* Requires DMA bindings. */
256
+
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
257
+
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
258
+
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
259
+
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
260
+
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
261
+
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
262
+
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
263
+
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
264
+
/* Requires clock name bindings. */
265
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
266
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
267
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
268
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
269
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
270
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
271
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
272
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
273
+
OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
274
+
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
275
+
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
276
+
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
277
+
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
278
+
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
279
+
/* Requires device name bindings. */
280
+
OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
281
+
/* Requires clock name and DMA bindings. */
282
+
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
283
+
"ux500-msp-i2s.0", &msp0_platform_data),
284
+
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
285
+
"ux500-msp-i2s.1", &msp1_platform_data),
286
+
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
287
+
"ux500-msp-i2s.2", &msp2_platform_data),
288
+
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
289
+
"ux500-msp-i2s.3", &msp3_platform_data),
290
+
{},
291
+
};
292
+
293
+
static const struct of_device_id u8500_local_bus_nodes[] = {
294
+
/* only create devices below soc node */
295
+
{ .compatible = "stericsson,db8500", },
296
+
{ .compatible = "stericsson,db8500-prcmu", },
297
+
{ .compatible = "simple-bus"},
298
+
{ },
299
+
};
300
+
301
+
static void __init u8500_init_machine(void)
302
+
{
303
+
struct device *parent = NULL;
304
+
305
+
/* Pinmaps must be in place before devices register */
306
+
if (of_machine_is_compatible("st-ericsson,mop500"))
307
+
mop500_pinmaps_init();
308
+
else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
309
+
snowball_pinmaps_init();
310
+
else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
311
+
hrefv60_pinmaps_init();
312
+
else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
313
+
/* TODO: Add pinmaps for ccu9540 board. */
314
+
315
+
/* TODO: Export SoC, USB, cpu-freq and DMA40 */
316
+
parent = u8500_of_init_devices();
317
+
318
+
/* automatically probe child nodes of db8500 device */
319
+
of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
320
+
}
321
+
322
+
static const char * stericsson_dt_platform_compat[] = {
323
+
"st-ericsson,u8500",
324
+
"st-ericsson,u8540",
325
+
"st-ericsson,u9500",
326
+
"st-ericsson,u9540",
327
+
NULL,
328
+
};
329
+
330
+
DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
331
+
.smp = smp_ops(ux500_smp_ops),
332
+
.map_io = u8500_map_io,
333
+
.init_irq = ux500_init_irq,
334
+
/* we re-use nomadik timer here */
335
+
.timer = &ux500_timer,
336
+
.handle_irq = gic_handle_irq,
337
+
.init_machine = u8500_init_machine,
338
+
.init_late = NULL,
339
+
.dt_compat = stericsson_dt_platform_compat,
340
+
MACHINE_END
341
+
342
+
#endif
+3
arch/arm/mach-ux500/cpu.c
+3
arch/arm/mach-ux500/cpu.c
···
26
26
#include <mach/setup.h>
27
27
#include <mach/devices.h>
28
28
29
+
#include "board-mop500.h"
30
+
29
31
void __iomem *_PRCMU_BASE;
30
32
31
33
/*
···
84
82
85
83
void __init ux500_init_late(void)
86
84
{
85
+
mop500_uib_init();
87
86
}
88
87
89
88
static const char * __init ux500_get_machine(void)
+29
-4
arch/arm/mach-zynq/common.c
+29
-4
arch/arm/mach-zynq/common.c
···
19
19
#include <linux/cpumask.h>
20
20
#include <linux/platform_device.h>
21
21
#include <linux/clk.h>
22
+
#include <linux/clk/zynq.h>
23
+
#include <linux/of_address.h>
22
24
#include <linux/of_irq.h>
23
25
#include <linux/of_platform.h>
24
26
#include <linux/of.h>
25
27
26
28
#include <asm/mach/arch.h>
27
29
#include <asm/mach/map.h>
30
+
#include <asm/mach/time.h>
28
31
#include <asm/mach-types.h>
29
32
#include <asm/page.h>
30
33
#include <asm/hardware/gic.h>
···
87
84
88
85
#ifdef CONFIG_DEBUG_LL
89
86
{
90
-
.virtual = UART0_VIRT,
91
-
.pfn = __phys_to_pfn(UART0_PHYS),
92
-
.length = UART0_SIZE,
87
+
.virtual = LL_UART_VADDR,
88
+
.pfn = __phys_to_pfn(LL_UART_PADDR),
89
+
.length = UART_SIZE,
93
90
.type = MT_DEVICE,
94
91
},
95
92
#endif
96
93
94
+
};
95
+
96
+
static void __init xilinx_zynq_timer_init(void)
97
+
{
98
+
struct device_node *np;
99
+
void __iomem *slcr;
100
+
101
+
np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
102
+
slcr = of_iomap(np, 0);
103
+
WARN_ON(!slcr);
104
+
105
+
xilinx_zynq_clocks_init(slcr);
106
+
107
+
xttcpss_timer_init();
108
+
}
109
+
110
+
/*
111
+
* Instantiate and initialize the system timer structure
112
+
*/
113
+
static struct sys_timer xttcpss_sys_timer = {
114
+
.init = xilinx_zynq_timer_init,
97
115
};
98
116
99
117
/**
···
126
102
}
127
103
128
104
static const char *xilinx_dt_match[] = {
129
-
"xlnx,zynq-ep107",
105
+
"xlnx,zynq-zc702",
106
+
"xlnx,zynq-7000",
130
107
NULL
131
108
};
132
109
+1
-3
arch/arm/mach-zynq/common.h
+1
-3
arch/arm/mach-zynq/common.h
+11
-5
arch/arm/mach-zynq/include/mach/zynq_soc.h
+11
-5
arch/arm/mach-zynq/include/mach/zynq_soc.h
···
25
25
* address that is known to work.
26
26
*/
27
27
#define UART0_PHYS 0xE0000000
28
-
#define UART0_SIZE SZ_4K
29
-
#define UART0_VIRT 0xF0001000
28
+
#define UART1_PHYS 0xE0001000
29
+
#define UART_SIZE SZ_4K
30
+
#define UART_VIRT 0xF0001000
30
31
31
32
#define TTC0_PHYS 0xF8001000
32
33
#define TTC0_SIZE SZ_4K
···
37
36
#define SCU_PERIPH_SIZE SZ_8K
38
37
#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE)
39
38
39
+
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
40
+
# define LL_UART_PADDR UART1_PHYS
41
+
#else
42
+
# define LL_UART_PADDR UART0_PHYS
43
+
#endif
44
+
45
+
#define LL_UART_VADDR UART_VIRT
46
+
40
47
/* The following are intended for the devices that are mapped early */
41
48
42
49
#define TTC0_BASE IOMEM(TTC0_VIRT)
43
50
#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
44
-
45
-
#define LL_UART_PADDR UART0_PHYS
46
-
#define LL_UART_VADDR UART0_VIRT
47
51
48
52
#endif
+162
-127
arch/arm/mach-zynq/timer.c
+162
-127
arch/arm/mach-zynq/timer.c
···
23
23
#include <linux/clocksource.h>
24
24
#include <linux/clockchips.h>
25
25
#include <linux/io.h>
26
+
#include <linux/of.h>
27
+
#include <linux/of_address.h>
28
+
#include <linux/of_irq.h>
29
+
#include <linux/slab.h>
30
+
#include <linux/clk-provider.h>
26
31
27
-
#include <asm/mach/time.h>
28
32
#include <mach/zynq_soc.h>
29
33
#include "common.h"
30
34
31
-
#define IRQ_TIMERCOUNTER0 42
32
-
33
-
/*
34
-
* This driver configures the 2 16-bit count-up timers as follows:
35
-
*
36
-
* T1: Timer 1, clocksource for generic timekeeping
37
-
* T2: Timer 2, clockevent source for hrtimers
38
-
* T3: Timer 3, <unused>
39
-
*
40
-
* The input frequency to the timer module for emulation is 2.5MHz which is
41
-
* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
42
-
* the timers are clocked at 78.125KHz (12.8 us resolution).
43
-
*
44
-
* The input frequency to the timer module in silicon will be 200MHz. With the
45
-
* pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
46
-
*/
47
-
#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
48
-
#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
49
-
50
-
#define XTTCPSS_TIMER_BASE TTC0_BASE
51
-
#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
52
35
/*
53
36
* Timer Register Offset Definitions of Timer 1, Increment base address by 4
54
37
* and use same offsets for Timer 2
···
48
65
49
66
#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
50
67
51
-
/* Setup the timers to use pre-scaling */
52
-
53
-
#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
68
+
/* Setup the timers to use pre-scaling, using a fixed value for now that will
69
+
* work across most input frequency, but it may need to be more dynamic
70
+
*/
71
+
#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
72
+
#define PRESCALE 2048 /* The exponent must match this */
73
+
#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
74
+
#define CLK_CNTRL_PRESCALE_EN 1
75
+
#define CNT_CNTRL_RESET (1<<4)
54
76
55
77
/**
56
78
* struct xttcpss_timer - This definition defines local timer structure
···
63
75
* @base_addr: Base address of timer
64
76
**/
65
77
struct xttcpss_timer {
66
-
void __iomem *base_addr;
78
+
void __iomem *base_addr;
67
79
};
68
80
69
-
static struct xttcpss_timer timers[2];
70
-
static struct clock_event_device xttcpss_clockevent;
81
+
struct xttcpss_timer_clocksource {
82
+
struct xttcpss_timer xttc;
83
+
struct clocksource cs;
84
+
};
85
+
86
+
#define to_xttcpss_timer_clksrc(x) \
87
+
container_of(x, struct xttcpss_timer_clocksource, cs)
88
+
89
+
struct xttcpss_timer_clockevent {
90
+
struct xttcpss_timer xttc;
91
+
struct clock_event_device ce;
92
+
struct clk *clk;
93
+
};
94
+
95
+
#define to_xttcpss_timer_clkevent(x) \
96
+
container_of(x, struct xttcpss_timer_clockevent, ce)
71
97
72
98
/**
73
99
* xttcpss_set_interval - Set the timer interval value
···
103
101
104
102
/* Reset the counter (0x10) so that it starts from 0, one-shot
105
103
mode makes this needed for timing to be right. */
106
-
ctrl_reg |= 0x10;
104
+
ctrl_reg |= CNT_CNTRL_RESET;
107
105
ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
108
106
__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
109
107
}
···
118
116
**/
119
117
static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
120
118
{
121
-
struct clock_event_device *evt = &xttcpss_clockevent;
122
-
struct xttcpss_timer *timer = dev_id;
119
+
struct xttcpss_timer_clockevent *xttce = dev_id;
120
+
struct xttcpss_timer *timer = &xttce->xttc;
123
121
124
122
/* Acknowledge the interrupt and call event handler */
125
123
__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
126
124
timer->base_addr + XTTCPSS_ISR_OFFSET);
127
125
128
-
evt->event_handler(evt);
126
+
xttce->ce.event_handler(&xttce->ce);
129
127
130
128
return IRQ_HANDLED;
131
129
}
132
130
133
-
static struct irqaction event_timer_irq = {
134
-
.name = "xttcpss clockevent",
135
-
.flags = IRQF_DISABLED | IRQF_TIMER,
136
-
.handler = xttcpss_clock_event_interrupt,
137
-
};
138
-
139
131
/**
140
-
* xttcpss_timer_hardware_init - Initialize the timer hardware
141
-
*
142
-
* Initialize the hardware to start the clock source, get the clock
143
-
* event timer ready to use, and hook up the interrupt.
144
-
**/
145
-
static void __init xttcpss_timer_hardware_init(void)
146
-
{
147
-
/* Setup the clock source counter to be an incrementing counter
148
-
* with no interrupt and it rolls over at 0xFFFF. Pre-scale
149
-
it by 32 also. Let it start running now.
150
-
*/
151
-
timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
152
-
153
-
__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
154
-
XTTCPSS_IER_OFFSET);
155
-
__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
156
-
XTTCPSS_CLK_CNTRL_OFFSET);
157
-
__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
158
-
XTTCPSS_CNT_CNTRL_OFFSET);
159
-
160
-
/* Setup the clock event timer to be an interval timer which
161
-
* is prescaled by 32 using the interval interrupt. Leave it
162
-
* disabled for now.
163
-
*/
164
-
165
-
timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
166
-
167
-
__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
168
-
XTTCPSS_CNT_CNTRL_OFFSET);
169
-
__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
170
-
XTTCPSS_CLK_CNTRL_OFFSET);
171
-
__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
172
-
XTTCPSS_IER_OFFSET);
173
-
174
-
/* Setup IRQ the clock event timer */
175
-
event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
176
-
setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
177
-
}
178
-
179
-
/**
180
-
* __raw_readl_cycles - Reads the timer counter register
132
+
* __xttc_clocksource_read - Reads the timer counter register
181
133
*
182
134
* returns: Current timer counter register value
183
135
**/
184
-
static cycle_t __raw_readl_cycles(struct clocksource *cs)
136
+
static cycle_t __xttc_clocksource_read(struct clocksource *cs)
185
137
{
186
-
struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
138
+
struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
187
139
188
140
return (cycle_t)__raw_readl(timer->base_addr +
189
141
XTTCPSS_COUNT_VAL_OFFSET);
190
142
}
191
-
192
-
193
-
/*
194
-
* Instantiate and initialize the clock source structure
195
-
*/
196
-
static struct clocksource clocksource_xttcpss = {
197
-
.name = "xttcpss_timer1",
198
-
.rating = 200, /* Reasonable clock source */
199
-
.read = __raw_readl_cycles,
200
-
.mask = CLOCKSOURCE_MASK(16),
201
-
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
202
-
};
203
-
204
143
205
144
/**
206
145
* xttcpss_set_next_event - Sets the time interval for next event
···
154
211
static int xttcpss_set_next_event(unsigned long cycles,
155
212
struct clock_event_device *evt)
156
213
{
157
-
struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
214
+
struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
215
+
struct xttcpss_timer *timer = &xttce->xttc;
158
216
159
217
xttcpss_set_interval(timer, cycles);
160
218
return 0;
···
170
226
static void xttcpss_set_mode(enum clock_event_mode mode,
171
227
struct clock_event_device *evt)
172
228
{
173
-
struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
229
+
struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
230
+
struct xttcpss_timer *timer = &xttce->xttc;
174
231
u32 ctrl_reg;
175
232
176
233
switch (mode) {
177
234
case CLOCK_EVT_MODE_PERIODIC:
178
-
xttcpss_set_interval(timer, TIMER_RATE / HZ);
235
+
xttcpss_set_interval(timer,
236
+
DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
237
+
PRESCALE * HZ));
179
238
break;
180
239
case CLOCK_EVT_MODE_ONESHOT:
181
240
case CLOCK_EVT_MODE_UNUSED:
···
199
252
}
200
253
}
201
254
202
-
/*
203
-
* Instantiate and initialize the clock event structure
204
-
*/
205
-
static struct clock_event_device xttcpss_clockevent = {
206
-
.name = "xttcpss_timer2",
207
-
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
208
-
.set_next_event = xttcpss_set_next_event,
209
-
.set_mode = xttcpss_set_mode,
210
-
.rating = 200,
255
+
static void __init zynq_ttc_setup_clocksource(struct device_node *np,
256
+
void __iomem *base)
257
+
{
258
+
struct xttcpss_timer_clocksource *ttccs;
259
+
struct clk *clk;
260
+
int err;
261
+
u32 reg;
262
+
263
+
ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
264
+
if (WARN_ON(!ttccs))
265
+
return;
266
+
267
+
err = of_property_read_u32(np, "reg", ®);
268
+
if (WARN_ON(err))
269
+
return;
270
+
271
+
clk = of_clk_get_by_name(np, "cpu_1x");
272
+
if (WARN_ON(IS_ERR(clk)))
273
+
return;
274
+
275
+
err = clk_prepare_enable(clk);
276
+
if (WARN_ON(err))
277
+
return;
278
+
279
+
ttccs->xttc.base_addr = base + reg * 4;
280
+
281
+
ttccs->cs.name = np->name;
282
+
ttccs->cs.rating = 200;
283
+
ttccs->cs.read = __xttc_clocksource_read;
284
+
ttccs->cs.mask = CLOCKSOURCE_MASK(16);
285
+
ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
286
+
287
+
__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
288
+
__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
289
+
ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
290
+
__raw_writel(CNT_CNTRL_RESET,
291
+
ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
292
+
293
+
err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
294
+
if (WARN_ON(err))
295
+
return;
296
+
}
297
+
298
+
static void __init zynq_ttc_setup_clockevent(struct device_node *np,
299
+
void __iomem *base)
300
+
{
301
+
struct xttcpss_timer_clockevent *ttcce;
302
+
int err, irq;
303
+
u32 reg;
304
+
305
+
ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
306
+
if (WARN_ON(!ttcce))
307
+
return;
308
+
309
+
err = of_property_read_u32(np, "reg", ®);
310
+
if (WARN_ON(err))
311
+
return;
312
+
313
+
ttcce->xttc.base_addr = base + reg * 4;
314
+
315
+
ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
316
+
if (WARN_ON(IS_ERR(ttcce->clk)))
317
+
return;
318
+
319
+
err = clk_prepare_enable(ttcce->clk);
320
+
if (WARN_ON(err))
321
+
return;
322
+
323
+
irq = irq_of_parse_and_map(np, 0);
324
+
if (WARN_ON(!irq))
325
+
return;
326
+
327
+
ttcce->ce.name = np->name;
328
+
ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
329
+
ttcce->ce.set_next_event = xttcpss_set_next_event;
330
+
ttcce->ce.set_mode = xttcpss_set_mode;
331
+
ttcce->ce.rating = 200;
332
+
ttcce->ce.irq = irq;
333
+
334
+
__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
335
+
__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
336
+
ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
337
+
__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
338
+
339
+
err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
340
+
np->name, ttcce);
341
+
if (WARN_ON(err))
342
+
return;
343
+
344
+
clockevents_config_and_register(&ttcce->ce,
345
+
clk_get_rate(ttcce->clk) / PRESCALE,
346
+
1, 0xfffe);
347
+
}
348
+
349
+
static const __initconst struct of_device_id zynq_ttc_match[] = {
350
+
{ .compatible = "xlnx,ttc-counter-clocksource",
351
+
.data = zynq_ttc_setup_clocksource, },
352
+
{ .compatible = "xlnx,ttc-counter-clockevent",
353
+
.data = zynq_ttc_setup_clockevent, },
354
+
{}
211
355
};
212
356
213
357
/**
···
307
269
* Initializes the timer hardware and register the clock source and clock event
308
270
* timers with Linux kernal timer framework
309
271
**/
310
-
static void __init xttcpss_timer_init(void)
272
+
void __init xttcpss_timer_init(void)
311
273
{
312
-
xttcpss_timer_hardware_init();
313
-
clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
274
+
struct device_node *np;
314
275
315
-
/* Calculate the parameters to allow the clockevent to operate using
316
-
integer math
317
-
*/
318
-
clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
276
+
for_each_compatible_node(np, NULL, "xlnx,ttc") {
277
+
struct device_node *np_chld;
278
+
void __iomem *base;
319
279
320
-
xttcpss_clockevent.max_delta_ns =
321
-
clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
322
-
xttcpss_clockevent.min_delta_ns =
323
-
clockevent_delta2ns(1, &xttcpss_clockevent);
280
+
base = of_iomap(np, 0);
281
+
if (WARN_ON(!base))
282
+
return;
324
283
325
-
/* Indicate that clock event is on 1st CPU as SMP boot needs it */
284
+
for_each_available_child_of_node(np, np_chld) {
285
+
int (*cb)(struct device_node *np, void __iomem *base);
286
+
const struct of_device_id *match;
326
287
327
-
xttcpss_clockevent.cpumask = cpumask_of(0);
328
-
clockevents_register_device(&xttcpss_clockevent);
288
+
match = of_match_node(zynq_ttc_match, np_chld);
289
+
if (match) {
290
+
cb = match->data;
291
+
cb(np_chld, base);
292
+
}
293
+
}
294
+
}
329
295
}
330
-
331
-
/*
332
-
* Instantiate and initialize the system timer structure
333
-
*/
334
-
struct sys_timer xttcpss_sys_timer = {
335
-
.init = xttcpss_timer_init,
336
-
};
+1
-5
arch/arm/plat-orion/irq.c
+1
-5
arch/arm/plat-orion/irq.c
···
41
41
static int __init orion_add_irq_domain(struct device_node *np,
42
42
struct device_node *interrupt_parent)
43
43
{
44
-
int i = 0, irq_gpio;
44
+
int i = 0;
45
45
void __iomem *base;
46
46
47
47
do {
···
54
54
55
55
irq_domain_add_legacy(np, i * 32, 0, 0,
56
56
&irq_domain_simple_ops, NULL);
57
-
58
-
irq_gpio = i * 32;
59
-
orion_gpio_of_init(irq_gpio);
60
-
61
57
return 0;
62
58
}
63
59
+1
arch/arm/plat-samsung/devs.c
+1
arch/arm/plat-samsung/devs.c
-2
arch/arm/plat-samsung/include/plat/devs.h
-2
arch/arm/plat-samsung/include/plat/devs.h
···
132
132
extern struct platform_device exynos4_device_pcm2;
133
133
extern struct platform_device exynos4_device_spdif;
134
134
135
-
extern struct platform_device exynos_device_drm;
136
-
137
135
extern struct platform_device samsung_asoc_dma;
138
136
extern struct platform_device samsung_asoc_idma;
139
137
extern struct platform_device samsung_device_keypad;
+11
arch/arm/plat-samsung/include/plat/mfc.h
+11
arch/arm/plat-samsung/include/plat/mfc.h
···
10
10
#ifndef __PLAT_SAMSUNG_MFC_H
11
11
#define __PLAT_SAMSUNG_MFC_H __FILE__
12
12
13
+
struct s5p_mfc_dt_meminfo {
14
+
unsigned long loff;
15
+
unsigned long lsize;
16
+
unsigned long roff;
17
+
unsigned long rsize;
18
+
char *compatible;
19
+
};
20
+
13
21
/**
14
22
* s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
15
23
* @rbase: base address for MFC 'right' memory interface
···
31
23
*/
32
24
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
33
25
phys_addr_t lbase, unsigned int lsize);
26
+
27
+
int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
28
+
int depth, void *data);
34
29
35
30
#endif /* __PLAT_SAMSUNG_MFC_H */
+34
arch/arm/plat-samsung/s5p-dev-mfc.c
+34
arch/arm/plat-samsung/s5p-dev-mfc.c
···
14
14
#include <linux/dma-mapping.h>
15
15
#include <linux/memblock.h>
16
16
#include <linux/ioport.h>
17
+
#include <linux/of_fdt.h>
18
+
#include <linux/of.h>
17
19
18
20
#include <mach/map.h>
19
21
#include <plat/devs.h>
···
71
69
return 0;
72
70
}
73
71
device_initcall(s5p_mfc_memory_init);
72
+
73
+
#ifdef CONFIG_OF
74
+
int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
75
+
int depth, void *data)
76
+
{
77
+
__be32 *prop;
78
+
unsigned long len;
79
+
struct s5p_mfc_dt_meminfo *mfc_mem = data;
80
+
81
+
if (!data)
82
+
return 0;
83
+
84
+
if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
85
+
return 0;
86
+
87
+
prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
88
+
if (!prop || (len != 2 * sizeof(unsigned long)))
89
+
return 0;
90
+
91
+
mfc_mem->loff = be32_to_cpu(prop[0]);
92
+
mfc_mem->lsize = be32_to_cpu(prop[1]);
93
+
94
+
prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
95
+
if (!prop || (len != 2 * sizeof(unsigned long)))
96
+
return 0;
97
+
98
+
mfc_mem->roff = be32_to_cpu(prop[0]);
99
+
mfc_mem->rsize = be32_to_cpu(prop[1]);
100
+
101
+
return 1;
102
+
}
103
+
#endif
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+383
drivers/clk/clk-zynq.c
+383
drivers/clk/clk-zynq.c
···
1
+
/*
2
+
* Copyright (c) 2012 National Instruments
3
+
*
4
+
* Josh Cartwright <josh.cartwright@ni.com>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License along with
16
+
* this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
#include <linux/io.h>
19
+
#include <linux/of.h>
20
+
#include <linux/slab.h>
21
+
#include <linux/kernel.h>
22
+
#include <linux/clk-provider.h>
23
+
24
+
static void __iomem *slcr_base;
25
+
26
+
struct zynq_pll_clk {
27
+
struct clk_hw hw;
28
+
void __iomem *pll_ctrl;
29
+
void __iomem *pll_cfg;
30
+
};
31
+
32
+
#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw)
33
+
34
+
#define CTRL_PLL_FDIV(x) ((x) >> 12)
35
+
36
+
static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
37
+
unsigned long parent_rate)
38
+
{
39
+
struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
40
+
return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
41
+
}
42
+
43
+
static const struct clk_ops zynq_pll_clk_ops = {
44
+
.recalc_rate = zynq_pll_recalc_rate,
45
+
};
46
+
47
+
static void __init zynq_pll_clk_setup(struct device_node *np)
48
+
{
49
+
struct clk_init_data init;
50
+
struct zynq_pll_clk *pll;
51
+
const char *parent_name;
52
+
struct clk *clk;
53
+
u32 regs[2];
54
+
int ret;
55
+
56
+
ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
57
+
if (WARN_ON(ret))
58
+
return;
59
+
60
+
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
61
+
if (WARN_ON(!pll))
62
+
return;
63
+
64
+
pll->pll_ctrl = slcr_base + regs[0];
65
+
pll->pll_cfg = slcr_base + regs[1];
66
+
67
+
of_property_read_string(np, "clock-output-names", &init.name);
68
+
69
+
init.ops = &zynq_pll_clk_ops;
70
+
parent_name = of_clk_get_parent_name(np, 0);
71
+
init.parent_names = &parent_name;
72
+
init.num_parents = 1;
73
+
74
+
pll->hw.init = &init;
75
+
76
+
clk = clk_register(NULL, &pll->hw);
77
+
if (WARN_ON(IS_ERR(clk)))
78
+
return;
79
+
80
+
ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
81
+
if (WARN_ON(ret))
82
+
return;
83
+
}
84
+
85
+
struct zynq_periph_clk {
86
+
struct clk_hw hw;
87
+
struct clk_onecell_data onecell_data;
88
+
struct clk *gates[2];
89
+
void __iomem *clk_ctrl;
90
+
spinlock_t clkact_lock;
91
+
};
92
+
93
+
#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw)
94
+
95
+
static const u8 periph_clk_parent_map[] = {
96
+
0, 0, 1, 2
97
+
};
98
+
#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
99
+
#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
100
+
101
+
static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
102
+
unsigned long parent_rate)
103
+
{
104
+
struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
105
+
return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
106
+
}
107
+
108
+
static u8 zynq_periph_get_parent(struct clk_hw *hw)
109
+
{
110
+
struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
111
+
return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
112
+
}
113
+
114
+
static const struct clk_ops zynq_periph_clk_ops = {
115
+
.recalc_rate = zynq_periph_recalc_rate,
116
+
.get_parent = zynq_periph_get_parent,
117
+
};
118
+
119
+
static void __init zynq_periph_clk_setup(struct device_node *np)
120
+
{
121
+
struct zynq_periph_clk *periph;
122
+
const char *parent_names[3];
123
+
struct clk_init_data init;
124
+
int clk_num = 0, err;
125
+
const char *name;
126
+
struct clk *clk;
127
+
u32 reg;
128
+
int i;
129
+
130
+
err = of_property_read_u32(np, "reg", ®);
131
+
if (WARN_ON(err))
132
+
return;
133
+
134
+
periph = kzalloc(sizeof(*periph), GFP_KERNEL);
135
+
if (WARN_ON(!periph))
136
+
return;
137
+
138
+
periph->clk_ctrl = slcr_base + reg;
139
+
spin_lock_init(&periph->clkact_lock);
140
+
141
+
init.name = np->name;
142
+
init.ops = &zynq_periph_clk_ops;
143
+
for (i = 0; i < ARRAY_SIZE(parent_names); i++)
144
+
parent_names[i] = of_clk_get_parent_name(np, i);
145
+
init.parent_names = parent_names;
146
+
init.num_parents = ARRAY_SIZE(parent_names);
147
+
148
+
periph->hw.init = &init;
149
+
150
+
clk = clk_register(NULL, &periph->hw);
151
+
if (WARN_ON(IS_ERR(clk)))
152
+
return;
153
+
154
+
err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
155
+
if (WARN_ON(err))
156
+
return;
157
+
158
+
err = of_property_read_string_index(np, "clock-output-names", 0,
159
+
&name);
160
+
if (WARN_ON(err))
161
+
return;
162
+
163
+
periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
164
+
periph->clk_ctrl, 0, 0,
165
+
&periph->clkact_lock);
166
+
if (WARN_ON(IS_ERR(periph->gates[0])))
167
+
return;
168
+
clk_num++;
169
+
170
+
/* some periph clks have 2 downstream gates */
171
+
err = of_property_read_string_index(np, "clock-output-names", 1,
172
+
&name);
173
+
if (err != -ENODATA) {
174
+
periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
175
+
periph->clk_ctrl, 1, 0,
176
+
&periph->clkact_lock);
177
+
if (WARN_ON(IS_ERR(periph->gates[1])))
178
+
return;
179
+
clk_num++;
180
+
}
181
+
182
+
periph->onecell_data.clks = periph->gates;
183
+
periph->onecell_data.clk_num = clk_num;
184
+
185
+
err = of_clk_add_provider(np, of_clk_src_onecell_get,
186
+
&periph->onecell_data);
187
+
if (WARN_ON(err))
188
+
return;
189
+
}
190
+
191
+
/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
192
+
* derivative rates depend on CLK_621_TRUE
193
+
*/
194
+
195
+
struct zynq_cpu_clk {
196
+
struct clk_hw hw;
197
+
struct clk_onecell_data onecell_data;
198
+
struct clk *subclks[4];
199
+
void __iomem *clk_ctrl;
200
+
spinlock_t clkact_lock;
201
+
};
202
+
203
+
#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw)
204
+
205
+
static const u8 zynq_cpu_clk_parent_map[] = {
206
+
1, 1, 2, 0
207
+
};
208
+
#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
209
+
#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
210
+
211
+
static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
212
+
{
213
+
struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
214
+
return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
215
+
}
216
+
217
+
static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
218
+
unsigned long parent_rate)
219
+
{
220
+
struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
221
+
return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
222
+
}
223
+
224
+
static const struct clk_ops zynq_cpu_clk_ops = {
225
+
.get_parent = zynq_cpu_clk_get_parent,
226
+
.recalc_rate = zynq_cpu_clk_recalc_rate,
227
+
};
228
+
229
+
struct zynq_cpu_subclk {
230
+
struct clk_hw hw;
231
+
void __iomem *clk_621;
232
+
enum {
233
+
CPU_SUBCLK_6X4X,
234
+
CPU_SUBCLK_3X2X,
235
+
CPU_SUBCLK_2X,
236
+
CPU_SUBCLK_1X,
237
+
} which;
238
+
};
239
+
240
+
#define CLK_621_TRUE(x) ((x) & 1)
241
+
242
+
#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw);
243
+
244
+
static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
245
+
unsigned long parent_rate)
246
+
{
247
+
unsigned long uninitialized_var(rate);
248
+
struct zynq_cpu_subclk *subclk;
249
+
bool is_621;
250
+
251
+
subclk = to_zynq_cpu_subclk(hw)
252
+
is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
253
+
254
+
switch (subclk->which) {
255
+
case CPU_SUBCLK_6X4X:
256
+
rate = parent_rate;
257
+
break;
258
+
case CPU_SUBCLK_3X2X:
259
+
rate = parent_rate / 2;
260
+
break;
261
+
case CPU_SUBCLK_2X:
262
+
rate = parent_rate / (is_621 ? 3 : 2);
263
+
break;
264
+
case CPU_SUBCLK_1X:
265
+
rate = parent_rate / (is_621 ? 6 : 4);
266
+
break;
267
+
};
268
+
269
+
return rate;
270
+
}
271
+
272
+
static const struct clk_ops zynq_cpu_subclk_ops = {
273
+
.recalc_rate = zynq_cpu_subclk_recalc_rate,
274
+
};
275
+
276
+
static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
277
+
void __iomem *clk_621)
278
+
{
279
+
struct zynq_cpu_subclk *subclk;
280
+
struct clk_init_data init;
281
+
struct clk *clk;
282
+
int err;
283
+
284
+
err = of_property_read_string_index(np, "clock-output-names",
285
+
which, &init.name);
286
+
if (WARN_ON(err))
287
+
goto err_read_output_name;
288
+
289
+
subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
290
+
if (!subclk)
291
+
goto err_subclk_alloc;
292
+
293
+
subclk->clk_621 = clk_621;
294
+
subclk->which = which;
295
+
296
+
init.ops = &zynq_cpu_subclk_ops;
297
+
init.parent_names = &np->name;
298
+
init.num_parents = 1;
299
+
300
+
subclk->hw.init = &init;
301
+
302
+
clk = clk_register(NULL, &subclk->hw);
303
+
if (WARN_ON(IS_ERR(clk)))
304
+
goto err_clk_register;
305
+
306
+
return clk;
307
+
308
+
err_clk_register:
309
+
kfree(subclk);
310
+
err_subclk_alloc:
311
+
err_read_output_name:
312
+
return ERR_PTR(-EINVAL);
313
+
}
314
+
315
+
static void __init zynq_cpu_clk_setup(struct device_node *np)
316
+
{
317
+
struct zynq_cpu_clk *cpuclk;
318
+
const char *parent_names[3];
319
+
struct clk_init_data init;
320
+
void __iomem *clk_621;
321
+
struct clk *clk;
322
+
u32 reg[2];
323
+
int err;
324
+
int i;
325
+
326
+
err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
327
+
if (WARN_ON(err))
328
+
return;
329
+
330
+
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
331
+
if (WARN_ON(!cpuclk))
332
+
return;
333
+
334
+
cpuclk->clk_ctrl = slcr_base + reg[0];
335
+
clk_621 = slcr_base + reg[1];
336
+
spin_lock_init(&cpuclk->clkact_lock);
337
+
338
+
init.name = np->name;
339
+
init.ops = &zynq_cpu_clk_ops;
340
+
for (i = 0; i < ARRAY_SIZE(parent_names); i++)
341
+
parent_names[i] = of_clk_get_parent_name(np, i);
342
+
init.parent_names = parent_names;
343
+
init.num_parents = ARRAY_SIZE(parent_names);
344
+
345
+
cpuclk->hw.init = &init;
346
+
347
+
clk = clk_register(NULL, &cpuclk->hw);
348
+
if (WARN_ON(IS_ERR(clk)))
349
+
return;
350
+
351
+
err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
352
+
if (WARN_ON(err))
353
+
return;
354
+
355
+
for (i = 0; i < 4; i++) {
356
+
cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
357
+
if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
358
+
return;
359
+
}
360
+
361
+
cpuclk->onecell_data.clks = cpuclk->subclks;
362
+
cpuclk->onecell_data.clk_num = i;
363
+
364
+
err = of_clk_add_provider(np, of_clk_src_onecell_get,
365
+
&cpuclk->onecell_data);
366
+
if (WARN_ON(err))
367
+
return;
368
+
}
369
+
370
+
static const __initconst struct of_device_id zynq_clk_match[] = {
371
+
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
372
+
{ .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, },
373
+
{ .compatible = "xlnx,zynq-periph-clock",
374
+
.data = zynq_periph_clk_setup, },
375
+
{ .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, },
376
+
{}
377
+
};
378
+
379
+
void __init xilinx_zynq_clocks_init(void __iomem *slcr)
380
+
{
381
+
slcr_base = slcr;
382
+
of_clk_init(zynq_clk_match);
383
+
}
+1
-1
drivers/gpio/Kconfig
+1
-1
drivers/gpio/Kconfig
+22
-21
drivers/gpio/gpio-samsung.c
+22
-21
drivers/gpio/gpio-samsung.c
···
2797
2797
int group = 0;
2798
2798
void __iomem *gpx_base;
2799
2799
2800
-
#ifdef CONFIG_PINCTRL_SAMSUNG
2801
-
/*
2802
-
* This gpio driver includes support for device tree support and
2803
-
* there are platforms using it. In order to maintain
2804
-
* compatibility with those platforms, and to allow non-dt
2805
-
* Exynos4210 platforms to use this gpiolib support, a check
2806
-
* is added to find out if there is a active pin-controller
2807
-
* driver support available. If it is available, this gpiolib
2808
-
* support is ignored and the gpiolib support available in
2809
-
* pin-controller driver is used. This is a temporary check and
2810
-
* will go away when all of the Exynos4210 platforms have
2811
-
* switched to using device tree and the pin-ctrl driver.
2812
-
*/
2813
-
struct device_node *pctrl_np;
2814
-
const char *pctrl_compat = "samsung,pinctrl-exynos4210";
2815
-
pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat);
2816
-
if (pctrl_np)
2817
-
if (of_device_is_available(pctrl_np))
2818
-
return;
2819
-
#endif
2820
-
2821
2800
/* gpio part1 */
2822
2801
gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2823
2802
if (gpio_base1 == NULL) {
···
3010
3031
struct samsung_gpio_chip *chip;
3011
3032
int i, nr_chips;
3012
3033
int group = 0;
3034
+
3035
+
#ifdef CONFIG_PINCTRL_SAMSUNG
3036
+
/*
3037
+
* This gpio driver includes support for device tree support and there
3038
+
* are platforms using it. In order to maintain compatibility with those
3039
+
* platforms, and to allow non-dt Exynos4210 platforms to use this
3040
+
* gpiolib support, a check is added to find out if there is a active
3041
+
* pin-controller driver support available. If it is available, this
3042
+
* gpiolib support is ignored and the gpiolib support available in
3043
+
* pin-controller driver is used. This is a temporary check and will go
3044
+
* away when all of the Exynos4210 platforms have switched to using
3045
+
* device tree and the pin-ctrl driver.
3046
+
*/
3047
+
struct device_node *pctrl_np;
3048
+
static const struct of_device_id exynos_pinctrl_ids[] = {
3049
+
{ .compatible = "samsung,pinctrl-exynos4210", },
3050
+
{ .compatible = "samsung,pinctrl-exynos4x12", },
3051
+
};
3052
+
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3053
+
if (pctrl_np && of_device_is_available(pctrl_np))
3054
+
return -ENODEV;
3055
+
#endif
3013
3056
3014
3057
samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3015
3058
+15
-7
drivers/pinctrl/mvebu/pinctrl-dove.c
+15
-7
drivers/pinctrl/mvebu/pinctrl-dove.c
···
22
22
23
23
#include "pinctrl-mvebu.h"
24
24
25
-
#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
26
-
#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
25
+
#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
26
+
#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
27
27
#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
28
28
#define DOVE_AU0_AC97_SEL BIT(16)
29
-
#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
29
+
#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
30
30
#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
31
-
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
31
+
#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
32
32
#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)
33
33
#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)
34
34
#define DOVE_TWSI_OPTION3_GPIO BIT(22)
35
-
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
35
+
#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
36
36
#define DOVE_SSP_ON_AU1 BIT(0)
37
-
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
37
+
#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
38
38
#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)
39
39
#define DOVE_NAND_GPIO_EN BIT(0)
40
-
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
40
+
#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
41
41
#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
42
42
#define DOVE_SPI_GPIO_SEL BIT(5)
43
43
#define DOVE_UART1_GPIO_SEL BIT(4)
···
233
233
unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
234
234
unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
235
235
unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
236
+
237
+
/*
238
+
* clear all audio1 related bits before configure
239
+
*/
240
+
gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
241
+
gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
242
+
sspc1 &= ~DOVE_SSP_ON_AU1;
243
+
mpp4 &= ~DOVE_AU1_GPIO_SEL;
236
244
237
245
if (config & BIT(0))
238
246
gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+290
-278
drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+290
-278
drivers/pinctrl/mvebu/pinctrl-kirkwood.c
···
21
21
22
22
#include "pinctrl-mvebu.h"
23
23
24
-
#define V(f6180, f6190, f6192, f6281, f6282) \
24
+
#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
25
25
((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
26
-
(f6281 << 3) | (f6282 << 4))
26
+
(f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
27
27
28
28
enum kirkwood_variant {
29
-
VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
30
-
VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
31
-
VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
32
-
VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
33
-
VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
29
+
VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0),
30
+
VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0),
31
+
VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0),
32
+
VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0),
33
+
VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0),
34
+
VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1),
34
35
};
35
36
36
37
static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
37
38
MPP_MODE(0,
38
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
39
-
MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1)),
40
-
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1))),
39
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
40
+
MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1)),
41
+
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))),
41
42
MPP_MODE(1,
42
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
43
-
MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1)),
44
-
MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1))),
43
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
44
+
MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1)),
45
+
MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))),
45
46
MPP_MODE(2,
46
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
47
-
MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1)),
48
-
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1))),
47
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
48
+
MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1)),
49
+
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))),
49
50
MPP_MODE(3,
50
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
51
-
MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1)),
52
-
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1))),
51
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
52
+
MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1)),
53
+
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))),
53
54
MPP_MODE(4,
54
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
55
-
MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1)),
56
-
MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1)),
57
-
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
58
-
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1)),
59
-
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0))),
55
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
56
+
MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1)),
57
+
MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
58
+
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
59
+
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0)),
60
+
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0))),
60
61
MPP_MODE(5,
61
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
62
-
MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1)),
63
-
MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1)),
64
-
MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0)),
65
-
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
66
-
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
62
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
63
+
MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1)),
64
+
MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
65
+
MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
66
+
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
67
+
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
67
68
MPP_MODE(6,
68
-
MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1)),
69
-
MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1)),
70
-
MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0))),
69
+
MPP_VAR_FUNCTION(0x0, "sysrst", "out", V(1, 1, 1, 1, 1, 1)),
70
+
MPP_VAR_FUNCTION(0x1, "spi", "mosi", V(1, 1, 1, 1, 1, 1)),
71
+
MPP_VAR_FUNCTION(0x2, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
71
72
MPP_MODE(7,
72
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
73
-
MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0)),
74
-
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1)),
75
-
MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0)),
76
-
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
73
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
74
+
MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1)),
75
+
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)),
76
+
MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0)),
77
+
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
77
78
MPP_MODE(8,
78
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
79
-
MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1)),
80
-
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
81
-
MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1)),
82
-
MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1)),
83
-
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
84
-
MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0)),
85
-
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
79
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
80
+
MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1)),
81
+
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
82
+
MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1)),
83
+
MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0)),
84
+
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
85
+
MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
86
+
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
86
87
MPP_MODE(9,
87
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
88
-
MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1)),
89
-
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
90
-
MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1)),
91
-
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
92
-
MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0)),
93
-
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
88
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
89
+
MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1)),
90
+
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
91
+
MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1)),
92
+
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
93
+
MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0)),
94
+
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
94
95
MPP_MODE(10,
95
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
96
-
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1)),
97
-
MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1)),
98
-
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
99
-
MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0))),
96
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
97
+
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)),
98
+
MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1)),
99
+
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
100
+
MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0))),
100
101
MPP_MODE(11,
101
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
102
-
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1)),
103
-
MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1)),
104
-
MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0)),
105
-
MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0)),
106
-
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0)),
107
-
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1))),
102
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
103
+
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)),
104
+
MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)),
105
+
MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0)),
106
+
MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0)),
107
+
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0)),
108
+
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0))),
108
109
MPP_MODE(12,
109
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1)),
110
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
111
-
MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1)),
112
-
MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
113
-
MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1)),
114
-
MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1))),
110
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0)),
111
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0)),
112
+
MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0)),
113
+
MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0)),
114
+
MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0)),
115
+
MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
115
116
MPP_MODE(13,
116
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
117
-
MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1)),
118
-
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
119
-
MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1)),
120
-
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1))),
117
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
118
+
MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0)),
119
+
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1)),
120
+
MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0)),
121
+
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))),
121
122
MPP_MODE(14,
122
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
123
-
MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1)),
124
-
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
125
-
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
126
-
MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
127
-
MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1)),
128
-
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1))),
123
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
124
+
MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0)),
125
+
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1)),
126
+
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
127
+
MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0)),
128
+
MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0)),
129
+
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))),
129
130
MPP_MODE(15,
130
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
131
-
MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1)),
132
-
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1)),
133
-
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1)),
134
-
MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1)),
135
-
MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1))),
131
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
132
+
MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0)),
133
+
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)),
134
+
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0)),
135
+
MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
136
+
MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0))),
136
137
MPP_MODE(16,
137
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
138
-
MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1)),
139
-
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1)),
140
-
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1)),
141
-
MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1)),
142
-
MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1)),
143
-
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1))),
138
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
139
+
MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0)),
140
+
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)),
141
+
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0)),
142
+
MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
143
+
MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0)),
144
+
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))),
144
145
MPP_MODE(17,
145
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
146
-
MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1)),
147
-
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
148
-
MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1)),
149
-
MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1))),
146
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
147
+
MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0)),
148
+
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
149
+
MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0)),
150
+
MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
150
151
MPP_MODE(18,
151
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
152
-
MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1)),
153
-
MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1))),
152
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
153
+
MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1)),
154
+
MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))),
154
155
MPP_MODE(19,
155
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1)),
156
-
MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1))),
156
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
157
+
MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))),
157
158
MPP_MODE(20,
158
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
159
-
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1)),
160
-
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
161
-
MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1)),
162
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
163
-
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1)),
164
-
MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1)),
165
-
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0))),
159
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
160
+
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)),
161
+
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
162
+
MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)),
163
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)),
164
+
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
165
+
MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)),
166
+
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0, 0))),
166
167
MPP_MODE(21,
167
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
168
-
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1)),
169
-
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1)),
170
-
MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1)),
171
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
172
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
173
-
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
174
-
MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1))),
168
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
169
+
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)),
170
+
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)),
171
+
MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)),
172
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0, 0)),
173
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)),
174
+
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
175
+
MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))),
175
176
MPP_MODE(22,
176
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
177
-
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1)),
178
-
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1)),
179
-
MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1)),
180
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
181
-
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1)),
182
-
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1)),
183
-
MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1))),
177
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
178
+
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)),
179
+
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)),
180
+
MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)),
181
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0, 0)),
182
+
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)),
183
+
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
184
+
MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))),
184
185
MPP_MODE(23,
185
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
186
-
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1)),
187
-
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1)),
188
-
MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1)),
189
-
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0)),
190
-
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1)),
191
-
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1)),
192
-
MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1))),
186
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
187
+
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)),
188
+
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)),
189
+
MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)),
190
+
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0, 0)),
191
+
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)),
192
+
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
193
+
MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))),
193
194
MPP_MODE(24,
194
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
195
-
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1)),
196
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1)),
197
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1)),
198
-
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0)),
199
-
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1)),
200
-
MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1))),
195
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
196
+
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)),
197
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)),
198
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)),
199
+
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0, 0)),
200
+
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)),
201
+
MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))),
201
202
MPP_MODE(25,
202
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
203
-
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1)),
204
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1)),
205
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1)),
206
-
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0)),
207
-
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1)),
208
-
MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1))),
203
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
204
+
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)),
205
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)),
206
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)),
207
+
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0, 0)),
208
+
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)),
209
+
MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))),
209
210
MPP_MODE(26,
210
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
211
-
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1)),
212
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
213
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1)),
214
-
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0)),
215
-
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1)),
216
-
MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1))),
211
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
212
+
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)),
213
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)),
214
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)),
215
+
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0, 0)),
216
+
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)),
217
+
MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))),
217
218
MPP_MODE(27,
218
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
219
-
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1)),
220
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
221
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1)),
222
-
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0)),
223
-
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1)),
224
-
MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1))),
219
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
220
+
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)),
221
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)),
222
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)),
223
+
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0, 0)),
224
+
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)),
225
+
MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))),
225
226
MPP_MODE(28,
226
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
227
-
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1)),
228
-
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1)),
229
-
MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1)),
230
-
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0)),
231
-
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
232
-
MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1))),
227
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
228
+
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)),
229
+
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)),
230
+
MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)),
231
+
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0, 0)),
232
+
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)),
233
+
MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))),
233
234
MPP_MODE(29,
234
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1)),
235
-
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1)),
236
-
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1)),
237
-
MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1)),
238
-
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
239
-
MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1))),
235
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
236
+
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)),
237
+
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)),
238
+
MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)),
239
+
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0, 0)),
240
+
MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))),
240
241
MPP_MODE(30,
241
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
242
-
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1)),
243
-
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1)),
244
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1)),
245
-
MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1))),
242
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
243
+
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0)),
244
+
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)),
245
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0)),
246
+
MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0))),
246
247
MPP_MODE(31,
247
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
248
-
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1)),
249
-
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1)),
250
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1)),
251
-
MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1))),
248
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
249
+
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0)),
250
+
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)),
251
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0)),
252
+
MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0))),
252
253
MPP_MODE(32,
253
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
254
-
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1)),
255
-
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1)),
256
-
MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1)),
257
-
MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1))),
254
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
255
+
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0)),
256
+
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)),
257
+
MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0)),
258
+
MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0))),
258
259
MPP_MODE(33,
259
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1)),
260
-
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1)),
261
-
MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1)),
262
-
MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1))),
260
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)),
261
+
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)),
262
+
MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)),
263
+
MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))),
263
264
MPP_MODE(34,
264
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
265
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1)),
266
-
MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1)),
267
-
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1)),
268
-
MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1))),
265
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
266
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)),
267
+
MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0)),
268
+
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)),
269
+
MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))),
269
270
MPP_MODE(35,
270
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1)),
271
-
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1)),
272
-
MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1)),
273
-
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1)),
274
-
MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1)),
275
-
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1))),
271
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
272
+
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
273
+
MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)),
274
+
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
275
+
MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)),
276
+
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1, 0))),
276
277
MPP_MODE(36,
277
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
278
-
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1)),
279
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1)),
280
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
281
-
MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1))),
278
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
279
+
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)),
280
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)),
281
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1, 0)),
282
+
MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
282
283
MPP_MODE(37,
283
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
284
-
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1)),
285
-
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1)),
286
-
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
287
-
MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1))),
284
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
285
+
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)),
286
+
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)),
287
+
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1, 0)),
288
+
MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
288
289
MPP_MODE(38,
289
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
290
-
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1)),
291
-
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1)),
292
-
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1)),
293
-
MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1))),
290
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
291
+
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)),
292
+
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)),
293
+
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1, 0)),
294
+
MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))),
294
295
MPP_MODE(39,
295
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
296
-
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1)),
297
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1)),
298
-
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1)),
299
-
MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1))),
296
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
297
+
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)),
298
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)),
299
+
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1, 0)),
300
+
MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))),
300
301
MPP_MODE(40,
301
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
302
-
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1)),
303
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1)),
304
-
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1)),
305
-
MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1))),
302
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
303
+
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)),
304
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)),
305
+
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1, 0)),
306
+
MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))),
306
307
MPP_MODE(41,
307
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
308
-
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1)),
309
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
310
-
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1)),
311
-
MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1))),
308
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
309
+
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)),
310
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)),
311
+
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1, 0)),
312
+
MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))),
312
313
MPP_MODE(42,
313
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
314
-
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1)),
315
-
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
316
-
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1)),
317
-
MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1))),
314
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
315
+
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)),
316
+
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)),
317
+
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1, 0)),
318
+
MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))),
318
319
MPP_MODE(43,
319
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
320
-
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1)),
321
-
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1)),
322
-
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1)),
323
-
MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1))),
320
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
321
+
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)),
322
+
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)),
323
+
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1, 0)),
324
+
MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))),
324
325
MPP_MODE(44,
325
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
326
-
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1)),
327
-
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1)),
328
-
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
329
-
MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1))),
326
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
327
+
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)),
328
+
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)),
329
+
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1, 0)),
330
+
MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))),
330
331
MPP_MODE(45,
331
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
332
-
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1)),
333
-
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1)),
334
-
MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1))),
332
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
333
+
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0)),
334
+
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)),
335
+
MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0))),
335
336
MPP_MODE(46,
336
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
337
-
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1)),
338
-
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1)),
339
-
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1))),
337
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
338
+
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0)),
339
+
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)),
340
+
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0))),
340
341
MPP_MODE(47,
341
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
342
-
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1)),
343
-
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1)),
344
-
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1))),
342
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
343
+
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0)),
344
+
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)),
345
+
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))),
345
346
MPP_MODE(48,
346
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1)),
347
-
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1)),
348
-
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1)),
349
-
MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1))),
347
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)),
348
+
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0)),
349
+
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)),
350
+
MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0))),
350
351
MPP_MODE(49,
351
-
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0)),
352
-
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1)),
353
-
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0)),
354
-
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1)),
355
-
MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0)),
356
-
MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1)),
357
-
MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1))),
352
+
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1)),
353
+
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0)),
354
+
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0)),
355
+
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)),
356
+
MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0)),
357
+
MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0)),
358
+
MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))),
358
359
};
359
360
360
361
static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
···
434
433
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
435
434
};
436
435
436
+
static struct mvebu_pinctrl_soc_info mv98dx4122_info = {
437
+
.variant = VARIANT_MV98DX4122,
438
+
.controls = mv88f628x_mpp_controls,
439
+
.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
440
+
.modes = mv88f6xxx_mpp_modes,
441
+
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
442
+
.gpioranges = mv88f628x_gpio_ranges,
443
+
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
444
+
};
445
+
437
446
static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
438
447
{ .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
439
448
{ .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
440
449
{ .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
441
450
{ .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
442
451
{ .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
452
+
{ .compatible = "marvell,98dx4122-pinctrl", .data = &mv98dx4122_info },
443
453
{ }
444
454
};
445
455
+3
drivers/power/Kconfig
+3
drivers/power/Kconfig
+1
drivers/power/Makefile
+1
drivers/power/Makefile
+15
drivers/power/reset/Kconfig
+15
drivers/power/reset/Kconfig
···
1
+
menuconfig POWER_RESET
2
+
bool "Board level reset or power off"
3
+
help
4
+
Provides a number of drivers which either reset a complete board
5
+
or shut it down, by manipulating the main power supply on the board.
6
+
7
+
Say Y here to enable board reset and power off
8
+
9
+
config POWER_RESET_GPIO
10
+
bool "GPIO power-off driver"
11
+
depends on OF_GPIO && POWER_RESET
12
+
help
13
+
This driver supports turning off your board via a GPIO line.
14
+
If your board needs a GPIO high/low to power down, say Y and
15
+
create a binding in your devicetree.
+1
drivers/power/reset/Makefile
+1
drivers/power/reset/Makefile
···
1
+
obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
+129
drivers/power/reset/gpio-poweroff.c
+129
drivers/power/reset/gpio-poweroff.c
···
1
+
/*
2
+
* Toggles a GPIO pin to power down a device
3
+
*
4
+
* Jamie Lentin <jm@lentin.co.uk>
5
+
* Andrew Lunn <andrew@lunn.ch>
6
+
*
7
+
* Copyright (C) 2012 Jamie Lentin
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License version 2 as
11
+
* published by the Free Software Foundation.
12
+
*
13
+
*/
14
+
#include <linux/kernel.h>
15
+
#include <linux/init.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/gpio.h>
19
+
#include <linux/of_platform.h>
20
+
#include <linux/of_gpio.h>
21
+
#include <linux/module.h>
22
+
23
+
/*
24
+
* Hold configuration here, cannot be more than one instance of the driver
25
+
* since pm_power_off itself is global.
26
+
*/
27
+
static int gpio_num = -1;
28
+
static int gpio_active_low;
29
+
30
+
static void gpio_poweroff_do_poweroff(void)
31
+
{
32
+
BUG_ON(gpio_num == -1);
33
+
34
+
/* drive it active */
35
+
gpio_direction_output(gpio_num, !gpio_active_low);
36
+
mdelay(100);
37
+
/* rising edge or drive inactive */
38
+
gpio_set_value(gpio_num, gpio_active_low);
39
+
mdelay(100);
40
+
/* falling edge */
41
+
gpio_set_value(gpio_num, !gpio_active_low);
42
+
43
+
/* give it some time */
44
+
mdelay(3000);
45
+
46
+
WARN_ON(1);
47
+
}
48
+
49
+
static int __devinit gpio_poweroff_probe(struct platform_device *pdev)
50
+
{
51
+
enum of_gpio_flags flags;
52
+
bool input = false;
53
+
int ret;
54
+
55
+
/* If a pm_power_off function has already been added, leave it alone */
56
+
if (pm_power_off != NULL) {
57
+
pr_err("%s: pm_power_off function already registered",
58
+
__func__);
59
+
return -EBUSY;
60
+
}
61
+
62
+
gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
63
+
if (gpio_num < 0) {
64
+
pr_err("%s: Could not get GPIO configuration: %d",
65
+
__func__, gpio_num);
66
+
return -ENODEV;
67
+
}
68
+
gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
69
+
70
+
if (of_get_property(pdev->dev.of_node, "input", NULL))
71
+
input = true;
72
+
73
+
ret = gpio_request(gpio_num, "poweroff-gpio");
74
+
if (ret) {
75
+
pr_err("%s: Could not get GPIO %d", __func__, gpio_num);
76
+
return ret;
77
+
}
78
+
if (input) {
79
+
if (gpio_direction_input(gpio_num)) {
80
+
pr_err("Could not set direction of GPIO %d to input",
81
+
gpio_num);
82
+
goto err;
83
+
}
84
+
} else {
85
+
if (gpio_direction_output(gpio_num, gpio_active_low)) {
86
+
pr_err("Could not set direction of GPIO %d", gpio_num);
87
+
goto err;
88
+
}
89
+
}
90
+
91
+
pm_power_off = &gpio_poweroff_do_poweroff;
92
+
return 0;
93
+
94
+
err:
95
+
gpio_free(gpio_num);
96
+
return -ENODEV;
97
+
}
98
+
99
+
static int __devexit gpio_poweroff_remove(struct platform_device *pdev)
100
+
{
101
+
if (gpio_num != -1)
102
+
gpio_free(gpio_num);
103
+
if (pm_power_off == &gpio_poweroff_do_poweroff)
104
+
pm_power_off = NULL;
105
+
106
+
return 0;
107
+
}
108
+
109
+
static const struct of_device_id of_gpio_poweroff_match[] = {
110
+
{ .compatible = "gpio-poweroff", },
111
+
{},
112
+
};
113
+
114
+
static struct platform_driver gpio_poweroff_driver = {
115
+
.probe = gpio_poweroff_probe,
116
+
.remove = __devexit_p(gpio_poweroff_remove),
117
+
.driver = {
118
+
.name = "poweroff-gpio",
119
+
.owner = THIS_MODULE,
120
+
.of_match_table = of_gpio_poweroff_match,
121
+
},
122
+
};
123
+
124
+
module_platform_driver(gpio_poweroff_driver);
125
+
126
+
MODULE_AUTHOR("Jamie Lentin <jm@lentin.co.uk>");
127
+
MODULE_DESCRIPTION("GPIO poweroff driver");
128
+
MODULE_LICENSE("GPL");
129
+
MODULE_ALIAS("platform:poweroff-gpio");
+35
-3
drivers/usb/host/ehci-orion.c
+35
-3
drivers/usb/host/ehci-orion.c
···
14
14
#include <linux/mbus.h>
15
15
#include <linux/clk.h>
16
16
#include <linux/platform_data/usb-ehci-orion.h>
17
+
#include <linux/of.h>
18
+
#include <linux/of_device.h>
19
+
#include <linux/of_irq.h>
17
20
18
21
#define rdl(off) __raw_readl(hcd->regs + (off))
19
22
#define wrl(off, val) __raw_writel((val), hcd->regs + (off))
···
170
167
}
171
168
}
172
169
170
+
static u64 ehci_orion_dma_mask = DMA_BIT_MASK(32);
171
+
173
172
static int ehci_orion_drv_probe(struct platform_device *pdev)
174
173
{
175
174
struct orion_ehci_data *pd = pdev->dev.platform_data;
···
182
177
struct clk *clk;
183
178
void __iomem *regs;
184
179
int irq, err;
180
+
enum orion_ehci_phy_ver phy_version;
185
181
186
182
if (usb_disabled())
187
183
return -ENODEV;
188
184
189
185
pr_debug("Initializing Orion-SoC USB Host Controller\n");
190
186
191
-
irq = platform_get_irq(pdev, 0);
187
+
if (pdev->dev.of_node)
188
+
irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
189
+
else
190
+
irq = platform_get_irq(pdev, 0);
192
191
if (irq <= 0) {
193
192
dev_err(&pdev->dev,
194
193
"Found HC with no IRQ. Check %s setup!\n",
···
209
200
err = -ENODEV;
210
201
goto err1;
211
202
}
203
+
204
+
/*
205
+
* Right now device-tree probed devices don't get dma_mask
206
+
* set. Since shared usb code relies on it, set it here for
207
+
* now. Once we have dma capability bindings this can go away.
208
+
*/
209
+
if (!pdev->dev.dma_mask)
210
+
pdev->dev.dma_mask = &ehci_orion_dma_mask;
212
211
213
212
if (!request_mem_region(res->start, resource_size(res),
214
213
ehci_orion_hc_driver.description)) {
···
265
248
/*
266
249
* setup Orion USB controller.
267
250
*/
268
-
switch (pd->phy_version) {
251
+
if (pdev->dev.of_node)
252
+
phy_version = EHCI_PHY_NA;
253
+
else
254
+
phy_version = pd->phy_version;
255
+
256
+
switch (phy_version) {
269
257
case EHCI_PHY_NA: /* dont change USB phy settings */
270
258
break;
271
259
case EHCI_PHY_ORION:
···
325
303
326
304
MODULE_ALIAS("platform:orion-ehci");
327
305
306
+
static const struct of_device_id ehci_orion_dt_ids[] __devinitdata = {
307
+
{ .compatible = "marvell,orion-ehci", },
308
+
{},
309
+
};
310
+
MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids);
311
+
328
312
static struct platform_driver ehci_orion_driver = {
329
313
.probe = ehci_orion_drv_probe,
330
314
.remove = __exit_p(ehci_orion_drv_remove),
331
315
.shutdown = usb_hcd_platform_shutdown,
332
-
.driver.name = "orion-ehci",
316
+
.driver = {
317
+
.name = "orion-ehci",
318
+
.owner = THIS_MODULE,
319
+
.of_match_table = of_match_ptr(ehci_orion_dt_ids),
320
+
},
333
321
};
+11
drivers/watchdog/at91sam9_wdt.c
+11
drivers/watchdog/at91sam9_wdt.c
···
32
32
#include <linux/timer.h>
33
33
#include <linux/bitops.h>
34
34
#include <linux/uaccess.h>
35
+
#include <linux/of.h>
35
36
36
37
#include "at91sam9_wdt.h"
37
38
···
303
302
return res;
304
303
}
305
304
305
+
#if defined(CONFIG_OF)
306
+
static const struct of_device_id at91_wdt_dt_ids[] __initconst = {
307
+
{ .compatible = "atmel,at91sam9260-wdt" },
308
+
{ /* sentinel */ }
309
+
};
310
+
311
+
MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
312
+
#endif
313
+
306
314
static struct platform_driver at91wdt_driver = {
307
315
.remove = __exit_p(at91wdt_remove),
308
316
.driver = {
309
317
.name = "at91_wdt",
310
318
.owner = THIS_MODULE,
319
+
.of_match_table = of_match_ptr(at91_wdt_dt_ids),
311
320
},
312
321
};
313
322
+24
include/linux/clk/zynq.h
+24
include/linux/clk/zynq.h
···
1
+
/*
2
+
* Copyright (C) 2012 National Instruments
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License as published by
6
+
* the Free Software Foundation; either version 2 of the License, or
7
+
* (at your option) any later version.
8
+
*
9
+
* This program is distributed in the hope that it will be useful,
10
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
+
* GNU General Public License for more details.
13
+
*
14
+
* You should have received a copy of the GNU General Public License
15
+
* along with this program; if not, write to the Free Software
16
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17
+
*/
18
+
19
+
#ifndef __LINUX_CLK_ZYNQ_H_
20
+
#define __LINUX_CLK_ZYNQ_H_
21
+
22
+
void __init xilinx_zynq_clocks_init(void __iomem *slcr);
23
+
24
+
#endif