drm/amd/display: Add some DCN401 reg name to macro definitions

+64

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

··· 236 236 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 237 237 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 238 238 239 + #define ABM_MASK_SH_LIST_DCN401(mask_sh) \ 240 + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 241 + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 242 + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 243 + ABM1_HG_VMAX_SEL, mask_sh), \ 244 + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 245 + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 246 + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 247 + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 248 + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 249 + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 250 + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 251 + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 252 + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 253 + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 254 + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 255 + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 256 + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 257 + BL1_PWM_USER_LEVEL, mask_sh), \ 258 + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 259 + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 260 + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 261 + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 262 + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 263 + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 264 + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 265 + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 266 + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 267 + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 268 + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ 269 + ABM1_ACE_SLOPE_DATA, mask_sh), \ 270 + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ 271 + ABM1_ACE_OFFSET_DATA, mask_sh), \ 272 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 273 + ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \ 274 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 275 + ABM1_ACE_THRES_INDEX, mask_sh), \ 276 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 277 + ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \ 278 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 279 + ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \ 280 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 281 + ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \ 282 + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ 283 + ABM1_ACE_LOCK, mask_sh), \ 284 + ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \ 285 + ABM1_ACE_THRES_DATA_1, mask_sh), \ 286 + ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \ 287 + ABM1_ACE_THRES_DATA_2, mask_sh), \ 288 + ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \ 289 + ABM1_HG_RESULT_DATA, mask_sh), \ 290 + ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \ 291 + ABM1_HG_RESULT_INDEX, mask_sh), \ 292 + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \ 293 + ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \ 294 + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \ 295 + ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \ 296 + ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \ 297 + ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \ 298 + ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \ 299 + ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \ 300 + ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \ 301 + ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh) 302 + 239 303 #define ABM_REG_FIELD_LIST(type) \ 240 304 type ABM1_HG_NUM_OF_BINS_SEL; \ 241 305 type ABM1_HG_VMAX_SEL; \

+46 -1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

··· 178 178 uint32_t DCHUBBUB_CLOCK_CNTL; 179 179 uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL; 180 180 uint32_t DCHUBBUB_ARB_QOS_FORCE; 181 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A; 182 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A; 183 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B; 184 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B; 185 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A; 186 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A; 187 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B; 188 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B; 189 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A; 190 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A; 191 + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B; 192 + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B; 193 + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A; 194 + uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B; 195 + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A; 196 + uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B; 197 + uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A; 198 + uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B; 199 + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A; 200 + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B; 181 201 }; 182 202 183 203 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ ··· 220 200 type MALL_PREFETCH_COMPLETE;\ 221 201 type MALL_IN_USE 222 202 223 - #define HUBBUB_REG_FIELD_LIST_DCN35(type) \ 203 + #define HUBBUB_REG_FIELD_LIST_DCN35(type) \ 224 204 type DCHUBBUB_FGCG_REP_DIS;\ 225 205 type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE 226 206 ··· 325 305 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ 326 306 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 327 307 308 + 328 309 #define HUBBUB_HVM_REG_FIELD_LIST(type) \ 329 310 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ 330 311 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ ··· 404 383 type DET_MEM_PWR_LS_MODE 405 384 406 385 386 + #define HUBBUB_REG_FIELD_LIST_DCN4_01(type) \ 387 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;\ 388 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;\ 389 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;\ 390 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;\ 391 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;\ 392 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;\ 393 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;\ 394 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;\ 395 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;\ 396 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;\ 397 + type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;\ 398 + type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;\ 399 + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;\ 400 + type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;\ 401 + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;\ 402 + type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;\ 403 + type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;\ 404 + type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;\ 405 + type DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;\ 406 + type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B 407 + 407 408 struct dcn_hubbub_shift { 408 409 DCN_HUBBUB_REG_FIELD_LIST(uint8_t); 409 410 HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); ··· 433 390 HUBBUB_RET_REG_FIELD_LIST(uint8_t); 434 391 HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); 435 392 HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); 393 + HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t); 436 394 }; 437 395 438 396 struct dcn_hubbub_mask { ··· 443 399 HUBBUB_RET_REG_FIELD_LIST(uint32_t); 444 400 HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); 445 401 HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); 402 + HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t); 446 403 }; 447 404 448 405 struct dc;

+7

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

··· 593 593 type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\ 594 594 type DIG_STREAM_LINK_TARGET 595 595 596 + #define SE_REG_FIELD_LIST_DCN4_01_COMMON(type) \ 597 + type COMPRESSED_PIXEL_FORMAT;\ 598 + type DP_VID_N_INTERVAL;\ 599 + type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE 600 + 596 601 struct dcn10_stream_encoder_shift { 597 602 SE_REG_FIELD_LIST_DCN1_0(uint8_t); 598 603 uint8_t HDMI_ACP_SEND; ··· 605 600 SE_REG_FIELD_LIST_DCN3_0(uint8_t); 606 601 SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t); 607 602 SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t); 603 + SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); 608 604 }; 609 605 610 606 struct dcn10_stream_encoder_mask { ··· 615 609 SE_REG_FIELD_LIST_DCN3_0(uint32_t); 616 610 SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t); 617 611 SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t); 612 + SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); 618 613 }; 619 614 620 615 struct dcn10_stream_encoder {

+27

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

··· 329 329 type DPSTREAMCLK2_GATE_DISABLE;\ 330 330 type DPSTREAMCLK3_GATE_DISABLE;\ 331 331 332 + #define DCCG401_REG_FIELD_LIST(type) \ 333 + type OTG0_TMDS_PIXEL_RATE_DIV;\ 334 + type DPDTO0_INT;\ 335 + type OTG1_TMDS_PIXEL_RATE_DIV;\ 336 + type DPDTO1_INT;\ 337 + type OTG2_TMDS_PIXEL_RATE_DIV;\ 338 + type DPDTO2_INT;\ 339 + type OTG3_TMDS_PIXEL_RATE_DIV;\ 340 + type DPDTO3_INT;\ 341 + type SYMCLK32_ROOT_LE2_GATE_DISABLE;\ 342 + type SYMCLK32_ROOT_LE3_GATE_DISABLE;\ 343 + type SYMCLK32_LE2_GATE_DISABLE;\ 344 + type SYMCLK32_LE3_GATE_DISABLE;\ 345 + type SYMCLK32_LE2_SRC_SEL;\ 346 + type SYMCLK32_LE3_SRC_SEL;\ 347 + type SYMCLK32_LE2_EN;\ 348 + type SYMCLK32_LE3_EN;\ 349 + type DP_DTO_ENABLE[MAX_PIPES];\ 350 + type DSCCLK0_DTO_DB_EN;\ 351 + type DSCCLK1_DTO_DB_EN;\ 352 + type DSCCLK2_DTO_DB_EN;\ 353 + type DSCCLK3_DTO_DB_EN; 354 + 332 355 struct dccg_shift { 333 356 DCCG_REG_FIELD_LIST(uint8_t) 334 357 DCCG3_REG_FIELD_LIST(uint8_t) ··· 359 336 DCCG314_REG_FIELD_LIST(uint8_t) 360 337 DCCG32_REG_FIELD_LIST(uint8_t) 361 338 DCCG35_REG_FIELD_LIST(uint8_t) 339 + DCCG401_REG_FIELD_LIST(uint8_t) 362 340 }; 363 341 364 342 struct dccg_mask { ··· 369 345 DCCG314_REG_FIELD_LIST(uint32_t) 370 346 DCCG32_REG_FIELD_LIST(uint32_t) 371 347 DCCG35_REG_FIELD_LIST(uint32_t) 348 + DCCG401_REG_FIELD_LIST(uint32_t) 372 349 }; 373 350 374 351 struct dccg_registers { ··· 417 392 uint32_t SYMCLKC_CLOCK_ENABLE; 418 393 uint32_t SYMCLKD_CLOCK_ENABLE; 419 394 uint32_t SYMCLKE_CLOCK_ENABLE; 395 + uint32_t DP_DTO_MODULO[MAX_PIPES]; 396 + uint32_t DP_DTO_PHASE[MAX_PIPES]; 420 397 }; 421 398 422 399 struct dcn_dccg {

+32 -3

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h

··· 167 167 uint32_t DCHUBP_VMPG_CONFIG;\ 168 168 uint32_t UCLK_PSTATE_FORCE 169 169 170 + #define DCN401_HUBP_REG_COMMON_VARIABLE_LIST \ 171 + DCN32_HUBP_REG_COMMON_VARIABLE_LIST;\ 172 + uint32_t _3DLUT_FL_BIAS_SCALE;\ 173 + uint32_t _3DLUT_FL_CONFIG;\ 174 + uint32_t HUBP_3DLUT_ADDRESS_HIGH;\ 175 + uint32_t HUBP_3DLUT_ADDRESS_LOW;\ 176 + uint32_t HUBP_3DLUT_CONTROL;\ 177 + uint32_t HUBP_3DLUT_DLG_PARAM;\ 178 + 170 179 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 171 180 DCN_HUBP_REG_FIELD_BASE_LIST(type); \ 172 181 type DMDATA_ADDRESS_HIGH;\ ··· 250 241 type CURSOR_UCLK_PSTATE_FORCE_EN; \ 251 242 type CURSOR_UCLK_PSTATE_FORCE_VALUE 252 243 244 + #define DCN401_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 245 + DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type);\ 246 + type MALL_PREF_CMD_TYPE; \ 247 + type MALL_PREF_MODE; \ 248 + type HUBP0_3DLUT_FL_MODE; \ 249 + type HUBP0_3DLUT_FL_FORMAT; \ 250 + type HUBP0_3DLUT_FL_SCALE; \ 251 + type HUBP0_3DLUT_FL_BIAS; \ 252 + type HUBP_3DLUT_ENABLE;\ 253 + type HUBP_3DLUT_DONE;\ 254 + type HUBP_3DLUT_ADDRESSING_MODE;\ 255 + type HUBP_3DLUT_WIDTH;\ 256 + type HUBP_3DLUT_TMZ;\ 257 + type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\ 258 + type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\ 259 + type HUBP_3DLUT_CROSSBAR_SELECT_CR_R;\ 260 + type HUBP_3DLUT_ADDRESS_HIGH;\ 261 + type HUBP_3DLUT_ADDRESS_LOW;\ 262 + type REFCYC_PER_3DLUT_GROUP;\ 263 + 253 264 struct dcn_hubp2_registers { 254 - DCN32_HUBP_REG_COMMON_VARIABLE_LIST; 265 + DCN401_HUBP_REG_COMMON_VARIABLE_LIST; 255 266 }; 256 267 257 268 struct dcn_hubp2_shift { 258 - DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 269 + DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 259 270 }; 260 271 261 272 struct dcn_hubp2_mask { 262 - DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 273 + DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 263 274 }; 264 275 265 276 struct dcn20_hubp {

+11

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

··· 78 78 SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\ 79 79 SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\ 80 80 SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\ 81 + SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\ 81 82 SRI(DSCCIF_CONFIG0, DSCCIF, id),\ 82 83 SRI(DSCCIF_CONFIG1, DSCCIF, id),\ 83 84 SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) ··· 96 95 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ 97 96 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ 98 97 DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ 98 + DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ 99 99 DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ 100 100 DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ 101 101 DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ ··· 249 247 DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ 250 248 DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ 251 249 DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ 250 + DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \ 251 + DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \ 252 + DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \ 253 + DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \ 252 254 DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \ 253 255 DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 254 256 DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \ ··· 427 421 type DSCC_UPDATE_PENDING_STATUS; \ 428 422 type DSCC_UPDATE_TAKEN_STATUS; \ 429 423 type DSCC_UPDATE_TAKEN_ACK; \ 424 + type DSCC_TEST_DEBUG_BUS0_ROTATE; \ 425 + type DSCC_TEST_DEBUG_BUS1_ROTATE; \ 426 + type DSCC_TEST_DEBUG_BUS2_ROTATE; \ 427 + type DSCC_TEST_DEBUG_BUS3_ROTATE; \ 430 428 type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \ 431 429 type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \ 432 430 type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \ ··· 502 492 uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; 503 493 uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; 504 494 uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; 495 + uint32_t DSCC_TEST_DEBUG_BUS_ROTATE; 505 496 uint32_t DSCCIF_CONFIG0; 506 497 uint32_t DSCCIF_CONFIG1; 507 498 uint32_t DSCRM_DSC_FORWARD_CONFIG;

+24

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

··· 684 684 uint32_t DMU_CLK_CNTL; 685 685 uint32_t DCCG_GATE_DISABLE_CNTL4; 686 686 uint32_t DCCG_GATE_DISABLE_CNTL5; 687 + uint32_t DOMAIN22_PG_CONFIG; 688 + uint32_t DOMAIN23_PG_CONFIG; 689 + uint32_t DOMAIN24_PG_CONFIG; 690 + uint32_t DOMAIN25_PG_CONFIG; 691 + uint32_t DOMAIN22_PG_STATUS; 692 + uint32_t DOMAIN23_PG_STATUS; 693 + uint32_t DOMAIN24_PG_STATUS; 694 + uint32_t DOMAIN25_PG_STATUS; 687 695 }; 688 696 /* set field name */ 689 697 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ ··· 1222 1214 type DPIASYMCLK2_GATE_DISABLE;\ 1223 1215 type DPIASYMCLK3_GATE_DISABLE; 1224 1216 1217 + #define HWSEQ_DCN401_REG_FIELD_LIST(type) \ 1218 + type DOMAIN22_POWER_FORCEON; \ 1219 + type DOMAIN22_POWER_GATE; \ 1220 + type DOMAIN23_POWER_FORCEON; \ 1221 + type DOMAIN23_POWER_GATE; \ 1222 + type DOMAIN24_POWER_FORCEON; \ 1223 + type DOMAIN24_POWER_GATE; \ 1224 + type DOMAIN25_POWER_FORCEON; \ 1225 + type DOMAIN25_POWER_GATE; \ 1226 + type DOMAIN22_PGFSM_PWR_STATUS; \ 1227 + type DOMAIN23_PGFSM_PWR_STATUS; \ 1228 + type DOMAIN24_PGFSM_PWR_STATUS; \ 1229 + type DOMAIN25_PGFSM_PWR_STATUS; \ 1230 + type DOMAIN_DESIRED_PWR_STATE; 1225 1231 struct dce_hwseq_shift { 1226 1232 HWSEQ_REG_FIELD_LIST(uint8_t) 1227 1233 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) ··· 1243 1221 HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) 1244 1222 HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) 1245 1223 HWSEQ_DCN35_REG_FIELD_LIST(uint8_t) 1224 + HWSEQ_DCN401_REG_FIELD_LIST(uint8_t) 1246 1225 }; 1247 1226 1248 1227 struct dce_hwseq_mask { ··· 1253 1230 HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) 1254 1231 HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) 1255 1232 HWSEQ_DCN35_REG_FIELD_LIST(uint32_t) 1233 + HWSEQ_DCN401_REG_FIELD_LIST(uint32_t) 1256 1234 }; 1257 1235 1258 1236

+11

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

··· 190 190 CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\ 191 191 CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh) 192 192 193 + #define CLK_REG_LIST_DCN401() \ 194 + CLK_SR_DCN401(CLK0_CLK_PLL_REQ, CLK01, 0), \ 195 + CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ 196 + CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ 197 + CLK_SR_DCN401(CLK0_CLK2_DFS_CNTL, CLK01, 0), \ 198 + CLK_SR_DCN401(CLK0_CLK3_DFS_CNTL, CLK01, 0), \ 199 + CLK_SR_DCN401(CLK0_CLK4_DFS_CNTL, CLK01, 0) 200 + 201 + #define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \ 202 + CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) 203 + 193 204 #define CLK_REG_FIELD_LIST(type) \ 194 205 type DPREFCLK_SRC_SEL; \ 195 206 type DENTIST_DPREFCLK_WDIVIDER; \

+7

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

··· 200 200 uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; 201 201 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; 202 202 uint32_t OPTC_CLOCK_CONTROL; 203 + uint32_t OPTC_WIDTH_CONTROL2; 203 204 }; 204 205 205 206 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ ··· 591 590 type OTG_V_COUNT_STOP;\ 592 591 type OTG_V_COUNT_STOP_TIMER; 593 592 593 + #define TG_REG_FIELD_LIST_DCN401(type) \ 594 + type OPTC_SEGMENT_WIDTH_LAST; 595 + 596 + 594 597 struct dcn_optc_shift { 595 598 TG_REG_FIELD_LIST(uint8_t) 596 599 TG_REG_FIELD_LIST_DCN3_2(uint8_t) 597 600 TG_REG_FIELD_LIST_DCN3_5(uint8_t) 601 + TG_REG_FIELD_LIST_DCN401(uint8_t) 598 602 }; 599 603 600 604 struct dcn_optc_mask { 601 605 TG_REG_FIELD_LIST(uint32_t) 602 606 TG_REG_FIELD_LIST_DCN3_2(uint32_t) 603 607 TG_REG_FIELD_LIST_DCN3_5(uint32_t) 608 + TG_REG_FIELD_LIST_DCN401(uint32_t) 604 609 }; 605 610 606 611 void dcn10_timing_generator_init(struct optc *optc);