Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: integrator: get rid of preallocated irq descriptors

The Integrators were using the .nr_irqs field of the machine
descriptor to pre-allocate a number of descriptors at boot. This
is not right: the irq chip implementations should allocate
their descriptors themselves, and as a result the simple
irqdomain code warns about it.

Get rid of this by just deleting the .nr_irq field from the
machine descriptors but take care: doing so makes the default
implementation hog the first 16 IRQ numbers, so these cannot
be used by the still static IRQ number assignments in the
ATAG boot case. So for these, bump the IRQ numbers to begin
at 64 and upward.

Introduce an offset to offset all IRQ numbers if need be,
though we don't expect to do that again as device tree comes
along.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

+55 -60
+54 -55
arch/arm/mach-integrator/include/mach/irqs.h
··· 19 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 20 */ 21 21 22 - /* 23 - * Interrupt numbers 22 + /* 23 + * Interrupt numbers, all of the above are just static reservations 24 + * used so they can be encoded into device resources. They will finally 25 + * be done away with when switching to device tree. 24 26 */ 25 - #define IRQ_PIC_START 1 26 - #define IRQ_SOFTINT 1 27 - #define IRQ_UARTINT0 2 28 - #define IRQ_UARTINT1 3 29 - #define IRQ_KMIINT0 4 30 - #define IRQ_KMIINT1 5 31 - #define IRQ_TIMERINT0 6 32 - #define IRQ_TIMERINT1 7 33 - #define IRQ_TIMERINT2 8 34 - #define IRQ_RTCINT 9 35 - #define IRQ_AP_EXPINT0 10 36 - #define IRQ_AP_EXPINT1 11 37 - #define IRQ_AP_EXPINT2 12 38 - #define IRQ_AP_EXPINT3 13 39 - #define IRQ_AP_PCIINT0 14 40 - #define IRQ_AP_PCIINT1 15 41 - #define IRQ_AP_PCIINT2 16 42 - #define IRQ_AP_PCIINT3 17 43 - #define IRQ_AP_V3INT 18 44 - #define IRQ_AP_CPINT0 19 45 - #define IRQ_AP_CPINT1 20 46 - #define IRQ_AP_LBUSTIMEOUT 21 47 - #define IRQ_AP_APCINT 22 48 - #define IRQ_CP_CLCDCINT 23 49 - #define IRQ_CP_MMCIINT0 24 50 - #define IRQ_CP_MMCIINT1 25 51 - #define IRQ_CP_AACIINT 26 52 - #define IRQ_CP_CPPLDINT 27 53 - #define IRQ_CP_ETHINT 28 54 - #define IRQ_CP_TSPENINT 29 55 - #define IRQ_PIC_END 29 27 + #define IRQ_PIC_START 64 28 + #define IRQ_SOFTINT (IRQ_PIC_START+0) 29 + #define IRQ_UARTINT0 (IRQ_PIC_START+1) 30 + #define IRQ_UARTINT1 (IRQ_PIC_START+2) 31 + #define IRQ_KMIINT0 (IRQ_PIC_START+3) 32 + #define IRQ_KMIINT1 (IRQ_PIC_START+4) 33 + #define IRQ_TIMERINT0 (IRQ_PIC_START+5) 34 + #define IRQ_TIMERINT1 (IRQ_PIC_START+6) 35 + #define IRQ_TIMERINT2 (IRQ_PIC_START+7) 36 + #define IRQ_RTCINT (IRQ_PIC_START+8) 37 + #define IRQ_AP_EXPINT0 (IRQ_PIC_START+9) 38 + #define IRQ_AP_EXPINT1 (IRQ_PIC_START+10) 39 + #define IRQ_AP_EXPINT2 (IRQ_PIC_START+11) 40 + #define IRQ_AP_EXPINT3 (IRQ_PIC_START+12) 41 + #define IRQ_AP_PCIINT0 (IRQ_PIC_START+13) 42 + #define IRQ_AP_PCIINT1 (IRQ_PIC_START+14) 43 + #define IRQ_AP_PCIINT2 (IRQ_PIC_START+15) 44 + #define IRQ_AP_PCIINT3 (IRQ_PIC_START+16) 45 + #define IRQ_AP_V3INT (IRQ_PIC_START+17) 46 + #define IRQ_AP_CPINT0 (IRQ_PIC_START+18) 47 + #define IRQ_AP_CPINT1 (IRQ_PIC_START+19) 48 + #define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20) 49 + #define IRQ_AP_APCINT (IRQ_PIC_START+21) 50 + #define IRQ_CP_CLCDCINT (IRQ_PIC_START+22) 51 + #define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23) 52 + #define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24) 53 + #define IRQ_CP_AACIINT (IRQ_PIC_START+25) 54 + #define IRQ_CP_CPPLDINT (IRQ_PIC_START+26) 55 + #define IRQ_CP_ETHINT (IRQ_PIC_START+27) 56 + #define IRQ_CP_TSPENINT (IRQ_PIC_START+28) 57 + #define IRQ_PIC_END (IRQ_PIC_START+28) 56 58 57 - #define IRQ_CIC_START 32 58 - #define IRQ_CM_SOFTINT 32 59 - #define IRQ_CM_COMMRX 33 60 - #define IRQ_CM_COMMTX 34 61 - #define IRQ_CIC_END 34 59 + #define IRQ_CIC_START (IRQ_PIC_END+1) 60 + #define IRQ_CM_SOFTINT (IRQ_CIC_START+0) 61 + #define IRQ_CM_COMMRX (IRQ_CIC_START+1) 62 + #define IRQ_CM_COMMTX (IRQ_CIC_START+2) 63 + #define IRQ_CIC_END (IRQ_CIC_START+2) 62 64 63 65 /* 64 66 * IntegratorCP only 65 67 */ 66 - #define IRQ_SIC_START 35 67 - #define IRQ_SIC_CP_SOFTINT 35 68 - #define IRQ_SIC_CP_RI0 36 69 - #define IRQ_SIC_CP_RI1 37 70 - #define IRQ_SIC_CP_CARDIN 38 71 - #define IRQ_SIC_CP_LMINT0 39 72 - #define IRQ_SIC_CP_LMINT1 40 73 - #define IRQ_SIC_CP_LMINT2 41 74 - #define IRQ_SIC_CP_LMINT3 42 75 - #define IRQ_SIC_CP_LMINT4 43 76 - #define IRQ_SIC_CP_LMINT5 44 77 - #define IRQ_SIC_CP_LMINT6 45 78 - #define IRQ_SIC_CP_LMINT7 46 79 - #define IRQ_SIC_END 46 80 - 81 - #define NR_IRQS_INTEGRATOR_AP 34 82 - #define NR_IRQS_INTEGRATOR_CP 47 68 + #define IRQ_SIC_START (IRQ_CIC_END+1) 69 + #define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0) 70 + #define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1) 71 + #define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2) 72 + #define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3) 73 + #define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4) 74 + #define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5) 75 + #define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6) 76 + #define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7) 77 + #define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8) 78 + #define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9) 79 + #define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10) 80 + #define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11) 81 + #define IRQ_SIC_END (IRQ_SIC_START+11)
-2
arch/arm/mach-integrator/integrator_ap.c
··· 499 499 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") 500 500 .reserve = integrator_reserve, 501 501 .map_io = ap_map_io, 502 - .nr_irqs = NR_IRQS_INTEGRATOR_AP, 503 502 .init_early = ap_init_early, 504 503 .init_irq = ap_init_irq_of, 505 504 .handle_irq = fpga_handle_irq, ··· 608 609 .atag_offset = 0x100, 609 610 .reserve = integrator_reserve, 610 611 .map_io = ap_map_io, 611 - .nr_irqs = NR_IRQS_INTEGRATOR_AP, 612 612 .init_early = ap_init_early, 613 613 .init_irq = ap_init_irq, 614 614 .handle_irq = fpga_handle_irq,
+1 -3
arch/arm/mach-integrator/integrator_cp.c
··· 350 350 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") 351 351 .reserve = integrator_reserve, 352 352 .map_io = intcp_map_io, 353 - .nr_irqs = NR_IRQS_INTEGRATOR_CP, 354 353 .init_early = intcp_init_early, 355 354 .init_irq = intcp_init_irq_of, 356 355 .handle_irq = fpga_handle_irq, ··· 422 423 u32 pic_mask, cic_mask, sic_mask; 423 424 424 425 /* These masks are for the HW IRQ registers */ 425 - pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); 426 + pic_mask = ~((~0u) << (11 - 0)); 426 427 pic_mask |= (~((~0u) << (29 - 22))) << 22; 427 428 cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); 428 429 sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); ··· 503 504 .atag_offset = 0x100, 504 505 .reserve = integrator_reserve, 505 506 .map_io = intcp_map_io, 506 - .nr_irqs = NR_IRQS_INTEGRATOR_CP, 507 507 .init_early = intcp_init_early, 508 508 .init_irq = intcp_init_irq, 509 509 .handle_irq = fpga_handle_irq,