tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ASoC: mediatek: mt8188: add control for timing select

Add mixer control for irq and memif timing selection.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230116034131.23943-10-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Trevor Wu and committed by
Mark Brown da387d32 bf106bf0

+506
+506
sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
··· 1394 1394 {"O041", "I169 Switch", "I169"}, 1395 1395 }; 1396 1396 1397 + static const char * const mt8188_afe_1x_en_sel_text[] = { 1398 + "a1sys_a2sys", "a3sys", "a4sys", 1399 + }; 1400 + 1401 + static const unsigned int mt8188_afe_1x_en_sel_values[] = { 1402 + 0, 1, 2, 1403 + }; 1404 + 1405 + static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, 1406 + A3_A4_TIMING_SEL1, 18, 0x3, 1407 + mt8188_afe_1x_en_sel_text, 1408 + mt8188_afe_1x_en_sel_values); 1409 + static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, 1410 + A3_A4_TIMING_SEL1, 20, 0x3, 1411 + mt8188_afe_1x_en_sel_text, 1412 + mt8188_afe_1x_en_sel_values); 1413 + static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, 1414 + A3_A4_TIMING_SEL1, 22, 0x3, 1415 + mt8188_afe_1x_en_sel_text, 1416 + mt8188_afe_1x_en_sel_values); 1417 + static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, 1418 + A3_A4_TIMING_SEL1, 24, 0x3, 1419 + mt8188_afe_1x_en_sel_text, 1420 + mt8188_afe_1x_en_sel_values); 1421 + static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, 1422 + A3_A4_TIMING_SEL1, 26, 0x3, 1423 + mt8188_afe_1x_en_sel_text, 1424 + mt8188_afe_1x_en_sel_values); 1425 + static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, 1426 + A3_A4_TIMING_SEL1, 28, 0x3, 1427 + mt8188_afe_1x_en_sel_text, 1428 + mt8188_afe_1x_en_sel_values); 1429 + static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, 1430 + A3_A4_TIMING_SEL1, 30, 0x3, 1431 + mt8188_afe_1x_en_sel_text, 1432 + mt8188_afe_1x_en_sel_values); 1433 + static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, 1434 + A3_A4_TIMING_SEL1, 0, 0x3, 1435 + mt8188_afe_1x_en_sel_text, 1436 + mt8188_afe_1x_en_sel_values); 1437 + static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, 1438 + A3_A4_TIMING_SEL1, 2, 0x3, 1439 + mt8188_afe_1x_en_sel_text, 1440 + mt8188_afe_1x_en_sel_values); 1441 + static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, 1442 + A3_A4_TIMING_SEL1, 4, 0x3, 1443 + mt8188_afe_1x_en_sel_text, 1444 + mt8188_afe_1x_en_sel_values); 1445 + static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, 1446 + A3_A4_TIMING_SEL1, 6, 0x3, 1447 + mt8188_afe_1x_en_sel_text, 1448 + mt8188_afe_1x_en_sel_values); 1449 + static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, 1450 + A3_A4_TIMING_SEL1, 8, 0x3, 1451 + mt8188_afe_1x_en_sel_text, 1452 + mt8188_afe_1x_en_sel_values); 1453 + static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, 1454 + A3_A4_TIMING_SEL1, 10, 0x3, 1455 + mt8188_afe_1x_en_sel_text, 1456 + mt8188_afe_1x_en_sel_values); 1457 + static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, 1458 + A3_A4_TIMING_SEL1, 12, 0x3, 1459 + mt8188_afe_1x_en_sel_text, 1460 + mt8188_afe_1x_en_sel_values); 1461 + static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, 1462 + A3_A4_TIMING_SEL1, 14, 0x3, 1463 + mt8188_afe_1x_en_sel_text, 1464 + mt8188_afe_1x_en_sel_values); 1465 + static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, 1466 + A3_A4_TIMING_SEL1, 16, 0x3, 1467 + mt8188_afe_1x_en_sel_text, 1468 + mt8188_afe_1x_en_sel_values); 1469 + 1470 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, 1471 + A3_A4_TIMING_SEL6, 0, 0x3, 1472 + mt8188_afe_1x_en_sel_text, 1473 + mt8188_afe_1x_en_sel_values); 1474 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, 1475 + A3_A4_TIMING_SEL6, 2, 0x3, 1476 + mt8188_afe_1x_en_sel_text, 1477 + mt8188_afe_1x_en_sel_values); 1478 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, 1479 + A3_A4_TIMING_SEL6, 4, 0x3, 1480 + mt8188_afe_1x_en_sel_text, 1481 + mt8188_afe_1x_en_sel_values); 1482 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, 1483 + A3_A4_TIMING_SEL6, 6, 0x3, 1484 + mt8188_afe_1x_en_sel_text, 1485 + mt8188_afe_1x_en_sel_values); 1486 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, 1487 + A3_A4_TIMING_SEL6, 8, 0x3, 1488 + mt8188_afe_1x_en_sel_text, 1489 + mt8188_afe_1x_en_sel_values); 1490 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, 1491 + A3_A4_TIMING_SEL6, 10, 0x3, 1492 + mt8188_afe_1x_en_sel_text, 1493 + mt8188_afe_1x_en_sel_values); 1494 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, 1495 + A3_A4_TIMING_SEL6, 12, 0x3, 1496 + mt8188_afe_1x_en_sel_text, 1497 + mt8188_afe_1x_en_sel_values); 1498 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, 1499 + A3_A4_TIMING_SEL6, 14, 0x3, 1500 + mt8188_afe_1x_en_sel_text, 1501 + mt8188_afe_1x_en_sel_values); 1502 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, 1503 + A3_A4_TIMING_SEL6, 16, 0x3, 1504 + mt8188_afe_1x_en_sel_text, 1505 + mt8188_afe_1x_en_sel_values); 1506 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, 1507 + A3_A4_TIMING_SEL6, 18, 0x3, 1508 + mt8188_afe_1x_en_sel_text, 1509 + mt8188_afe_1x_en_sel_values); 1510 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, 1511 + A3_A4_TIMING_SEL6, 20, 0x3, 1512 + mt8188_afe_1x_en_sel_text, 1513 + mt8188_afe_1x_en_sel_values); 1514 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, 1515 + A3_A4_TIMING_SEL6, 22, 0x3, 1516 + mt8188_afe_1x_en_sel_text, 1517 + mt8188_afe_1x_en_sel_values); 1518 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, 1519 + A3_A4_TIMING_SEL6, 24, 0x3, 1520 + mt8188_afe_1x_en_sel_text, 1521 + mt8188_afe_1x_en_sel_values); 1522 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, 1523 + A3_A4_TIMING_SEL6, 26, 0x3, 1524 + mt8188_afe_1x_en_sel_text, 1525 + mt8188_afe_1x_en_sel_values); 1526 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, 1527 + A3_A4_TIMING_SEL6, 28, 0x3, 1528 + mt8188_afe_1x_en_sel_text, 1529 + mt8188_afe_1x_en_sel_values); 1530 + static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, 1531 + A3_A4_TIMING_SEL6, 30, 0x3, 1532 + mt8188_afe_1x_en_sel_text, 1533 + mt8188_afe_1x_en_sel_values); 1534 + 1535 + static const char * const mt8188_afe_fs_timing_sel_text[] = { 1536 + "asys", 1537 + "etdmout1_1x_en", 1538 + "etdmout2_1x_en", 1539 + "etdmout3_1x_en", 1540 + "etdmin1_1x_en", 1541 + "etdmin2_1x_en", 1542 + "etdmin1_nx_en", 1543 + "etdmin2_nx_en", 1544 + }; 1545 + 1546 + static const unsigned int mt8188_afe_fs_timing_sel_values[] = { 1547 + 0, 1548 + MT8188_ETDM_OUT1_1X_EN, 1549 + MT8188_ETDM_OUT2_1X_EN, 1550 + MT8188_ETDM_OUT3_1X_EN, 1551 + MT8188_ETDM_IN1_1X_EN, 1552 + MT8188_ETDM_IN2_1X_EN, 1553 + MT8188_ETDM_IN1_NX_EN, 1554 + MT8188_ETDM_IN2_NX_EN, 1555 + }; 1556 + 1557 + static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum, 1558 + SND_SOC_NOPM, 0, 0, 1559 + mt8188_afe_fs_timing_sel_text, 1560 + mt8188_afe_fs_timing_sel_values); 1561 + static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum, 1562 + SND_SOC_NOPM, 0, 0, 1563 + mt8188_afe_fs_timing_sel_text, 1564 + mt8188_afe_fs_timing_sel_values); 1565 + static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum, 1566 + SND_SOC_NOPM, 0, 0, 1567 + mt8188_afe_fs_timing_sel_text, 1568 + mt8188_afe_fs_timing_sel_values); 1569 + static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum, 1570 + SND_SOC_NOPM, 0, 0, 1571 + mt8188_afe_fs_timing_sel_text, 1572 + mt8188_afe_fs_timing_sel_values); 1573 + static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum, 1574 + SND_SOC_NOPM, 0, 0, 1575 + mt8188_afe_fs_timing_sel_text, 1576 + mt8188_afe_fs_timing_sel_values); 1577 + static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum, 1578 + SND_SOC_NOPM, 0, 0, 1579 + mt8188_afe_fs_timing_sel_text, 1580 + mt8188_afe_fs_timing_sel_values); 1581 + static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum, 1582 + SND_SOC_NOPM, 0, 0, 1583 + mt8188_afe_fs_timing_sel_text, 1584 + mt8188_afe_fs_timing_sel_values); 1585 + static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum, 1586 + SND_SOC_NOPM, 0, 0, 1587 + mt8188_afe_fs_timing_sel_text, 1588 + mt8188_afe_fs_timing_sel_values); 1589 + static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum, 1590 + SND_SOC_NOPM, 0, 0, 1591 + mt8188_afe_fs_timing_sel_text, 1592 + mt8188_afe_fs_timing_sel_values); 1593 + static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum, 1594 + SND_SOC_NOPM, 0, 0, 1595 + mt8188_afe_fs_timing_sel_text, 1596 + mt8188_afe_fs_timing_sel_values); 1597 + 1598 + static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1599 + struct snd_ctl_elem_value *ucontrol) 1600 + { 1601 + struct snd_soc_component *component = 1602 + snd_soc_kcontrol_component(kcontrol); 1603 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1604 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1605 + struct mtk_dai_memif_priv *memif_priv; 1606 + unsigned int dai_id = kcontrol->id.device; 1607 + long val = ucontrol->value.integer.value[0]; 1608 + int ret = 0; 1609 + 1610 + memif_priv = afe_priv->dai_priv[dai_id]; 1611 + 1612 + if (val == memif_priv->asys_timing_sel) 1613 + return 0; 1614 + 1615 + ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1616 + 1617 + memif_priv->asys_timing_sel = val; 1618 + 1619 + return ret; 1620 + } 1621 + 1622 + static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, 1623 + struct snd_ctl_elem_value *ucontrol) 1624 + { 1625 + struct snd_soc_component *component = 1626 + snd_soc_kcontrol_component(kcontrol); 1627 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1628 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1629 + unsigned int id = kcontrol->id.device; 1630 + long val = ucontrol->value.integer.value[0]; 1631 + int ret = 0; 1632 + 1633 + if (val == afe_priv->irq_priv[id].asys_timing_sel) 1634 + return 0; 1635 + 1636 + ret = snd_soc_put_enum_double(kcontrol, ucontrol); 1637 + 1638 + afe_priv->irq_priv[id].asys_timing_sel = val; 1639 + 1640 + return ret; 1641 + } 1642 + 1643 + static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol, 1644 + struct snd_ctl_elem_value *ucontrol) 1645 + { 1646 + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1647 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1648 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1649 + struct mtk_dai_memif_priv *memif_priv; 1650 + unsigned int dai_id = kcontrol->id.device; 1651 + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1652 + 1653 + memif_priv = afe_priv->dai_priv[dai_id]; 1654 + 1655 + ucontrol->value.enumerated.item[0] = 1656 + snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1657 + 1658 + return 0; 1659 + } 1660 + 1661 + static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol, 1662 + struct snd_ctl_elem_value *ucontrol) 1663 + { 1664 + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1665 + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 1666 + struct mt8188_afe_private *afe_priv = afe->platform_priv; 1667 + struct mtk_dai_memif_priv *memif_priv; 1668 + unsigned int dai_id = kcontrol->id.device; 1669 + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1670 + unsigned int *item = ucontrol->value.enumerated.item; 1671 + unsigned int prev_item = 0; 1672 + 1673 + if (item[0] >= e->items) 1674 + return -EINVAL; 1675 + 1676 + memif_priv = afe_priv->dai_priv[dai_id]; 1677 + 1678 + prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing); 1679 + 1680 + if (item[0] == prev_item) 1681 + return 0; 1682 + 1683 + memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]); 1684 + 1685 + return 1; 1686 + } 1687 + 1688 + static const struct snd_kcontrol_new mt8188_memif_controls[] = { 1689 + MT8188_SOC_ENUM_EXT("dl2_1x_en_sel", 1690 + dl2_1x_en_sel_enum, 1691 + snd_soc_get_enum_double, 1692 + mt8188_memif_1x_en_sel_put, 1693 + MT8188_AFE_MEMIF_DL2), 1694 + MT8188_SOC_ENUM_EXT("dl3_1x_en_sel", 1695 + dl3_1x_en_sel_enum, 1696 + snd_soc_get_enum_double, 1697 + mt8188_memif_1x_en_sel_put, 1698 + MT8188_AFE_MEMIF_DL3), 1699 + MT8188_SOC_ENUM_EXT("dl6_1x_en_sel", 1700 + dl6_1x_en_sel_enum, 1701 + snd_soc_get_enum_double, 1702 + mt8188_memif_1x_en_sel_put, 1703 + MT8188_AFE_MEMIF_DL6), 1704 + MT8188_SOC_ENUM_EXT("dl7_1x_en_sel", 1705 + dl7_1x_en_sel_enum, 1706 + snd_soc_get_enum_double, 1707 + mt8188_memif_1x_en_sel_put, 1708 + MT8188_AFE_MEMIF_DL7), 1709 + MT8188_SOC_ENUM_EXT("dl8_1x_en_sel", 1710 + dl8_1x_en_sel_enum, 1711 + snd_soc_get_enum_double, 1712 + mt8188_memif_1x_en_sel_put, 1713 + MT8188_AFE_MEMIF_DL8), 1714 + MT8188_SOC_ENUM_EXT("dl10_1x_en_sel", 1715 + dl10_1x_en_sel_enum, 1716 + snd_soc_get_enum_double, 1717 + mt8188_memif_1x_en_sel_put, 1718 + MT8188_AFE_MEMIF_DL10), 1719 + MT8188_SOC_ENUM_EXT("dl11_1x_en_sel", 1720 + dl11_1x_en_sel_enum, 1721 + snd_soc_get_enum_double, 1722 + mt8188_memif_1x_en_sel_put, 1723 + MT8188_AFE_MEMIF_DL11), 1724 + MT8188_SOC_ENUM_EXT("ul1_1x_en_sel", 1725 + ul1_1x_en_sel_enum, 1726 + snd_soc_get_enum_double, 1727 + mt8188_memif_1x_en_sel_put, 1728 + MT8188_AFE_MEMIF_UL1), 1729 + MT8188_SOC_ENUM_EXT("ul2_1x_en_sel", 1730 + ul2_1x_en_sel_enum, 1731 + snd_soc_get_enum_double, 1732 + mt8188_memif_1x_en_sel_put, 1733 + MT8188_AFE_MEMIF_UL2), 1734 + MT8188_SOC_ENUM_EXT("ul3_1x_en_sel", 1735 + ul3_1x_en_sel_enum, 1736 + snd_soc_get_enum_double, 1737 + mt8188_memif_1x_en_sel_put, 1738 + MT8188_AFE_MEMIF_UL3), 1739 + MT8188_SOC_ENUM_EXT("ul4_1x_en_sel", 1740 + ul4_1x_en_sel_enum, 1741 + snd_soc_get_enum_double, 1742 + mt8188_memif_1x_en_sel_put, 1743 + MT8188_AFE_MEMIF_UL4), 1744 + MT8188_SOC_ENUM_EXT("ul5_1x_en_sel", 1745 + ul5_1x_en_sel_enum, 1746 + snd_soc_get_enum_double, 1747 + mt8188_memif_1x_en_sel_put, 1748 + MT8188_AFE_MEMIF_UL5), 1749 + MT8188_SOC_ENUM_EXT("ul6_1x_en_sel", 1750 + ul6_1x_en_sel_enum, 1751 + snd_soc_get_enum_double, 1752 + mt8188_memif_1x_en_sel_put, 1753 + MT8188_AFE_MEMIF_UL6), 1754 + MT8188_SOC_ENUM_EXT("ul8_1x_en_sel", 1755 + ul8_1x_en_sel_enum, 1756 + snd_soc_get_enum_double, 1757 + mt8188_memif_1x_en_sel_put, 1758 + MT8188_AFE_MEMIF_UL8), 1759 + MT8188_SOC_ENUM_EXT("ul9_1x_en_sel", 1760 + ul9_1x_en_sel_enum, 1761 + snd_soc_get_enum_double, 1762 + mt8188_memif_1x_en_sel_put, 1763 + MT8188_AFE_MEMIF_UL9), 1764 + MT8188_SOC_ENUM_EXT("ul10_1x_en_sel", 1765 + ul10_1x_en_sel_enum, 1766 + snd_soc_get_enum_double, 1767 + mt8188_memif_1x_en_sel_put, 1768 + MT8188_AFE_MEMIF_UL10), 1769 + MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel", 1770 + asys_irq1_1x_en_sel_enum, 1771 + snd_soc_get_enum_double, 1772 + mt8188_asys_irq_1x_en_sel_put, 1773 + MT8188_AFE_IRQ_13), 1774 + MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel", 1775 + asys_irq2_1x_en_sel_enum, 1776 + snd_soc_get_enum_double, 1777 + mt8188_asys_irq_1x_en_sel_put, 1778 + MT8188_AFE_IRQ_14), 1779 + MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel", 1780 + asys_irq3_1x_en_sel_enum, 1781 + snd_soc_get_enum_double, 1782 + mt8188_asys_irq_1x_en_sel_put, 1783 + MT8188_AFE_IRQ_15), 1784 + MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel", 1785 + asys_irq4_1x_en_sel_enum, 1786 + snd_soc_get_enum_double, 1787 + mt8188_asys_irq_1x_en_sel_put, 1788 + MT8188_AFE_IRQ_16), 1789 + MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel", 1790 + asys_irq5_1x_en_sel_enum, 1791 + snd_soc_get_enum_double, 1792 + mt8188_asys_irq_1x_en_sel_put, 1793 + MT8188_AFE_IRQ_17), 1794 + MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel", 1795 + asys_irq6_1x_en_sel_enum, 1796 + snd_soc_get_enum_double, 1797 + mt8188_asys_irq_1x_en_sel_put, 1798 + MT8188_AFE_IRQ_18), 1799 + MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel", 1800 + asys_irq7_1x_en_sel_enum, 1801 + snd_soc_get_enum_double, 1802 + mt8188_asys_irq_1x_en_sel_put, 1803 + MT8188_AFE_IRQ_19), 1804 + MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel", 1805 + asys_irq8_1x_en_sel_enum, 1806 + snd_soc_get_enum_double, 1807 + mt8188_asys_irq_1x_en_sel_put, 1808 + MT8188_AFE_IRQ_20), 1809 + MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel", 1810 + asys_irq9_1x_en_sel_enum, 1811 + snd_soc_get_enum_double, 1812 + mt8188_asys_irq_1x_en_sel_put, 1813 + MT8188_AFE_IRQ_21), 1814 + MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel", 1815 + asys_irq10_1x_en_sel_enum, 1816 + snd_soc_get_enum_double, 1817 + mt8188_asys_irq_1x_en_sel_put, 1818 + MT8188_AFE_IRQ_22), 1819 + MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel", 1820 + asys_irq11_1x_en_sel_enum, 1821 + snd_soc_get_enum_double, 1822 + mt8188_asys_irq_1x_en_sel_put, 1823 + MT8188_AFE_IRQ_23), 1824 + MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel", 1825 + asys_irq12_1x_en_sel_enum, 1826 + snd_soc_get_enum_double, 1827 + mt8188_asys_irq_1x_en_sel_put, 1828 + MT8188_AFE_IRQ_24), 1829 + MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel", 1830 + asys_irq13_1x_en_sel_enum, 1831 + snd_soc_get_enum_double, 1832 + mt8188_asys_irq_1x_en_sel_put, 1833 + MT8188_AFE_IRQ_25), 1834 + MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel", 1835 + asys_irq14_1x_en_sel_enum, 1836 + snd_soc_get_enum_double, 1837 + mt8188_asys_irq_1x_en_sel_put, 1838 + MT8188_AFE_IRQ_26), 1839 + MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel", 1840 + asys_irq15_1x_en_sel_enum, 1841 + snd_soc_get_enum_double, 1842 + mt8188_asys_irq_1x_en_sel_put, 1843 + MT8188_AFE_IRQ_27), 1844 + MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel", 1845 + asys_irq16_1x_en_sel_enum, 1846 + snd_soc_get_enum_double, 1847 + mt8188_asys_irq_1x_en_sel_put, 1848 + MT8188_AFE_IRQ_28), 1849 + MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel", 1850 + dl2_fs_timing_sel_enum, 1851 + mt8188_memif_fs_timing_sel_get, 1852 + mt8188_memif_fs_timing_sel_put, 1853 + MT8188_AFE_MEMIF_DL2), 1854 + MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel", 1855 + dl3_fs_timing_sel_enum, 1856 + mt8188_memif_fs_timing_sel_get, 1857 + mt8188_memif_fs_timing_sel_put, 1858 + MT8188_AFE_MEMIF_DL3), 1859 + MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel", 1860 + dl6_fs_timing_sel_enum, 1861 + mt8188_memif_fs_timing_sel_get, 1862 + mt8188_memif_fs_timing_sel_put, 1863 + MT8188_AFE_MEMIF_DL6), 1864 + MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel", 1865 + dl8_fs_timing_sel_enum, 1866 + mt8188_memif_fs_timing_sel_get, 1867 + mt8188_memif_fs_timing_sel_put, 1868 + MT8188_AFE_MEMIF_DL8), 1869 + MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel", 1870 + dl11_fs_timing_sel_enum, 1871 + mt8188_memif_fs_timing_sel_get, 1872 + mt8188_memif_fs_timing_sel_put, 1873 + MT8188_AFE_MEMIF_DL11), 1874 + MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel", 1875 + ul2_fs_timing_sel_enum, 1876 + mt8188_memif_fs_timing_sel_get, 1877 + mt8188_memif_fs_timing_sel_put, 1878 + MT8188_AFE_MEMIF_UL2), 1879 + MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel", 1880 + ul4_fs_timing_sel_enum, 1881 + mt8188_memif_fs_timing_sel_get, 1882 + mt8188_memif_fs_timing_sel_put, 1883 + MT8188_AFE_MEMIF_UL4), 1884 + MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel", 1885 + ul5_fs_timing_sel_enum, 1886 + mt8188_memif_fs_timing_sel_get, 1887 + mt8188_memif_fs_timing_sel_put, 1888 + MT8188_AFE_MEMIF_UL5), 1889 + MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel", 1890 + ul9_fs_timing_sel_enum, 1891 + mt8188_memif_fs_timing_sel_get, 1892 + mt8188_memif_fs_timing_sel_put, 1893 + MT8188_AFE_MEMIF_UL9), 1894 + MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel", 1895 + ul10_fs_timing_sel_enum, 1896 + mt8188_memif_fs_timing_sel_get, 1897 + mt8188_memif_fs_timing_sel_put, 1898 + MT8188_AFE_MEMIF_UL10), 1899 + }; 1900 + 1397 1901 static const struct snd_soc_component_driver mt8188_afe_pcm_dai_component = { 1398 1902 .name = "mt8188-afe-pcm-dai", 1399 1903 }; ··· 3087 2583 dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets); 3088 2584 dai->dapm_routes = mt8188_memif_routes; 3089 2585 dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes); 2586 + dai->controls = mt8188_memif_controls; 2587 + dai->num_controls = ARRAY_SIZE(mt8188_memif_controls); 3090 2588 3091 2589 return init_memif_priv_data(afe); 3092 2590 }