tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARC: Disintegrate arcregs.h
* Move the various sub-system defines/types into relevant files/functions
(reduces compilation time)
* move CPU specific stuff out of asm/tlb.h into asm/mmu.h
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
+139
-162
-116
arch/arc/include/asm/arcregs.h
-116
arch/arc/include/asm/arcregs.h
···
20
20
#define ARC_REG_PERIBASE_BCR 0x69
21
21
#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
22
22
#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
23
-
#define ARC_REG_MMU_BCR 0x6f
24
23
#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
25
24
#define ARC_REG_TIMERS_BCR 0x75
26
25
#define ARC_REG_ICCM_BCR 0x78
···
33
34
#define ARC_REG_D_UNCACH_BCR 0x6A
34
35
35
36
/* status32 Bits Positions */
36
-
#define STATUS_H_BIT 0 /* CPU Halted */
37
-
#define STATUS_E1_BIT 1 /* Int 1 enable */
38
-
#define STATUS_E2_BIT 2 /* Int 2 enable */
39
-
#define STATUS_A1_BIT 3 /* Int 1 active */
40
-
#define STATUS_A2_BIT 4 /* Int 2 active */
41
37
#define STATUS_AE_BIT 5 /* Exception active */
42
38
#define STATUS_DE_BIT 6 /* PC is in delay slot */
43
39
#define STATUS_U_BIT 7 /* User/Kernel mode */
44
40
#define STATUS_L_BIT 12 /* Loop inhibit */
45
41
46
42
/* These masks correspond to the status word(STATUS_32) bits */
47
-
#define STATUS_H_MASK (1<<STATUS_H_BIT)
48
-
#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
49
-
#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
50
-
#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
51
-
#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
52
43
#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
53
44
#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
54
45
#define STATUS_U_MASK (1<<STATUS_U_BIT)
···
76
87
/* Auxiliary registers */
77
88
#define AUX_IDENTITY 4
78
89
#define AUX_INTR_VEC_BASE 0x25
79
-
#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
80
-
#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
81
-
#define AUX_IRQ_LV12 0x43 /* interrupt level register */
82
90
83
-
#define AUX_IENABLE 0x40c
84
-
#define AUX_ITRIGGER 0x40d
85
-
#define AUX_IPULSE 0x415
86
-
87
-
/* Timer related Aux registers */
88
-
#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
89
-
#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
90
-
#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
91
-
#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
92
-
#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
93
-
#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
94
-
95
-
#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
96
-
#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
97
-
98
-
/* MMU Management regs */
99
-
#define ARC_REG_TLBPD0 0x405
100
-
#define ARC_REG_TLBPD1 0x406
101
-
#define ARC_REG_TLBINDEX 0x407
102
-
#define ARC_REG_TLBCOMMAND 0x408
103
-
#define ARC_REG_PID 0x409
104
-
#define ARC_REG_SCRATCH_DATA0 0x418
105
-
106
-
/* Bits in MMU PID register */
107
-
#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
108
-
109
-
/* Error code if probe fails */
110
-
#define TLB_LKUP_ERR 0x80000000
111
-
112
-
/* TLB Commands */
113
-
#define TLBWrite 0x1
114
-
#define TLBRead 0x2
115
-
#define TLBGetIndex 0x3
116
-
#define TLBProbe 0x4
117
-
118
-
#if (CONFIG_ARC_MMU_VER >= 2)
119
-
#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
120
-
#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
121
-
#else
122
-
#undef TLBWriteNI /* These cmds don't exist on older MMU */
123
-
#undef TLBIVUTLB
124
-
#endif
125
-
126
-
/* Instruction cache related Auxiliary registers */
127
-
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
128
-
#define ARC_REG_IC_IVIC 0x10
129
-
#define ARC_REG_IC_CTRL 0x11
130
-
#define ARC_REG_IC_IVIL 0x19
131
-
#if (CONFIG_ARC_MMU_VER > 2)
132
-
#define ARC_REG_IC_PTAG 0x1E
133
-
#endif
134
-
135
-
/* Bit val in IC_CTRL */
136
-
#define IC_CTRL_CACHE_DISABLE 0x1
137
-
138
-
/* Data cache related Auxiliary registers */
139
-
#define ARC_REG_DC_BCR 0x72
140
-
#define ARC_REG_DC_IVDC 0x47
141
-
#define ARC_REG_DC_CTRL 0x48
142
-
#define ARC_REG_DC_IVDL 0x4A
143
-
#define ARC_REG_DC_FLSH 0x4B
144
-
#define ARC_REG_DC_FLDL 0x4C
145
-
#if (CONFIG_ARC_MMU_VER > 2)
146
-
#define ARC_REG_DC_PTAG 0x5C
147
-
#endif
148
-
149
-
/* Bit val in DC_CTRL */
150
-
#define DC_CTRL_INV_MODE_FLUSH 0x40
151
-
#define DC_CTRL_FLUSH_STATUS 0x100
152
-
153
-
/* MMU Management regs */
154
-
#define ARC_REG_PID 0x409
155
-
#define ARC_REG_SCRATCH_DATA0 0x418
156
-
157
-
/* Bits in MMU PID register */
158
-
#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
159
91
160
92
/*
161
93
* Floating Pt Registers
···
203
293
#endif
204
294
};
205
295
206
-
struct bcr_mmu_1_2 {
207
-
#ifdef CONFIG_CPU_BIG_ENDIAN
208
-
unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
209
-
#else
210
-
unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
211
-
#endif
212
-
};
213
-
214
-
struct bcr_mmu_3 {
215
-
#ifdef CONFIG_CPU_BIG_ENDIAN
216
-
unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
217
-
u_itlb:4, u_dtlb:4;
218
-
#else
219
-
unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
220
-
ways:4, ver:8;
221
-
#endif
222
-
};
223
-
224
296
#define EXTN_SWAP_VALID 0x1
225
297
#define EXTN_NORM_VALID 0x2
226
298
#define EXTN_MINMAX_VALID 0x2
···
232
340
unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
233
341
#else
234
342
unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
235
-
#endif
236
-
};
237
-
238
-
struct bcr_cache {
239
-
#ifdef CONFIG_CPU_BIG_ENDIAN
240
-
unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
241
-
#else
242
-
unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
243
343
#endif
244
344
};
245
345
+9
-10
arch/arc/include/asm/cache.h
+9
-10
arch/arc/include/asm/cache.h
···
9
9
#ifndef __ARC_ASM_CACHE_H
10
10
#define __ARC_ASM_CACHE_H
11
11
12
-
#include <asm/mmu.h> /* some of cache registers depend on MMU ver */
13
-
14
12
/* In case $$ not config, setup a dummy number for rest of kernel */
15
13
#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
16
14
#define L1_CACHE_SHIFT 6
···
34
36
#define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK))
35
37
#endif
36
38
39
+
/*
40
+
* ARC700 doesn't cache any access in top 256M.
41
+
* Ideal for wiring memory mapped peripherals as we don't need to do
42
+
* explicit uncached accesses (LD.di/ST.di) hence more portable drivers
43
+
*/
44
+
#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
45
+
37
46
#ifndef __ASSEMBLY__
38
47
39
48
/* Uncached access macros */
···
64
59
65
60
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
66
61
67
-
/*
68
-
* ARC700 doesn't cache any access in top 256M.
69
-
* Ideal for wiring memory mapped peripherals as we don't need to do
70
-
* explicit uncached accesses (LD.di/ST.di) hence more portable drivers
71
-
*/
72
-
#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
73
-
74
62
extern void arc_cache_init(void);
75
63
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
76
64
extern void __init read_decode_cache_bcr(void);
77
-
#endif
65
+
66
+
#endif /* !__ASSEMBLY__ */
78
67
79
68
#endif /* _ASM_CACHE_H */
+20
arch/arc/include/asm/irqflags.h
+20
arch/arc/include/asm/irqflags.h
···
19
19
20
20
#include <asm/arcregs.h>
21
21
22
+
/* status32 Reg bits related to Interrupt Handling */
23
+
#define STATUS_E1_BIT 1 /* Int 1 enable */
24
+
#define STATUS_E2_BIT 2 /* Int 2 enable */
25
+
#define STATUS_A1_BIT 3 /* Int 1 active */
26
+
#define STATUS_A2_BIT 4 /* Int 2 active */
27
+
28
+
#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
29
+
#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
30
+
#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
31
+
#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
32
+
33
+
/* Other Interrupt Handling related Aux regs */
34
+
#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
35
+
#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
36
+
#define AUX_IRQ_LV12 0x43 /* interrupt level register */
37
+
38
+
#define AUX_IENABLE 0x40c
39
+
#define AUX_ITRIGGER 0x40d
40
+
#define AUX_IPULSE 0x415
41
+
22
42
#ifndef __ASSEMBLY__
23
43
24
44
/******************************************************************
+36
arch/arc/include/asm/mmu.h
+36
arch/arc/include/asm/mmu.h
···
17
17
#define CONFIG_ARC_MMU_VER 3
18
18
#endif
19
19
20
+
/* MMU Management regs */
21
+
#define ARC_REG_MMU_BCR 0x06f
22
+
#define ARC_REG_TLBPD0 0x405
23
+
#define ARC_REG_TLBPD1 0x406
24
+
#define ARC_REG_TLBINDEX 0x407
25
+
#define ARC_REG_TLBCOMMAND 0x408
26
+
#define ARC_REG_PID 0x409
27
+
#define ARC_REG_SCRATCH_DATA0 0x418
28
+
29
+
/* Bits in MMU PID register */
30
+
#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
31
+
32
+
/* Error code if probe fails */
33
+
#define TLB_LKUP_ERR 0x80000000
34
+
35
+
/* TLB Commands */
36
+
#define TLBWrite 0x1
37
+
#define TLBRead 0x2
38
+
#define TLBGetIndex 0x3
39
+
#define TLBProbe 0x4
40
+
41
+
#if (CONFIG_ARC_MMU_VER >= 2)
42
+
#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
43
+
#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
44
+
#endif
45
+
20
46
#ifndef __ASSEMBLY__
21
47
22
48
typedef struct {
···
52
26
#endif
53
27
} mm_context_t;
54
28
29
+
#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
30
+
void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
31
+
#else
32
+
#define tlb_paranoid_check(a, b)
55
33
#endif
34
+
35
+
void arc_mmu_init(void);
36
+
extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
37
+
void __init read_decode_mmu_bcr(void);
38
+
39
+
#endif /* !__ASSEMBLY__ */
56
40
57
41
#endif
+6
arch/arc/include/asm/pgtable.h
+6
arch/arc/include/asm/pgtable.h
···
135
135
/* ioremap */
136
136
#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
137
137
138
+
/* Masks for actual TLB "PD"s */
139
+
#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
140
+
#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
141
+
_PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
142
+
_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
143
+
138
144
/**************************************************************************
139
145
* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
140
146
*
-1
arch/arc/include/asm/tlb-mmu1.h
-1
arch/arc/include/asm/tlb-mmu1.h
-26
arch/arc/include/asm/tlb.h
-26
arch/arc/include/asm/tlb.h
···
9
9
#ifndef _ASM_ARC_TLB_H
10
10
#define _ASM_ARC_TLB_H
11
11
12
-
#ifdef __KERNEL__
13
-
14
-
#include <asm/pgtable.h>
15
-
16
-
/* Masks for actual TLB "PD"s */
17
-
#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
18
-
#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
19
-
_PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
20
-
_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
21
-
22
-
#ifndef __ASSEMBLY__
23
-
24
12
#define tlb_flush(tlb) \
25
13
do { \
26
14
if (tlb->fullmm) \
···
43
55
44
56
#include <linux/pagemap.h>
45
57
#include <asm-generic/tlb.h>
46
-
47
-
#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
48
-
void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
49
-
#else
50
-
#define tlb_paranoid_check(a, b)
51
-
#endif
52
-
53
-
void arc_mmu_init(void);
54
-
extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
55
-
void __init read_decode_mmu_bcr(void);
56
-
57
-
#endif /* __ASSEMBLY__ */
58
-
59
-
#endif /* __KERNEL__ */
60
58
61
59
#endif /* _ASM_ARC_TLB_H */
+11
arch/arc/kernel/time.c
+11
arch/arc/kernel/time.c
···
44
44
#include <asm/clk.h>
45
45
#include <asm/mach_desc.h>
46
46
47
+
/* Timer related Aux registers */
48
+
#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
49
+
#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
50
+
#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
51
+
#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
52
+
#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
53
+
#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
54
+
55
+
#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
56
+
#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
57
+
47
58
#define ARC_TIMER_MAX 0xFFFFFFFF
48
59
49
60
/********** Clock Source Device *********/
+35
-4
arch/arc/mm/cache_arc700.c
+35
-4
arch/arc/mm/cache_arc700.c
···
73
73
#include <asm/cachectl.h>
74
74
#include <asm/setup.h>
75
75
76
+
/* Instruction cache related Auxiliary registers */
77
+
#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78
+
#define ARC_REG_IC_IVIC 0x10
79
+
#define ARC_REG_IC_CTRL 0x11
80
+
#define ARC_REG_IC_IVIL 0x19
81
+
#if (CONFIG_ARC_MMU_VER > 2)
82
+
#define ARC_REG_IC_PTAG 0x1E
83
+
#endif
84
+
85
+
/* Bit val in IC_CTRL */
86
+
#define IC_CTRL_CACHE_DISABLE 0x1
87
+
88
+
/* Data cache related Auxiliary registers */
89
+
#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90
+
#define ARC_REG_DC_IVDC 0x47
91
+
#define ARC_REG_DC_CTRL 0x48
92
+
#define ARC_REG_DC_IVDL 0x4A
93
+
#define ARC_REG_DC_FLSH 0x4B
94
+
#define ARC_REG_DC_FLDL 0x4C
95
+
#if (CONFIG_ARC_MMU_VER > 2)
96
+
#define ARC_REG_DC_PTAG 0x5C
97
+
#endif
98
+
99
+
/* Bit val in DC_CTRL */
100
+
#define DC_CTRL_INV_MODE_FLUSH 0x40
101
+
#define DC_CTRL_FLUSH_STATUS 0x100
102
+
76
103
char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
77
104
{
78
105
int n = 0;
···
131
104
*/
132
105
void __cpuinit read_decode_cache_bcr(void)
133
106
{
134
-
struct bcr_cache ibcr, dbcr;
135
107
struct cpuinfo_arc_cache *p_ic, *p_dc;
136
108
unsigned int cpu = smp_processor_id();
109
+
struct bcr_cache {
110
+
#ifdef CONFIG_CPU_BIG_ENDIAN
111
+
unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
112
+
#else
113
+
unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
114
+
#endif
115
+
} ibcr, dbcr;
137
116
138
117
p_ic = &cpuinfo_arc700[cpu].icache;
139
118
READ_BCR(ARC_REG_IC_BCR, ibcr);
···
169
136
*/
170
137
void __cpuinit arc_cache_init(void)
171
138
{
172
-
unsigned int temp;
173
139
unsigned int cpu = smp_processor_id();
174
140
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
175
141
struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
176
-
int way_pg_ratio = way_pg_ratio;
177
-
int dcache_does_alias;
142
+
unsigned int dcache_does_alias, temp;
178
143
char str[256];
179
144
180
145
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+1
arch/arc/mm/fault.c
+1
arch/arc/mm/fault.c
+20
-4
arch/arc/mm/tlb.c
+20
-4
arch/arc/mm/tlb.c
···
55
55
#include <asm/arcregs.h>
56
56
#include <asm/setup.h>
57
57
#include <asm/mmu_context.h>
58
-
#include <asm/tlb.h>
58
+
#include <asm/mmu.h>
59
59
60
60
/* Need for ARC MMU v2
61
61
*
···
96
96
* corner cases when TLBWrite was not executed at all because the corresp
97
97
* J-TLB entry got evicted/replaced.
98
98
*/
99
+
99
100
100
101
/* A copy of the ASID from the PID reg is kept in asid_cache */
101
102
int asid_cache = FIRST_ASID;
···
467
466
*/
468
467
void __cpuinit read_decode_mmu_bcr(void)
469
468
{
470
-
unsigned int tmp;
471
-
struct bcr_mmu_1_2 *mmu2; /* encoded MMU2 attr */
472
-
struct bcr_mmu_3 *mmu3; /* encoded MMU3 attr */
473
469
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
470
+
unsigned int tmp;
471
+
struct bcr_mmu_1_2 {
472
+
#ifdef CONFIG_CPU_BIG_ENDIAN
473
+
unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
474
+
#else
475
+
unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
476
+
#endif
477
+
} *mmu2;
478
+
479
+
struct bcr_mmu_3 {
480
+
#ifdef CONFIG_CPU_BIG_ENDIAN
481
+
unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
482
+
u_itlb:4, u_dtlb:4;
483
+
#else
484
+
unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
485
+
ways:4, ver:8;
486
+
#endif
487
+
} *mmu3;
474
488
475
489
tmp = read_aux_reg(ARC_REG_MMU_BCR);
476
490
mmu->ver = (tmp >> 24);