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ARM: dts: renesas: Fix pin controller node names

According to Devicetree Specification v0.2 and later, Section "Generic
Names Recommendation", the node name for a pin controller device node
should be "pinctrl".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be

Geert Uytterhoeven d9fd7ff5 63070d7c

+19 -19
+1 -1
arch/arm/boot/dts/emev2.dtsi
··· 195 195 clock-names = "sclk"; 196 196 }; 197 197 198 - pfc: pin-controller@e0140200 { 198 + pfc: pinctrl@e0140200 { 199 199 compatible = "renesas,pfc-emev2"; 200 200 reg = <0xe0140200 0x100>; 201 201 };
+1 -1
arch/arm/boot/dts/r7s72100.dtsi
··· 499 499 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 500 500 }; 501 501 502 - pinctrl: pin-controller@fcfe3000 { 502 + pinctrl: pinctrl@fcfe3000 { 503 503 compatible = "renesas,r7s72100-ports"; 504 504 505 505 reg = <0xfcfe3000 0x4230>;
+1 -1
arch/arm/boot/dts/r7s9210.dtsi
··· 489 489 interrupt-map-mask = <7 0>; 490 490 }; 491 491 492 - pinctrl: pin-controller@fcffe000 { 492 + pinctrl: pinctrl@fcffe000 { 493 493 compatible = "renesas,r7s9210-pinctrl"; 494 494 reg = <0xfcffe000 0x1000>; 495 495
+1 -1
arch/arm/boot/dts/r8a73a4.dtsi
··· 221 221 power-domains = <&pd_c4>; 222 222 }; 223 223 224 - pfc: pin-controller@e6050000 { 224 + pfc: pinctrl@e6050000 { 225 225 compatible = "renesas,pfc-r8a73a4"; 226 226 reg = <0 0xe6050000 0 0x9000>; 227 227 gpio-controller;
+1 -1
arch/arm/boot/dts/r8a7740.dtsi
··· 311 311 status = "disabled"; 312 312 }; 313 313 314 - pfc: pin-controller@e6050000 { 314 + pfc: pinctrl@e6050000 { 315 315 compatible = "renesas,pfc-r8a7740"; 316 316 reg = <0xe6050000 0x8000>, 317 317 <0xe605800c 0x20>;
+1 -1
arch/arm/boot/dts/r8a7742.dtsi
··· 338 338 resets = <&cpg 907>; 339 339 }; 340 340 341 - pfc: pin-controller@e6060000 { 341 + pfc: pinctrl@e6060000 { 342 342 compatible = "renesas,pfc-r8a7742"; 343 343 reg = <0 0xe6060000 0 0x250>; 344 344 };
+1 -1
arch/arm/boot/dts/r8a7743.dtsi
··· 265 265 resets = <&cpg 904>; 266 266 }; 267 267 268 - pfc: pin-controller@e6060000 { 268 + pfc: pinctrl@e6060000 { 269 269 compatible = "renesas,pfc-r8a7743"; 270 270 reg = <0 0xe6060000 0 0x250>; 271 271 };
+1 -1
arch/arm/boot/dts/r8a7744.dtsi
··· 265 265 resets = <&cpg 904>; 266 266 }; 267 267 268 - pfc: pin-controller@e6060000 { 268 + pfc: pinctrl@e6060000 { 269 269 compatible = "renesas,pfc-r8a7744"; 270 270 reg = <0 0xe6060000 0 0x250>; 271 271 };
+1 -1
arch/arm/boot/dts/r8a7745.dtsi
··· 230 230 resets = <&cpg 905>; 231 231 }; 232 232 233 - pfc: pin-controller@e6060000 { 233 + pfc: pinctrl@e6060000 { 234 234 compatible = "renesas,pfc-r8a7745"; 235 235 reg = <0 0xe6060000 0 0x11c>; 236 236 };
+1 -1
arch/arm/boot/dts/r8a77470.dtsi
··· 187 187 resets = <&cpg 907>; 188 188 }; 189 189 190 - pfc: pin-controller@e6060000 { 190 + pfc: pinctrl@e6060000 { 191 191 compatible = "renesas,pfc-r8a77470"; 192 192 reg = <0 0xe6060000 0 0x118>; 193 193 };
+1 -1
arch/arm/boot/dts/r8a7778.dtsi
··· 142 142 interrupt-controller; 143 143 }; 144 144 145 - pfc: pin-controller@fffc0000 { 145 + pfc: pinctrl@fffc0000 { 146 146 compatible = "renesas,pfc-r8a7778"; 147 147 reg = <0xfffc0000 0x118>; 148 148 };
+1 -1
arch/arm/boot/dts/r8a7779.dtsi
··· 321 321 status = "disabled"; 322 322 }; 323 323 324 - pfc: pin-controller@fffc0000 { 324 + pfc: pinctrl@fffc0000 { 325 325 compatible = "renesas,pfc-r8a7779"; 326 326 reg = <0xfffc0000 0x23c>; 327 327 };
+1 -1
arch/arm/boot/dts/r8a7790.dtsi
··· 363 363 resets = <&cpg 907>; 364 364 }; 365 365 366 - pfc: pin-controller@e6060000 { 366 + pfc: pinctrl@e6060000 { 367 367 compatible = "renesas,pfc-r8a7790"; 368 368 reg = <0 0xe6060000 0 0x250>; 369 369 };
+1 -1
arch/arm/boot/dts/r8a7791.dtsi
··· 286 286 resets = <&cpg 904>; 287 287 }; 288 288 289 - pfc: pin-controller@e6060000 { 289 + pfc: pinctrl@e6060000 { 290 290 compatible = "renesas,pfc-r8a7791"; 291 291 reg = <0 0xe6060000 0 0x250>; 292 292 };
+1 -1
arch/arm/boot/dts/r8a7792.dtsi
··· 296 296 resets = <&cpg 913>; 297 297 }; 298 298 299 - pfc: pin-controller@e6060000 { 299 + pfc: pinctrl@e6060000 { 300 300 compatible = "renesas,pfc-r8a7792"; 301 301 reg = <0 0xe6060000 0 0x144>; 302 302 };
+1 -1
arch/arm/boot/dts/r8a7793.dtsi
··· 271 271 resets = <&cpg 904>; 272 272 }; 273 273 274 - pfc: pin-controller@e6060000 { 274 + pfc: pinctrl@e6060000 { 275 275 compatible = "renesas,pfc-r8a7793"; 276 276 reg = <0 0xe6060000 0 0x250>; 277 277 };
+1 -1
arch/arm/boot/dts/r8a7794.dtsi
··· 238 238 resets = <&cpg 905>; 239 239 }; 240 240 241 - pfc: pin-controller@e6060000 { 241 + pfc: pinctrl@e6060000 { 242 242 compatible = "renesas,pfc-r8a7794"; 243 243 reg = <0 0xe6060000 0 0x11c>; 244 244 };
+1 -1
arch/arm/boot/dts/r9a06g032.dtsi
··· 165 165 status = "disabled"; 166 166 }; 167 167 168 - pinctrl: pin-controller@40067000 { 168 + pinctrl: pinctrl@40067000 { 169 169 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 170 170 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 171 171 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
+1 -1
arch/arm/boot/dts/sh73a0.dtsi
··· 448 448 status = "disabled"; 449 449 }; 450 450 451 - pfc: pin-controller@e6050000 { 451 + pfc: pinctrl@e6050000 { 452 452 compatible = "renesas,pfc-sh73a0"; 453 453 reg = <0xe6050000 0x8000>, 454 454 <0xe605801c 0x1c>;