Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"

As it says on the tin, add a DT for this board. It's been sitting on my
desk for a while, so may as well have it upstream...

The DT is only partially complete, as it needs the fabric content added.
Unfortunately, I don't have a reference design in RTL or SmartDesign
for it and therefore don't know what that fabric content is.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

+187
+1
Documentation/devicetree/bindings/riscv/microchip.yaml
··· 27 27 28 28 - items: 29 29 - enum: 30 + - aldec,tysom-m-mpfs250t-rev2 30 31 - aries,m100pfsevp 31 32 - microchip,mpfs-sev-kit 32 33 - sundance,polarberry
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
··· 69 69 description: Annapurna Labs 70 70 "^alcatel,.*": 71 71 description: Alcatel 72 + "^aldec,.*": 73 + description: Aldec, Inc. 72 74 "^alfa-network,.*": 73 75 description: ALFA Network Inc. 74 76 "^allegro,.*":
+1
arch/riscv/boot/dts/microchip/Makefile
··· 3 3 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb 4 4 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb 5 5 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb 6 + dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb 6 7 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
+18
arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* Copyright (c) 2022 Microchip Technology Inc */ 3 + 4 + // #include "dt-bindings/mailbox/miv-ihc.h" 5 + 6 + / { 7 + fabric_clk3: fabric-clk3 { 8 + compatible = "fixed-clock"; 9 + #clock-cells = <0>; 10 + clock-frequency = <62500000>; 11 + }; 12 + 13 + fabric_clk1: fabric-clk1 { 14 + compatible = "fixed-clock"; 15 + #clock-cells = <0>; 16 + clock-frequency = <125000000>; 17 + }; 18 + };
+165
arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Original all-in-one devicetree: 4 + * Copyright (C) 2020-2022 - Aldec 5 + * Rewritten to use includes: 6 + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "mpfs.dtsi" 12 + #include "mpfs-tysom-m-fabric.dtsi" 13 + 14 + /* Clock frequency (in Hz) of the rtcclk */ 15 + #define MTIMER_FREQ 1000000 16 + 17 + / { 18 + model = "Aldec TySOM-M-MPFS250T-REV2"; 19 + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; 20 + 21 + aliases { 22 + ethernet0 = &mac0; 23 + ethernet1 = &mac1; 24 + serial0 = &mmuart0; 25 + serial1 = &mmuart1; 26 + serial2 = &mmuart2; 27 + serial3 = &mmuart3; 28 + serial4 = &mmuart4; 29 + gpio0 = &gpio0; 30 + gpio1 = &gpio2; 31 + }; 32 + 33 + chosen { 34 + stdout-path = "serial1:115200n8"; 35 + }; 36 + 37 + cpus { 38 + timebase-frequency = <MTIMER_FREQ>; 39 + }; 40 + 41 + ddrc_cache_lo: memory@80000000 { 42 + device_type = "memory"; 43 + reg = <0x0 0x80000000 0x0 0x30000000>; 44 + status = "okay"; 45 + }; 46 + 47 + ddrc_cache_hi: memory@1000000000 { 48 + device_type = "memory"; 49 + reg = <0x10 0x00000000 0x0 0x40000000>; 50 + status = "okay"; 51 + }; 52 + 53 + leds { 54 + compatible = "gpio-leds"; 55 + status = "okay"; 56 + 57 + led0 { 58 + gpios = <&gpio1 23 1>; 59 + default-state = "on"; 60 + linux,default-trigger = "heartbeat"; 61 + }; 62 + }; 63 + }; 64 + 65 + &i2c0 { 66 + status = "okay"; 67 + }; 68 + 69 + &i2c1 { 70 + status = "okay"; 71 + hwmon: hwmon@45 { 72 + status = "okay"; 73 + compatible = "ti,ina219"; 74 + reg = <0x45>; 75 + shunt-resistor = <2000>; 76 + }; 77 + }; 78 + 79 + &gpio1 { 80 + interrupts = <27>, <28>, <29>, <30>, 81 + <31>, <32>, <33>, <47>, 82 + <35>, <36>, <37>, <38>, 83 + <39>, <40>, <41>, <42>, 84 + <43>, <44>, <45>, <46>, 85 + <47>, <48>, <49>, <50>; 86 + status = "okay"; 87 + }; 88 + 89 + &mac0 { 90 + status = "okay"; 91 + phy-mode = "gmii"; 92 + phy-handle = <&phy0>; 93 + 94 + }; 95 + 96 + &mac1 { 97 + status = "okay"; 98 + phy-mode = "gmii"; 99 + phy-handle = <&phy1>; 100 + phy1: ethernet-phy@1 { 101 + reg = <1>; 102 + }; 103 + phy0: ethernet-phy@0 { 104 + reg = <0>; 105 + }; 106 + }; 107 + 108 + &mbox { 109 + status = "okay"; 110 + }; 111 + 112 + &mmc { 113 + max-frequency = <200000000>; 114 + cap-mmc-highspeed; 115 + cap-sd-highspeed; 116 + no-1-8-v; 117 + disable-wp; 118 + status = "okay"; 119 + }; 120 + 121 + &mmuart1 { 122 + status = "okay"; 123 + }; 124 + 125 + &mmuart2 { 126 + status = "okay"; 127 + }; 128 + 129 + &mmuart3 { 130 + status = "okay"; 131 + }; 132 + 133 + &mmuart4 { 134 + status = "okay"; 135 + }; 136 + 137 + &refclk { 138 + clock-frequency = <125000000>; 139 + }; 140 + 141 + &rtc { 142 + status = "okay"; 143 + }; 144 + 145 + &spi0 { 146 + status = "okay"; 147 + }; 148 + 149 + &spi1 { 150 + status = "okay"; 151 + flash@0 { 152 + compatible = "micron,n25q128a11", "jedec,spi-nor"; 153 + reg = <0x0>; 154 + spi-max-frequency = <10000000>; 155 + }; 156 + }; 157 + 158 + &syscontroller { 159 + status = "okay"; 160 + }; 161 + 162 + &usb { 163 + status = "okay"; 164 + dr_mode = "host"; 165 + };