tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

ARM: spear: make clock driver independent of headers

Device drivers should not access MMIO registers through hardcoded
platform specific address constants. Instead, we can pass the
MMIO token to the spear clock driver in the initialization routine
to contain that knowledge in the platform code itself.

Ideally, the clock driver would use of_iomap() or similar to
get the address, and that can be used later, but for now, this
is the minimal change.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Arnd Bergmann d9909ebe 2b9c613c

+143 -142
+7 -6
arch/arm/mach-spear/generic.h
··· 29 29 bool dw_dma_filter(struct dma_chan *chan, void *slave); 30 30 31 31 void __init spear_setup_of_timer(void); 32 - void __init spear3xx_clk_init(void); 32 + void __init spear3xx_clk_init(void __iomem *misc_base, 33 + void __iomem *soc_config_base); 33 34 void __init spear3xx_map_io(void); 34 35 void __init spear3xx_dt_init_irq(void); 35 - void __init spear6xx_clk_init(void); 36 + void __init spear6xx_clk_init(void __iomem *misc_base); 36 37 void __init spear13xx_map_io(void); 37 38 void __init spear13xx_l2x0_init(void); 38 39 ··· 45 44 extern struct smp_operations spear13xx_smp_ops; 46 45 47 46 #ifdef CONFIG_MACH_SPEAR1310 48 - void __init spear1310_clk_init(void); 47 + void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base); 49 48 #else 50 - static inline void spear1310_clk_init(void) {} 49 + static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {} 51 50 #endif 52 51 53 52 #ifdef CONFIG_MACH_SPEAR1340 54 - void __init spear1340_clk_init(void); 53 + void __init spear1340_clk_init(void __iomem *misc_base); 55 54 #else 56 - static inline void spear1340_clk_init(void) {} 55 + static inline void spear1340_clk_init(void __iomem *misc_base) {} 57 56 #endif 58 57 59 58 #endif /* __MACH_GENERIC_H */
+1 -1
arch/arm/mach-spear/include/mach/misc_regs.h
··· 16 16 17 17 #include <mach/spear.h> 18 18 19 - #define MISC_BASE IOMEM(VA_SPEAR_ICM3_MISC_REG_BASE) 19 + #define MISC_BASE (VA_SPEAR_ICM3_MISC_REG_BASE) 20 20 #define DMA_CHN_CFG (MISC_BASE + 0x0A0) 21 21 22 22 #endif /* __MACH_MISC_REGS_H */
+11 -17
arch/arm/mach-spear/include/mach/spear.h
··· 19 19 20 20 /* ICM1 - Low speed connection */ 21 21 #define SPEAR_ICM1_2_BASE UL(0xD0000000) 22 - #define VA_SPEAR_ICM1_2_BASE UL(0xFD000000) 22 + #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000) 23 23 #define SPEAR_ICM1_UART_BASE UL(0xD0000000) 24 - #define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE) 24 + #define VA_SPEAR_ICM1_UART_BASE (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE) 25 25 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 26 26 27 27 /* ML-1, 2 - Multi Layer CPU Subsystem */ 28 28 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000) 29 - #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 29 + #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000) 30 30 31 31 /* ICM3 - Basic Subsystem */ 32 32 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) 33 - #define VA_SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000) 33 + #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000) 34 34 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000) 35 35 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 36 - #define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE) 36 + #define VA_SPEAR_ICM3_SYS_CTRL_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE) 37 37 #define SPEAR_ICM3_MISC_REG_BASE UL(0xFCA80000) 38 - #define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE) 38 + #define VA_SPEAR_ICM3_MISC_REG_BASE (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE) 39 39 40 40 /* Debug uart for linux, will be used for debug and uncompress messages */ 41 41 #define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE ··· 44 44 /* Sysctl base for spear platform */ 45 45 #define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE 46 46 #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR_ICM3_SYS_CTRL_BASE 47 + #endif /* SPEAR3xx || SPEAR6XX */ 47 48 48 49 /* SPEAr320 Macros */ 49 50 #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) 50 - #define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) 51 - #define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) 52 - #define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) 53 - #define SPEAR320_UARTX_PCLK_MASK 0x1 54 - #define SPEAR320_UART2_PCLK_SHIFT 8 55 - #define SPEAR320_UART3_PCLK_SHIFT 9 56 - #define SPEAR320_UART4_PCLK_SHIFT 10 57 - #define SPEAR320_UART5_PCLK_SHIFT 11 58 - #define SPEAR320_UART6_PCLK_SHIFT 12 59 - #define SPEAR320_RS485_PCLK_SHIFT 13 60 - #endif /* SPEAR3xx || SPEAR6XX */ 51 + #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000) 61 52 62 53 #ifdef CONFIG_ARCH_SPEAR13XX 63 54 ··· 69 78 70 79 #define A9SM_AND_MPMC_BASE UL(0xEC000000) 71 80 #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) 81 + 82 + #define SPEAR1310_RAS_BASE UL(0xD8400000) 83 + #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) 72 84 73 85 /* A9SM peripheral offsets */ 74 86 #define A9SM_PERIP_BASE UL(0xEC800000)
-2
arch/arm/mach-spear/spear1310.c
··· 30 30 31 31 #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) 32 32 #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) 33 - #define SPEAR1310_RAS_BASE UL(0xD8400000) 34 - #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) 35 33 36 34 static struct arasan_cf_pdata cf_pdata = { 37 35 .cf_if_clk = CF_IF_CLK_166M,
+2 -2
arch/arm/mach-spear/spear13xx.c
··· 146 146 static void __init spear13xx_clk_init(void) 147 147 { 148 148 if (of_machine_is_compatible("st,spear1310")) 149 - spear1310_clk_init(); 149 + spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE); 150 150 else if (of_machine_is_compatible("st,spear1340")) 151 - spear1340_clk_init(); 151 + spear1340_clk_init(VA_MISC_BASE); 152 152 else 153 153 pr_err("%s: Unknown machine\n", __func__); 154 154 }
+1 -1
arch/arm/mach-spear/spear320.c
··· 254 254 255 255 struct map_desc spear320_io_desc[] __initdata = { 256 256 { 257 - .virtual = VA_SPEAR320_SOC_CONFIG_BASE, 257 + .virtual = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE, 258 258 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), 259 259 .length = SZ_16M, 260 260 .type = MT_DEVICE
+4 -3
arch/arm/mach-spear/spear3xx.c
··· 21 21 #include "pl080.h" 22 22 #include "generic.h" 23 23 #include <mach/spear.h> 24 + #include <mach/misc_regs.h> 24 25 25 26 /* ssp device registration */ 26 27 struct pl022_ssp_controller pl022_plat_data = { ··· 68 67 */ 69 68 struct map_desc spear3xx_io_desc[] __initdata = { 70 69 { 71 - .virtual = VA_SPEAR_ICM1_2_BASE, 70 + .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, 72 71 .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), 73 72 .length = SZ_16M, 74 73 .type = MT_DEVICE 75 74 }, { 76 - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, 75 + .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, 77 76 .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), 78 77 .length = SZ_16M, 79 78 .type = MT_DEVICE ··· 91 90 char pclk_name[] = "pll3_clk"; 92 91 struct clk *gpt_clk, *pclk; 93 92 94 - spear3xx_clk_init(); 93 + spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE); 95 94 96 95 /* get the system timer clock */ 97 96 gpt_clk = clk_get_sys("gpt0", NULL);
+5 -4
arch/arm/mach-spear/spear6xx.c
··· 27 27 #include "pl080.h" 28 28 #include "generic.h" 29 29 #include <mach/spear.h> 30 + #include <mach/misc_regs.h> 30 31 31 32 /* dmac device registration */ 32 33 static struct pl08x_channel_data spear600_dma_info[] = { ··· 351 350 */ 352 351 struct map_desc spear6xx_io_desc[] __initdata = { 353 352 { 354 - .virtual = VA_SPEAR6XX_ML_CPU_BASE, 353 + .virtual = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE, 355 354 .pfn = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE), 356 355 .length = 2 * SZ_16M, 357 356 .type = MT_DEVICE 358 357 }, { 359 - .virtual = VA_SPEAR_ICM1_2_BASE, 358 + .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, 360 359 .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), 361 360 .length = SZ_16M, 362 361 .type = MT_DEVICE 363 362 }, { 364 - .virtual = VA_SPEAR_ICM3_SMI_CTRL_BASE, 363 + .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, 365 364 .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), 366 365 .length = SZ_16M, 367 366 .type = MT_DEVICE ··· 379 378 char pclk_name[] = "pll3_clk"; 380 379 struct clk *gpt_clk, *pclk; 381 380 382 - spear6xx_clk_init(); 381 + spear6xx_clk_init(MISC_BASE); 383 382 384 383 /* get the system timer clock */ 385 384 gpt_clk = clk_get_sys("gpt0", NULL);
+31 -33
drivers/clk/spear/spear1310_clock.c
··· 17 17 #include <linux/io.h> 18 18 #include <linux/of_platform.h> 19 19 #include <linux/spinlock_types.h> 20 - #include <mach/spear.h> 21 20 #include "clk.h" 22 21 23 - #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) 24 22 /* PLL related registers and bit values */ 25 - #define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210) 23 + #define SPEAR1310_PLL_CFG (misc_base + 0x210) 26 24 /* PLL_CFG bit values */ 27 25 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 28 26 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 ··· 33 35 #define SPEAR1310_PLL2_CLK_SHIFT 22 34 36 #define SPEAR1310_PLL1_CLK_SHIFT 20 35 37 36 - #define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214) 37 - #define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218) 38 - #define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220) 39 - #define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224) 40 - #define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C) 41 - #define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230) 42 - #define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238) 43 - #define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C) 44 - #define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 38 + #define SPEAR1310_PLL1_CTR (misc_base + 0x214) 39 + #define SPEAR1310_PLL1_FRQ (misc_base + 0x218) 40 + #define SPEAR1310_PLL2_CTR (misc_base + 0x220) 41 + #define SPEAR1310_PLL2_FRQ (misc_base + 0x224) 42 + #define SPEAR1310_PLL3_CTR (misc_base + 0x22C) 43 + #define SPEAR1310_PLL3_FRQ (misc_base + 0x230) 44 + #define SPEAR1310_PLL4_CTR (misc_base + 0x238) 45 + #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C) 46 + #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244) 45 47 /* PERIP_CLK_CFG bit values */ 46 48 #define SPEAR1310_GPT_OSC24_VAL 0 47 49 #define SPEAR1310_GPT_APB_VAL 1 ··· 63 65 #define SPEAR1310_C3_CLK_MASK 1 64 66 #define SPEAR1310_C3_CLK_SHIFT 1 65 67 66 - #define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 68 + #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248) 67 69 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 68 70 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 69 71 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 ··· 71 73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 72 74 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 73 75 74 - #define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 76 + #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C) 75 77 /* I2S_CLK_CFG register mask */ 76 78 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 77 79 #define SPEAR1310_I2S_SCLK_X_SHIFT 27 ··· 89 91 #define SPEAR1310_I2S_SRC_CLK_MASK 2 90 92 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 91 93 92 - #define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 93 - #define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254) 94 - #define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258) 95 - #define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C) 96 - #define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260) 97 - #define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264) 98 - #define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268) 99 - #define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270) 100 - #define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280) 101 - #define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288) 102 - #define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290) 103 - #define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298) 94 + #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250) 95 + #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254) 96 + #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258) 97 + #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C) 98 + #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260) 99 + #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264) 100 + #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268) 101 + #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270) 102 + #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280) 103 + #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288) 104 + #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290) 105 + #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298) 104 106 /* Check Fractional synthesizer reg masks */ 105 107 106 - #define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300) 108 + #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300) 107 109 /* PERIP1_CLK_ENB register masks */ 108 110 #define SPEAR1310_RTC_CLK_ENB 31 109 111 #define SPEAR1310_ADC_CLK_ENB 30 ··· 136 138 #define SPEAR1310_SYSROM_CLK_ENB 1 137 139 #define SPEAR1310_BUS_CLK_ENB 0 138 140 139 - #define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304) 141 + #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304) 140 142 /* PERIP2_CLK_ENB register masks */ 141 143 #define SPEAR1310_THSENS_CLK_ENB 8 142 144 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 ··· 148 150 #define SPEAR1310_DDR_CORE_CLK_ENB 1 149 151 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 150 152 151 - #define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310) 153 + #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310) 152 154 /* RAS_CLK_ENB register masks */ 153 155 #define SPEAR1310_SYNT3_CLK_ENB 17 154 156 #define SPEAR1310_SYNT2_CLK_ENB 16 ··· 170 172 #define SPEAR1310_ACLK_CLK_ENB 0 171 173 172 174 /* RAS Area Control Register */ 173 - #define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000) 175 + #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000) 174 176 #define SPEAR1310_SSP1_CLK_MASK 3 175 177 #define SPEAR1310_SSP1_CLK_SHIFT 26 176 178 #define SPEAR1310_TDM_CLK_MASK 1 ··· 195 197 #define SPEAR1310_PCI_CLK_MASK 1 196 198 #define SPEAR1310_PCI_CLK_SHIFT 0 197 199 198 - #define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004) 200 + #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004) 199 201 #define SPEAR1310_PHY_CLK_MASK 0x3 200 202 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 201 203 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 202 204 203 - #define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148) 205 + #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148) 204 206 #define SPEAR1310_CAN1_CLK_ENB 25 205 207 #define SPEAR1310_CAN0_CLK_ENB 24 206 208 #define SPEAR1310_GPT64_CLK_ENB 23 ··· 383 385 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 384 386 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 385 387 386 - void __init spear1310_clk_init(void) 388 + void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) 387 389 { 388 390 struct clk *clk, *clk1; 389 391
+31 -32
drivers/clk/spear/spear1340_clock.c
··· 17 17 #include <linux/io.h> 18 18 #include <linux/of_platform.h> 19 19 #include <linux/spinlock_types.h> 20 - #include <mach/spear.h> 21 20 #include "clk.h" 22 21 23 22 /* Clock Configuration Registers */ 24 - #define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200) 23 + #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200) 25 24 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27 26 25 #define SPEAR1340_HCLK_SRC_SEL_MASK 1 27 26 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23 28 27 #define SPEAR1340_SCLK_SRC_SEL_MASK 3 29 28 30 29 /* PLL related registers and bit values */ 31 - #define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210) 30 + #define SPEAR1340_PLL_CFG (misc_base + 0x210) 32 31 /* PLL_CFG bit values */ 33 32 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1 34 33 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31 ··· 39 40 #define SPEAR1340_PLL2_CLK_SHIFT 22 40 41 #define SPEAR1340_PLL1_CLK_SHIFT 20 41 42 42 - #define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214) 43 - #define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218) 44 - #define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220) 45 - #define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224) 46 - #define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C) 47 - #define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230) 48 - #define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238) 49 - #define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C) 50 - #define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 43 + #define SPEAR1340_PLL1_CTR (misc_base + 0x214) 44 + #define SPEAR1340_PLL1_FRQ (misc_base + 0x218) 45 + #define SPEAR1340_PLL2_CTR (misc_base + 0x220) 46 + #define SPEAR1340_PLL2_FRQ (misc_base + 0x224) 47 + #define SPEAR1340_PLL3_CTR (misc_base + 0x22C) 48 + #define SPEAR1340_PLL3_FRQ (misc_base + 0x230) 49 + #define SPEAR1340_PLL4_CTR (misc_base + 0x238) 50 + #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C) 51 + #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244) 51 52 /* PERIP_CLK_CFG bit values */ 52 53 #define SPEAR1340_SPDIF_CLK_MASK 1 53 54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15 ··· 65 66 #define SPEAR1340_C3_CLK_MASK 1 66 67 #define SPEAR1340_C3_CLK_SHIFT 1 67 68 68 - #define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 69 + #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248) 69 70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1 70 71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2 71 72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2 72 73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0 73 74 74 - #define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 75 + #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C) 75 76 /* I2S_CLK_CFG register mask */ 76 77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F 77 78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27 ··· 89 90 #define SPEAR1340_I2S_SRC_CLK_MASK 2 90 91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0 91 92 92 - #define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 93 - #define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254) 94 - #define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258) 95 - #define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C) 96 - #define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260) 97 - #define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264) 98 - #define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270) 99 - #define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274) 100 - #define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C) 101 - #define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284) 102 - #define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C) 103 - #define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294) 104 - #define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C) 105 - #define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304) 106 - #define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C) 93 + #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250) 94 + #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254) 95 + #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258) 96 + #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C) 97 + #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260) 98 + #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264) 99 + #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270) 100 + #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274) 101 + #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C) 102 + #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284) 103 + #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C) 104 + #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294) 105 + #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C) 106 + #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304) 107 + #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C) 107 108 #define SPEAR1340_RTC_CLK_ENB 31 108 109 #define SPEAR1340_ADC_CLK_ENB 30 109 110 #define SPEAR1340_C3_CLK_ENB 29 ··· 132 133 #define SPEAR1340_SYSROM_CLK_ENB 1 133 134 #define SPEAR1340_BUS_CLK_ENB 0 134 135 135 - #define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310) 136 + #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310) 136 137 #define SPEAR1340_THSENS_CLK_ENB 8 137 138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7 138 139 #define SPEAR1340_ACP_CLK_ENB 6 ··· 143 144 #define SPEAR1340_DDR_CORE_CLK_ENB 1 144 145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0 145 146 146 - #define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314) 147 + #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314) 147 148 #define SPEAR1340_PLGPIO_CLK_ENB 18 148 149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16 149 150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15 ··· 440 441 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", 441 442 "pll2_clk", }; 442 443 443 - void __init spear1340_clk_init(void) 444 + void __init spear1340_clk_init(void __iomem *misc_base) 444 445 { 445 446 struct clk *clk, *clk1; 446 447
+35 -25
drivers/clk/spear/spear3xx_clock.c
··· 15 15 #include <linux/io.h> 16 16 #include <linux/of_platform.h> 17 17 #include <linux/spinlock_types.h> 18 - #include <mach/misc_regs.h> 19 18 #include "clk.h" 20 19 21 20 static DEFINE_SPINLOCK(_lock); 22 21 23 - #define PLL1_CTR (MISC_BASE + 0x008) 24 - #define PLL1_FRQ (MISC_BASE + 0x00C) 25 - #define PLL2_CTR (MISC_BASE + 0x014) 26 - #define PLL2_FRQ (MISC_BASE + 0x018) 27 - #define PLL_CLK_CFG (MISC_BASE + 0x020) 22 + #define PLL1_CTR (misc_base + 0x008) 23 + #define PLL1_FRQ (misc_base + 0x00C) 24 + #define PLL2_CTR (misc_base + 0x014) 25 + #define PLL2_FRQ (misc_base + 0x018) 26 + #define PLL_CLK_CFG (misc_base + 0x020) 28 27 /* PLL_CLK_CFG register masks */ 29 28 #define MCTR_CLK_SHIFT 28 30 29 #define MCTR_CLK_MASK 3 31 30 32 - #define CORE_CLK_CFG (MISC_BASE + 0x024) 31 + #define CORE_CLK_CFG (misc_base + 0x024) 33 32 /* CORE CLK CFG register masks */ 34 33 #define GEN_SYNTH2_3_CLK_SHIFT 18 35 34 #define GEN_SYNTH2_3_CLK_MASK 1 ··· 38 39 #define PCLK_RATIO_SHIFT 8 39 40 #define PCLK_RATIO_MASK 2 40 41 41 - #define PERIP_CLK_CFG (MISC_BASE + 0x028) 42 + #define PERIP_CLK_CFG (misc_base + 0x028) 42 43 /* PERIP_CLK_CFG register masks */ 43 44 #define UART_CLK_SHIFT 4 44 45 #define UART_CLK_MASK 1 ··· 49 50 #define GPT2_CLK_SHIFT 12 50 51 #define GPT_CLK_MASK 1 51 52 52 - #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 53 + #define PERIP1_CLK_ENB (misc_base + 0x02C) 53 54 /* PERIP1_CLK_ENB register masks */ 54 55 #define UART_CLK_ENB 3 55 56 #define SSP_CLK_ENB 5 ··· 68 69 #define USBH_CLK_ENB 25 69 70 #define C3_CLK_ENB 31 70 71 71 - #define RAS_CLK_ENB (MISC_BASE + 0x034) 72 + #define RAS_CLK_ENB (misc_base + 0x034) 72 73 #define RAS_AHB_CLK_ENB 0 73 74 #define RAS_PLL1_CLK_ENB 1 74 75 #define RAS_APB_CLK_ENB 2 ··· 81 82 #define RAS_SYNT2_CLK_ENB 10 82 83 #define RAS_SYNT3_CLK_ENB 11 83 84 84 - #define PRSC0_CLK_CFG (MISC_BASE + 0x044) 85 - #define PRSC1_CLK_CFG (MISC_BASE + 0x048) 86 - #define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 87 - #define AMEM_CLK_CFG (MISC_BASE + 0x050) 85 + #define PRSC0_CLK_CFG (misc_base + 0x044) 86 + #define PRSC1_CLK_CFG (misc_base + 0x048) 87 + #define PRSC2_CLK_CFG (misc_base + 0x04C) 88 + #define AMEM_CLK_CFG (misc_base + 0x050) 88 89 #define AMEM_CLK_ENB 0 89 90 90 - #define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 91 - #define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 92 - #define UART_CLK_SYNT (MISC_BASE + 0x064) 93 - #define GMAC_CLK_SYNT (MISC_BASE + 0x068) 94 - #define GEN0_CLK_SYNT (MISC_BASE + 0x06C) 95 - #define GEN1_CLK_SYNT (MISC_BASE + 0x070) 96 - #define GEN2_CLK_SYNT (MISC_BASE + 0x074) 97 - #define GEN3_CLK_SYNT (MISC_BASE + 0x078) 91 + #define CLCD_CLK_SYNT (misc_base + 0x05C) 92 + #define FIRDA_CLK_SYNT (misc_base + 0x060) 93 + #define UART_CLK_SYNT (misc_base + 0x064) 94 + #define GMAC_CLK_SYNT (misc_base + 0x068) 95 + #define GEN0_CLK_SYNT (misc_base + 0x06C) 96 + #define GEN1_CLK_SYNT (misc_base + 0x070) 97 + #define GEN2_CLK_SYNT (misc_base + 0x074) 98 + #define GEN3_CLK_SYNT (misc_base + 0x078) 98 99 99 100 /* pll rate configuration table, in ascending order of rates */ 100 101 static struct pll_rate_tbl pll_rtbl[] = { ··· 210 211 211 212 /* array of all spear 320 clock lookups */ 212 213 #ifdef CONFIG_MACH_SPEAR320 214 + 215 + #define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) 216 + #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) 217 + 218 + #define SPEAR320_UARTX_PCLK_MASK 0x1 219 + #define SPEAR320_UART2_PCLK_SHIFT 8 220 + #define SPEAR320_UART3_PCLK_SHIFT 9 221 + #define SPEAR320_UART4_PCLK_SHIFT 10 222 + #define SPEAR320_UART5_PCLK_SHIFT 11 223 + #define SPEAR320_UART6_PCLK_SHIFT 12 224 + #define SPEAR320_RS485_PCLK_SHIFT 13 213 225 #define SMII_PCLK_SHIFT 18 214 226 #define SMII_PCLK_MASK 2 215 227 #define SMII_PCLK_VAL_PAD 0x0 ··· 245 235 "ras_syn0_gclk", }; 246 236 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; 247 237 248 - static void __init spear320_clk_init(void) 238 + static void __init spear320_clk_init(void __iomem *soc_config_base) 249 239 { 250 240 struct clk *clk; 251 241 ··· 372 362 static inline void spear320_clk_init(void) { } 373 363 #endif 374 364 375 - void __init spear3xx_clk_init(void) 365 + void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) 376 366 { 377 367 struct clk *clk, *clk1; 378 368 ··· 644 634 else if (of_machine_is_compatible("st,spear310")) 645 635 spear310_clk_init(); 646 636 else if (of_machine_is_compatible("st,spear320")) 647 - spear320_clk_init(); 637 + spear320_clk_init(soc_config_base); 648 638 }
+15 -16
drivers/clk/spear/spear6xx_clock.c
··· 13 13 #include <linux/clkdev.h> 14 14 #include <linux/io.h> 15 15 #include <linux/spinlock_types.h> 16 - #include <mach/misc_regs.h> 17 16 #include "clk.h" 18 17 19 18 static DEFINE_SPINLOCK(_lock); 20 19 21 - #define PLL1_CTR (MISC_BASE + 0x008) 22 - #define PLL1_FRQ (MISC_BASE + 0x00C) 23 - #define PLL2_CTR (MISC_BASE + 0x014) 24 - #define PLL2_FRQ (MISC_BASE + 0x018) 25 - #define PLL_CLK_CFG (MISC_BASE + 0x020) 20 + #define PLL1_CTR (misc_base + 0x008) 21 + #define PLL1_FRQ (misc_base + 0x00C) 22 + #define PLL2_CTR (misc_base + 0x014) 23 + #define PLL2_FRQ (misc_base + 0x018) 24 + #define PLL_CLK_CFG (misc_base + 0x020) 26 25 /* PLL_CLK_CFG register masks */ 27 26 #define MCTR_CLK_SHIFT 28 28 27 #define MCTR_CLK_MASK 3 29 28 30 - #define CORE_CLK_CFG (MISC_BASE + 0x024) 29 + #define CORE_CLK_CFG (misc_base + 0x024) 31 30 /* CORE CLK CFG register masks */ 32 31 #define HCLK_RATIO_SHIFT 10 33 32 #define HCLK_RATIO_MASK 2 34 33 #define PCLK_RATIO_SHIFT 8 35 34 #define PCLK_RATIO_MASK 2 36 35 37 - #define PERIP_CLK_CFG (MISC_BASE + 0x028) 36 + #define PERIP_CLK_CFG (misc_base + 0x028) 38 37 /* PERIP_CLK_CFG register masks */ 39 38 #define CLCD_CLK_SHIFT 2 40 39 #define CLCD_CLK_MASK 2 ··· 47 48 #define GPT3_CLK_SHIFT 12 48 49 #define GPT_CLK_MASK 1 49 50 50 - #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 51 + #define PERIP1_CLK_ENB (misc_base + 0x02C) 51 52 /* PERIP1_CLK_ENB register masks */ 52 53 #define UART0_CLK_ENB 3 53 54 #define UART1_CLK_ENB 4 ··· 73 74 #define USBH0_CLK_ENB 25 74 75 #define USBH1_CLK_ENB 26 75 76 76 - #define PRSC0_CLK_CFG (MISC_BASE + 0x044) 77 - #define PRSC1_CLK_CFG (MISC_BASE + 0x048) 78 - #define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 77 + #define PRSC0_CLK_CFG (misc_base + 0x044) 78 + #define PRSC1_CLK_CFG (misc_base + 0x048) 79 + #define PRSC2_CLK_CFG (misc_base + 0x04C) 79 80 80 - #define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 81 - #define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 82 - #define UART_CLK_SYNT (MISC_BASE + 0x064) 81 + #define CLCD_CLK_SYNT (misc_base + 0x05C) 82 + #define FIRDA_CLK_SYNT (misc_base + 0x060) 83 + #define UART_CLK_SYNT (misc_base + 0x064) 83 84 84 85 /* vco rate configuration table, in ascending order of rates */ 85 86 static struct pll_rate_tbl pll_rtbl[] = { ··· 114 115 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 115 116 }; 116 117 117 - void __init spear6xx_clk_init(void) 118 + void __init spear6xx_clk_init(void __iomem *misc_base) 118 119 { 119 120 struct clk *clk, *clk1; 120 121