tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: imx6: add DT for aristainetos2 board
This patch adds support for the imx6dl based aristainetos2 board
with following configuration:
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
MReset cause: POR
MBoard: aristaitenos2
DRAM: 1 GiB
NAND: 1024 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lb07wv8 (800x480)
As this board can be used with 2 different display types, the
differences between them are extracted into 2 DTS files, and
the common settings are collected in a common file.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
authored by
Heiko Schocher
and committed by
Shawn Guo
d94a3d3e
f4b5939d
+891
+2
arch/arm/boot/dts/Makefile
+2
arch/arm/boot/dts/Makefile
+159
arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
+159
arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
···
1
+
/*
2
+
* support for the imx6 based aristainetos2 board
3
+
*
4
+
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
5
+
*
6
+
* This file is dual-licensed: you can use it either under the terms
7
+
* of the GPL or the X11 license, at your option. Note that this dual
8
+
* licensing only applies to this file, and not this project as a
9
+
* whole.
10
+
*
11
+
* a) This file is free software; you can redistribute it and/or
12
+
* modify it under the terms of the GNU General Public License
13
+
* version 2 as published by the Free Software Foundation.
14
+
*
15
+
* This file is distributed in the hope that it will be useful
16
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
17
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18
+
* GNU General Public License for more details.
19
+
*
20
+
* Or, alternatively
21
+
*
22
+
* b) Permission is hereby granted, free of charge, to any person
23
+
* obtaining a copy of this software and associated documentation
24
+
* files (the "Software"), to deal in the Software without
25
+
* restriction, including without limitation the rights to use
26
+
* copy, modify, merge, publish, distribute, sublicense, and/or
27
+
* sell copies of the Software, and to permit persons to whom the
28
+
* Software is furnished to do so, subject to the following
29
+
* conditions:
30
+
*
31
+
* The above copyright notice and this permission notice shall be
32
+
* included in all copies or substantial portions of the Software.
33
+
*
34
+
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36
+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38
+
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39
+
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41
+
* OTHER DEALINGS IN THE SOFTWARE.
42
+
*/
43
+
/dts-v1/;
44
+
#include "imx6dl.dtsi"
45
+
#include "imx6qdl-aristainetos2.dtsi"
46
+
47
+
/ {
48
+
model = "aristainetos2 i.MX6 Dual Lite Board 4";
49
+
compatible = "fsl,imx6dl";
50
+
51
+
memory {
52
+
reg = <0x10000000 0x40000000>;
53
+
};
54
+
55
+
display0: display@di0 {
56
+
#address-cells = <1>;
57
+
#size-cells = <0>;
58
+
compatible = "fsl,imx-parallel-display";
59
+
interface-pix-fmt = "rgb24";
60
+
pinctrl-names = "default";
61
+
pinctrl-0 = <&pinctrl_ipu_disp>;
62
+
63
+
port@0 {
64
+
reg = <0>;
65
+
display0_in: endpoint {
66
+
remote-endpoint = <&ipu1_di0_disp0>;
67
+
};
68
+
};
69
+
70
+
port@1 {
71
+
reg = <1>;
72
+
display_out: endpoint {
73
+
remote-endpoint = <&panel_in>;
74
+
};
75
+
};
76
+
};
77
+
};
78
+
79
+
&ecspi1 {
80
+
lcd_panel: display@0 {
81
+
#address-cells = <1>;
82
+
#size-cells = <1>;
83
+
compatible = "lg,lg4573";
84
+
spi-max-frequency = <10000000>;
85
+
reg = <0>;
86
+
power-on-delay = <10>;
87
+
88
+
display-timings {
89
+
480x800p57 {
90
+
native-mode;
91
+
clock-frequency = <27000027>;
92
+
hactive = <480>;
93
+
vactive = <800>;
94
+
hfront-porch = <10>;
95
+
hback-porch = <59>;
96
+
hsync-len = <10>;
97
+
vback-porch = <15>;
98
+
vfront-porch = <15>;
99
+
vsync-len = <15>;
100
+
hsync-active = <1>;
101
+
vsync-active = <1>;
102
+
};
103
+
};
104
+
105
+
port {
106
+
panel_in: endpoint {
107
+
remote-endpoint = <&display_out>;
108
+
};
109
+
};
110
+
};
111
+
};
112
+
113
+
&i2c3 {
114
+
touch: touch@4b {
115
+
compatible = "atmel,maxtouch";
116
+
reg = <0x4b>;
117
+
interrupt-parent = <&gpio2>;
118
+
interrupts = <9 8>;
119
+
};
120
+
};
121
+
122
+
&ipu1_di0_disp0 {
123
+
remote-endpoint = <&display0_in>;
124
+
};
125
+
126
+
&iomuxc {
127
+
pinctrl_ipu_disp: ipudisp1grp {
128
+
fsl,pins = <
129
+
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
130
+
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1
131
+
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
132
+
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
133
+
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1
134
+
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1
135
+
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1
136
+
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1
137
+
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1
138
+
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1
139
+
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1
140
+
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1
141
+
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1
142
+
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1
143
+
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1
144
+
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1
145
+
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1
146
+
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1
147
+
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1
148
+
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1
149
+
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1
150
+
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1
151
+
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1
152
+
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1
153
+
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1
154
+
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1
155
+
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1
156
+
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1
157
+
>;
158
+
};
159
+
};
+97
arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
+97
arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
···
1
+
/*
2
+
* support for the imx6 based aristainetos2 board
3
+
*
4
+
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
5
+
*
6
+
* This file is dual-licensed: you can use it either under the terms
7
+
* of the GPL or the X11 license, at your option. Note that this dual
8
+
* licensing only applies to this file, and not this project as a
9
+
* whole.
10
+
*
11
+
* a) This file is free software; you can redistribute it and/or
12
+
* modify it under the terms of the GNU General Public License
13
+
* version 2 as published by the Free Software Foundation.
14
+
*
15
+
* This file is distributed in the hope that it will be useful
16
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
17
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18
+
* GNU General Public License for more details.
19
+
*
20
+
* Or, alternatively
21
+
*
22
+
* b) Permission is hereby granted, free of charge, to any person
23
+
* obtaining a copy of this software and associated documentation
24
+
* files (the "Software"), to deal in the Software without
25
+
* restriction, including without limitation the rights to use
26
+
* copy, modify, merge, publish, distribute, sublicense, and/or
27
+
* sell copies of the Software, and to permit persons to whom the
28
+
* Software is furnished to do so, subject to the following
29
+
* conditions:
30
+
*
31
+
* The above copyright notice and this permission notice shall be
32
+
* included in all copies or substantial portions of the Software.
33
+
*
34
+
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36
+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38
+
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39
+
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41
+
* OTHER DEALINGS IN THE SOFTWARE.
42
+
*/
43
+
/dts-v1/;
44
+
#include "imx6dl.dtsi"
45
+
#include "imx6qdl-aristainetos2.dtsi"
46
+
47
+
/ {
48
+
model = "aristainetos2 i.MX6 Dual Lite Board 7";
49
+
compatible = "fsl,imx6dl";
50
+
51
+
memory {
52
+
reg = <0x10000000 0x40000000>;
53
+
};
54
+
55
+
panel: panel {
56
+
compatible = "lg,lb070wv8";
57
+
backlight = <&backlight>;
58
+
enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
59
+
60
+
port {
61
+
panel_in: endpoint {
62
+
remote-endpoint = <&lvds0_out>;
63
+
};
64
+
};
65
+
};
66
+
};
67
+
68
+
&i2c3 {
69
+
touch: touch@4d {
70
+
compatible = "atmel,maxtouch";
71
+
reg = <0x4d>;
72
+
interrupt-parent = <&gpio2>;
73
+
interrupts = <9 8>;
74
+
};
75
+
};
76
+
77
+
&ldb {
78
+
status = "okay";
79
+
80
+
lvds-channel@0 {
81
+
status = "okay";
82
+
83
+
port@0 {
84
+
reg = <0>;
85
+
lvds0_in: endpoint {
86
+
remote-endpoint = <&ipu1_di0_lvds0>;
87
+
};
88
+
};
89
+
90
+
port@4 {
91
+
reg = <4>;
92
+
lvds0_out: endpoint {
93
+
remote-endpoint = <&panel_in>;
94
+
};
95
+
};
96
+
};
97
+
};
+633
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+633
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
···
1
+
/*
2
+
* support for the imx6 based aristainetos2 board
3
+
*
4
+
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
5
+
*
6
+
* This file is dual-licensed: you can use it either under the terms
7
+
* of the GPL or the X11 license, at your option. Note that this dual
8
+
* licensing only applies to this file, and not this project as a
9
+
* whole.
10
+
*
11
+
* a) This file is free software; you can redistribute it and/or
12
+
* modify it under the terms of the GNU General Public License
13
+
* version 2 as published by the Free Software Foundation.
14
+
*
15
+
* This file is distributed in the hope that it will be useful
16
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
17
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18
+
* GNU General Public License for more details.
19
+
*
20
+
* Or, alternatively
21
+
*
22
+
* b) Permission is hereby granted, free of charge, to any person
23
+
* obtaining a copy of this software and associated documentation
24
+
* files (the "Software"), to deal in the Software without
25
+
* restriction, including without limitation the rights to use
26
+
* copy, modify, merge, publish, distribute, sublicense, and/or
27
+
* sell copies of the Software, and to permit persons to whom the
28
+
* Software is furnished to do so, subject to the following
29
+
* conditions:
30
+
*
31
+
* The above copyright notice and this permission notice shall be
32
+
* included in all copies or substantial portions of the Software.
33
+
*
34
+
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
35
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36
+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38
+
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
39
+
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41
+
* OTHER DEALINGS IN THE SOFTWARE.
42
+
*/
43
+
#include <dt-bindings/gpio/gpio.h>
44
+
#include <dt-bindings/clock/imx6qdl-clock.h>
45
+
46
+
/ {
47
+
backlight: backlight {
48
+
compatible = "pwm-backlight";
49
+
pwms = <&pwm1 0 5000000>;
50
+
brightness-levels = <0 4 8 16 32 64 128 255>;
51
+
default-brightness-level = <7>;
52
+
enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
53
+
};
54
+
55
+
regulators {
56
+
compatible = "simple-bus";
57
+
58
+
reg_2p5v: 2p5v {
59
+
compatible = "regulator-fixed";
60
+
regulator-name = "2P5V";
61
+
regulator-min-microvolt = <2500000>;
62
+
regulator-max-microvolt = <2500000>;
63
+
regulator-always-on;
64
+
};
65
+
66
+
reg_3p3v: 3p3v {
67
+
compatible = "regulator-fixed";
68
+
regulator-name = "3P3V";
69
+
regulator-min-microvolt = <3300000>;
70
+
regulator-max-microvolt = <3300000>;
71
+
regulator-always-on;
72
+
};
73
+
74
+
reg_usbh1_vbus: usb-h1-vbus {
75
+
compatible = "regulator-fixed";
76
+
enable-active-high;
77
+
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
78
+
pinctrl-names = "default";
79
+
pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>;
80
+
regulator-name = "usb_h1_vbus";
81
+
regulator-min-microvolt = <5000000>;
82
+
regulator-max-microvolt = <5000000>;
83
+
};
84
+
85
+
reg_usbotg_vbus: usb-otg-vbus {
86
+
compatible = "regulator-fixed";
87
+
enable-active-high;
88
+
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
89
+
pinctrl-names = "default";
90
+
pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>;
91
+
regulator-name = "usb_otg_vbus";
92
+
regulator-min-microvolt = <5000000>;
93
+
regulator-max-microvolt = <5000000>;
94
+
};
95
+
};
96
+
};
97
+
98
+
&audmux {
99
+
pinctrl-names = "default";
100
+
pinctrl-0 = <&pinctrl_audmux>;
101
+
status = "okay";
102
+
};
103
+
104
+
&can1 {
105
+
pinctrl-names = "default";
106
+
pinctrl-0 = <&pinctrl_flexcan1>;
107
+
status = "okay";
108
+
};
109
+
110
+
&can2 {
111
+
pinctrl-names = "default";
112
+
pinctrl-0 = <&pinctrl_flexcan2>;
113
+
status = "okay";
114
+
};
115
+
116
+
&ecspi1 {
117
+
fsl,spi-num-chipselects = <3>;
118
+
cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
119
+
&gpio4 10 GPIO_ACTIVE_HIGH
120
+
&gpio4 11 GPIO_ACTIVE_HIGH>;
121
+
pinctrl-names = "default";
122
+
pinctrl-0 = <&pinctrl_ecspi1>;
123
+
status = "okay";
124
+
};
125
+
126
+
&ecspi2 {
127
+
fsl,spi-num-chipselects = <2>;
128
+
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>;
129
+
pinctrl-names = "default";
130
+
pinctrl-0 = <&pinctrl_ecspi2>;
131
+
status = "okay";
132
+
};
133
+
134
+
&ecspi4 {
135
+
fsl,spi-num-chipselects = <2>;
136
+
cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
137
+
pinctrl-names = "default";
138
+
pinctrl-0 = <&pinctrl_ecspi4>;
139
+
status = "okay";
140
+
141
+
flash: m25p80@1 {
142
+
#address-cells = <1>;
143
+
#size-cells = <1>;
144
+
compatible = "micron,n25q128a11";
145
+
spi-max-frequency = <20000000>;
146
+
reg = <1>;
147
+
};
148
+
};
149
+
150
+
&i2c1 {
151
+
pinctrl-names = "default";
152
+
pinctrl-0 = <&pinctrl_i2c1>;
153
+
status = "okay";
154
+
155
+
pmic@58 {
156
+
compatible = "dlg,da9063";
157
+
reg = <0x58>;
158
+
interrupt-parent = <&gpio1>;
159
+
interrupts = <04 0x8>;
160
+
161
+
regulators {
162
+
bcore1 {
163
+
regulator-name = "bcore1";
164
+
regulator-always-on = <1>;
165
+
regulator-min-microvolt = <300000>;
166
+
regulator-max-microvolt = <3300000>;
167
+
};
168
+
169
+
bcore2 {
170
+
regulator-name = "bcore2";
171
+
regulator-always-on = <1>;
172
+
regulator-min-microvolt = <300000>;
173
+
regulator-max-microvolt = <3300000>;
174
+
};
175
+
176
+
bpro {
177
+
regulator-name = "bpro";
178
+
regulator-always-on = <1>;
179
+
regulator-min-microvolt = <300000>;
180
+
regulator-max-microvolt = <3300000>;
181
+
};
182
+
183
+
bperi {
184
+
regulator-name = "bperi";
185
+
regulator-always-on = <1>;
186
+
regulator-min-microvolt = <300000>;
187
+
regulator-max-microvolt = <3300000>;
188
+
};
189
+
190
+
bmem {
191
+
regulator-name = "bmem";
192
+
regulator-always-on = <1>;
193
+
regulator-min-microvolt = <300000>;
194
+
regulator-max-microvolt = <3300000>;
195
+
};
196
+
197
+
ldo2 {
198
+
regulator-name = "ldo2";
199
+
regulator-always-on = <1>;
200
+
regulator-min-microvolt = <300000>;
201
+
regulator-max-microvolt = <1800000>;
202
+
};
203
+
204
+
ldo3 {
205
+
regulator-name = "ldo3";
206
+
regulator-always-on = <1>;
207
+
regulator-min-microvolt = <300000>;
208
+
regulator-max-microvolt = <3300000>;
209
+
};
210
+
211
+
ldo4 {
212
+
regulator-name = "ldo4";
213
+
regulator-always-on = <1>;
214
+
regulator-min-microvolt = <300000>;
215
+
regulator-max-microvolt = <3300000>;
216
+
};
217
+
218
+
ldo5 {
219
+
regulator-name = "ldo5";
220
+
regulator-always-on = <1>;
221
+
regulator-min-microvolt = <300000>;
222
+
regulator-max-microvolt = <3300000>;
223
+
};
224
+
225
+
ldo6 {
226
+
regulator-name = "ldo6";
227
+
regulator-always-on = <1>;
228
+
regulator-min-microvolt = <300000>;
229
+
regulator-max-microvolt = <3300000>;
230
+
};
231
+
232
+
ldo7 {
233
+
regulator-name = "ldo7";
234
+
regulator-always-on = <1>;
235
+
regulator-min-microvolt = <300000>;
236
+
regulator-max-microvolt = <3300000>;
237
+
};
238
+
239
+
ldo8 {
240
+
regulator-name = "ldo8";
241
+
regulator-always-on = <1>;
242
+
regulator-min-microvolt = <300000>;
243
+
regulator-max-microvolt = <3300000>;
244
+
};
245
+
246
+
ldo9 {
247
+
regulator-name = "ldo9";
248
+
regulator-always-on = <1>;
249
+
regulator-min-microvolt = <300000>;
250
+
regulator-max-microvolt = <3300000>;
251
+
};
252
+
253
+
ldo10 {
254
+
regulator-name = "ldo10";
255
+
regulator-always-on = <1>;
256
+
regulator-min-microvolt = <300000>;
257
+
regulator-max-microvolt = <3300000>;
258
+
};
259
+
260
+
ldo11 {
261
+
regulator-name = "ldo11";
262
+
regulator-always-on = <1>;
263
+
regulator-min-microvolt = <300000>;
264
+
regulator-max-microvolt = <3300000>;
265
+
};
266
+
267
+
bio {
268
+
regulator-name = "bio";
269
+
regulator-always-on = <1>;
270
+
regulator-min-microvolt = <1800000>;
271
+
regulator-max-microvolt = <1800000>;
272
+
};
273
+
};
274
+
};
275
+
276
+
tmp103: tmp103@71 {
277
+
compatible = "ti,tmp103";
278
+
reg = <0x71>;
279
+
};
280
+
};
281
+
282
+
&i2c2 {
283
+
pinctrl-names = "default";
284
+
pinctrl-0 = <&pinctrl_i2c2>;
285
+
status = "okay";
286
+
};
287
+
288
+
&i2c3 {
289
+
pinctrl-names = "default";
290
+
pinctrl-0 = <&pinctrl_i2c3>;
291
+
status = "okay";
292
+
293
+
expander: tca6416@20 {
294
+
compatible = "ti,tca6416";
295
+
reg = <0x20>;
296
+
#gpio-cells = <2>;
297
+
gpio-controller;
298
+
};
299
+
300
+
rtc@68 {
301
+
compatible = "dallas,m41t00";
302
+
reg = <0x68>;
303
+
};
304
+
};
305
+
306
+
&i2c4 {
307
+
pinctrl-names = "default";
308
+
pinctrl-0 = <&pinctrl_i2c4>;
309
+
status = "okay";
310
+
311
+
eeprom@50{
312
+
compatible = "atmel,24c64";
313
+
reg = <0x50>;
314
+
};
315
+
316
+
eeprom@57{
317
+
compatible = "atmel,24c64";
318
+
reg = <0x57>;
319
+
};
320
+
};
321
+
322
+
&fec {
323
+
pinctrl-names = "default";
324
+
pinctrl-0 = <&pinctrl_enet>;
325
+
phy-mode = "rgmii";
326
+
phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>;
327
+
txd0-skew-ps = <0>;
328
+
txd1-skew-ps = <0>;
329
+
txd2-skew-ps = <0>;
330
+
txd3-skew-ps = <0>;
331
+
status = "okay";
332
+
};
333
+
334
+
&gpmi {
335
+
pinctrl-names = "default";
336
+
pinctrl-0 = <&pinctrl_gpmi_nand>;
337
+
status = "okay";
338
+
};
339
+
340
+
&pcie {
341
+
reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
342
+
status = "okay";
343
+
};
344
+
345
+
&pwm1 {
346
+
pinctrl-names = "default";
347
+
pinctrl-0 = <&pinctrl_pwm1>;
348
+
status = "okay";
349
+
};
350
+
351
+
&uart1 {
352
+
pinctrl-names = "default";
353
+
pinctrl-0 = <&pinctrl_uart1>;
354
+
fsl,uart-has-rtscts;
355
+
status = "okay";
356
+
};
357
+
358
+
&uart2 {
359
+
pinctrl-names = "default";
360
+
pinctrl-0 = <&pinctrl_uart2>;
361
+
status = "okay";
362
+
};
363
+
364
+
&uart3 {
365
+
pinctrl-names = "default";
366
+
pinctrl-0 = <&pinctrl_uart3>;
367
+
fsl,uart-has-rtscts;
368
+
status = "okay";
369
+
};
370
+
371
+
&uart4 {
372
+
pinctrl-names = "default";
373
+
pinctrl-0 = <&pinctrl_uart4>;
374
+
status = "okay";
375
+
};
376
+
377
+
&usbh1 {
378
+
vbus-supply = <®_usbh1_vbus>;
379
+
dr_mode = "host";
380
+
status = "okay";
381
+
};
382
+
383
+
&usbotg {
384
+
vbus-supply = <®_usbotg_vbus>;
385
+
pinctrl-names = "default";
386
+
pinctrl-0 = <&pinctrl_usbotg>;
387
+
disable-over-current;
388
+
dr_mode = "host";
389
+
status = "okay";
390
+
};
391
+
392
+
&usdhc1 {
393
+
pinctrl-names = "default";
394
+
pinctrl-0 = <&pinctrl_usdhc1>;
395
+
cd-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
396
+
no-1-8-v;
397
+
status = "okay";
398
+
};
399
+
400
+
&usdhc2 {
401
+
pinctrl-names = "default";
402
+
pinctrl-0 = <&pinctrl_usdhc2>;
403
+
cd-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
404
+
wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
405
+
no-1-8-v;
406
+
status = "okay";
407
+
};
408
+
409
+
&iomuxc {
410
+
pinctrl-names = "default";
411
+
pinctrl-0 = <&pinctrl_gpio>;
412
+
413
+
pinctrl_audmux: audmux {
414
+
fsl,pins = <
415
+
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
416
+
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
417
+
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
418
+
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
419
+
>;
420
+
};
421
+
422
+
pinctrl_ecspi1: ecspi1grp {
423
+
fsl,pins = <
424
+
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
425
+
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
426
+
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
427
+
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
428
+
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
429
+
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
430
+
>;
431
+
};
432
+
433
+
pinctrl_ecspi2: ecspi2grp {
434
+
fsl,pins = <
435
+
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
436
+
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
437
+
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
438
+
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */
439
+
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */
440
+
>;
441
+
};
442
+
443
+
pinctrl_ecspi4: ecspi4grp {
444
+
fsl,pins = <
445
+
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
446
+
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
447
+
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
448
+
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
449
+
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
450
+
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
451
+
>;
452
+
};
453
+
454
+
pinctrl_enet: enetgrp {
455
+
fsl,pins = <
456
+
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
457
+
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
458
+
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
459
+
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
460
+
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
461
+
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
462
+
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
463
+
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
464
+
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
465
+
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
466
+
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
467
+
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
468
+
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
469
+
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
470
+
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
471
+
>;
472
+
};
473
+
474
+
pinctrl_flexcan1: flexcan1grp {
475
+
fsl,pins = <
476
+
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
477
+
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
478
+
>;
479
+
};
480
+
481
+
pinctrl_flexcan2: flexcan2grp {
482
+
fsl,pins = <
483
+
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
484
+
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
485
+
>;
486
+
};
487
+
488
+
pinctrl_gpio: gpiogrp {
489
+
fsl,pins = <
490
+
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* led enable */
491
+
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* LCD power enable */
492
+
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* led yellow */
493
+
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 /* led red */
494
+
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 /* led green */
495
+
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 /* led blue */
496
+
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* Profibus IRQ */
497
+
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* FPGA IRQ */
498
+
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* spi bus #2 SS driver enable */
499
+
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/
500
+
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b0b0 /* USB_OTG_ID = GPIO1_24*/
501
+
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* Touchscreen IRQ */
502
+
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 /* PCIe reset */
503
+
>;
504
+
};
505
+
506
+
pinctrl_gpmi_nand: gpmi-nand {
507
+
fsl,pins = <
508
+
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
509
+
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
510
+
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
511
+
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
512
+
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
513
+
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
514
+
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
515
+
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
516
+
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
517
+
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
518
+
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
519
+
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
520
+
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
521
+
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
522
+
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
523
+
>;
524
+
};
525
+
526
+
pinctrl_i2c1: i2c1grp {
527
+
fsl,pins = <
528
+
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
529
+
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
530
+
>;
531
+
};
532
+
533
+
pinctrl_i2c2: i2c2grp {
534
+
fsl,pins = <
535
+
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
536
+
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
537
+
>;
538
+
};
539
+
540
+
pinctrl_i2c3: i2c3grp {
541
+
fsl,pins = <
542
+
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
543
+
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
544
+
>;
545
+
};
546
+
547
+
pinctrl_i2c4: i2c4grp {
548
+
fsl,pins = <
549
+
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
550
+
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
551
+
>;
552
+
};
553
+
554
+
pinctrl_pwm1: pwm1grp {
555
+
fsl,pins = <
556
+
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
557
+
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 /* backlight enable */
558
+
>;
559
+
};
560
+
561
+
pinctrl_uart1: uart1grp {
562
+
fsl,pins = <
563
+
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
564
+
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
565
+
MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
566
+
MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
567
+
>;
568
+
};
569
+
570
+
pinctrl_uart2: uart2grp {
571
+
fsl,pins = <
572
+
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
573
+
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
574
+
>;
575
+
};
576
+
577
+
pinctrl_uart3: uart3grp {
578
+
fsl,pins = <
579
+
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
580
+
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
581
+
MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
582
+
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
583
+
>;
584
+
};
585
+
586
+
pinctrl_uart4: uart4grp {
587
+
fsl,pins = <
588
+
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
589
+
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
590
+
>;
591
+
};
592
+
593
+
pinctrl_usbotg: usbotggrp {
594
+
fsl,pins = <
595
+
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
596
+
>;
597
+
};
598
+
599
+
pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus {
600
+
fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>;
601
+
};
602
+
603
+
pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus {
604
+
fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>;
605
+
};
606
+
607
+
pinctrl_usdhc1: usdhc1grp {
608
+
fsl,pins = <
609
+
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
610
+
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
611
+
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
612
+
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
613
+
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
614
+
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
615
+
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 /* SD1 card detect input */
616
+
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* SD1 write protect input */
617
+
>;
618
+
};
619
+
620
+
pinctrl_usdhc2: usdhc2grp {
621
+
fsl,pins = <
622
+
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
623
+
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
624
+
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
625
+
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
626
+
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
627
+
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
628
+
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 /* SD2 level shifter output enable */
629
+
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 card detect input */
630
+
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SD2 write protect input */
631
+
>;
632
+
};
633
+
};