tjh.dev / kernel
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drm/radeon: Clean up errors in smu7_discrete.h

Fix the following errors reported by checkpatch:

ERROR: open brace '{' following struct go on the same line

Signed-off-by: GuoHua Chen <chenguohua_716@163.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

GuoHua Chen and committed by
Alex Deucher d93eb053 007cded6

+17 -34
+17 -34
drivers/gpu/drm/radeon/smu7_discrete.h
··· 35 35 #define SMU7_NUM_GPU_TES 1 36 36 #define SMU7_NUM_NON_TES 2 37 37 38 - struct SMU7_SoftRegisters 39 - { 38 + struct SMU7_SoftRegisters { 40 39 uint32_t RefClockFrequency; 41 40 uint32_t PmTimerP; 42 41 uint32_t FeatureEnables; ··· 88 89 89 90 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 90 91 91 - struct SMU7_Discrete_VoltageLevel 92 - { 92 + struct SMU7_Discrete_VoltageLevel { 93 93 uint16_t Voltage; 94 94 uint16_t StdVoltageHiSidd; 95 95 uint16_t StdVoltageLoSidd; ··· 98 100 99 101 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; 100 102 101 - struct SMU7_Discrete_GraphicsLevel 102 - { 103 + struct SMU7_Discrete_GraphicsLevel { 103 104 uint32_t Flags; 104 105 uint32_t MinVddc; 105 106 uint32_t MinVddcPhases; ··· 128 131 129 132 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; 130 133 131 - struct SMU7_Discrete_ACPILevel 132 - { 134 + struct SMU7_Discrete_ACPILevel { 133 135 uint32_t Flags; 134 136 uint32_t MinVddc; 135 137 uint32_t MinVddcPhases; ··· 149 153 150 154 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; 151 155 152 - struct SMU7_Discrete_Ulv 153 - { 156 + struct SMU7_Discrete_Ulv { 154 157 uint32_t CcPwrDynRm; 155 158 uint32_t CcPwrDynRm1; 156 159 uint16_t VddcOffset; ··· 160 165 161 166 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; 162 167 163 - struct SMU7_Discrete_MemoryLevel 164 - { 168 + struct SMU7_Discrete_MemoryLevel { 165 169 uint32_t MinVddc; 166 170 uint32_t MinVddcPhases; 167 171 uint32_t MinVddci; ··· 200 206 201 207 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; 202 208 203 - struct SMU7_Discrete_LinkLevel 204 - { 209 + struct SMU7_Discrete_LinkLevel { 205 210 uint8_t PcieGenSpeed; 206 211 uint8_t PcieLaneCount; 207 212 uint8_t EnabledForActivity; ··· 213 220 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; 214 221 215 222 216 - struct SMU7_Discrete_MCArbDramTimingTableEntry 217 - { 223 + struct SMU7_Discrete_MCArbDramTimingTableEntry { 218 224 uint32_t McArbDramTiming; 219 225 uint32_t McArbDramTiming2; 220 226 uint8_t McArbBurstTime; ··· 222 230 223 231 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; 224 232 225 - struct SMU7_Discrete_MCArbDramTimingTable 226 - { 233 + struct SMU7_Discrete_MCArbDramTimingTable { 227 234 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 228 235 }; 229 236 230 237 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; 231 238 232 - struct SMU7_Discrete_UvdLevel 233 - { 239 + struct SMU7_Discrete_UvdLevel { 234 240 uint32_t VclkFrequency; 235 241 uint32_t DclkFrequency; 236 242 uint16_t MinVddc; ··· 240 250 241 251 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; 242 252 243 - struct SMU7_Discrete_ExtClkLevel 244 - { 253 + struct SMU7_Discrete_ExtClkLevel { 245 254 uint32_t Frequency; 246 255 uint16_t MinVoltage; 247 256 uint8_t MinPhases; ··· 249 260 250 261 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; 251 262 252 - struct SMU7_Discrete_StateInfo 253 - { 263 + struct SMU7_Discrete_StateInfo { 254 264 uint32_t SclkFrequency; 255 265 uint32_t MclkFrequency; 256 266 uint32_t VclkFrequency; ··· 273 285 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; 274 286 275 287 276 - struct SMU7_Discrete_DpmTable 277 - { 288 + struct SMU7_Discrete_DpmTable { 278 289 SMU7_PIDController GraphicsPIDController; 279 290 SMU7_PIDController MemoryPIDController; 280 291 SMU7_PIDController LinkPIDController; ··· 393 406 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 394 407 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY 395 408 396 - struct SMU7_Discrete_MCRegisterAddress 397 - { 409 + struct SMU7_Discrete_MCRegisterAddress { 398 410 uint16_t s0; 399 411 uint16_t s1; 400 412 }; 401 413 402 414 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; 403 415 404 - struct SMU7_Discrete_MCRegisterSet 405 - { 416 + struct SMU7_Discrete_MCRegisterSet { 406 417 uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 407 418 }; 408 419 409 420 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; 410 421 411 - struct SMU7_Discrete_MCRegisters 412 - { 422 + struct SMU7_Discrete_MCRegisters { 413 423 uint8_t last; 414 424 uint8_t reserved[3]; 415 425 SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; ··· 415 431 416 432 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; 417 433 418 - struct SMU7_Discrete_FanTable 419 - { 434 + struct SMU7_Discrete_FanTable { 420 435 uint16_t FdoMode; 421 436 int16_t TempMin; 422 437 int16_t TempMed;