media: qcom: camss: Fix invalid clock enable bit disjunction

define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)

disjunction for gen2 ? BIT(7) : is a nop we are setting the same bit
either way.

Fixes: 4abb21309fda ("media: camss: csiphy: Move to hardcode CSI Clock Lane number")
Cc: [e-mail]
Signed-off-by: Bryan O'Donoghue <[e-mail]>
Reviewed-by: Konrad Dybcio <[e-mail]>
Reviewed-by: Laurent Pinchart <[e-mail]>
Signed-off-by: Hans Verkuil <[e-mail]>

drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c

···
 
 	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
 
-	val = is_gen2 ? BIT(7) : CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
+	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
 	for (i = 0; i < c->num_data; i++)
 		val |= BIT(c->data[i].pos * 2);