tjh.dev
+8
arch/mips/dec/ioasic-irq.c
+8
arch/mips/dec/ioasic-irq.c
···
51
51
.irq_unmask = unmask_ioasic_irq,
52
52
};
53
53
54
+
void clear_ioasic_dma_irq(unsigned int irq)
55
+
{
56
+
u32 sir;
57
+
58
+
sir = ~(1 << (irq - ioasic_irq_base));
59
+
ioasic_write(IO_REG_SIR, sir);
60
+
}
61
+
54
62
static struct irq_chip ioasic_dma_irq_type = {
55
63
.name = "IO-ASIC-DMA",
56
64
.irq_ack = ack_ioasic_irq,
+19
-3
arch/mips/dec/time.c
+19
-3
arch/mips/dec/time.c
···
125
125
126
126
void __init plat_time_init(void)
127
127
{
128
+
int ioasic_clock = 0;
128
129
u32 start, end;
129
130
int i = HZ / 8;
130
131
131
132
/* Set up the rate of periodic DS1287 interrupts. */
132
133
ds1287_set_base_clock(HZ);
133
134
135
+
/* On some I/O ASIC systems we have the I/O ASIC's counter. */
136
+
if (IOASIC)
137
+
ioasic_clock = dec_ioasic_clocksource_init() == 0;
134
138
if (cpu_has_counter) {
135
139
ds1287_timer_state();
136
140
while (!ds1287_timer_state())
···
151
147
mips_hpt_frequency = (end - start) * 8;
152
148
printk(KERN_INFO "MIPS counter frequency %dHz\n",
153
149
mips_hpt_frequency);
154
-
} else if (IOASIC)
155
-
/* For pre-R4k systems we use the I/O ASIC's counter. */
156
-
dec_ioasic_clocksource_init();
150
+
151
+
/*
152
+
* All R4k DECstations suffer from the CP0 Count erratum,
153
+
* so we can't use the timer as a clock source, and a clock
154
+
* event both at a time. An accurate wall clock is more
155
+
* important than a high-precision interval timer so only
156
+
* use the timer as a clock source, and not a clock event
157
+
* if there's no I/O ASIC counter available to serve as a
158
+
* clock source.
159
+
*/
160
+
if (!ioasic_clock) {
161
+
init_r4k_clocksource();
162
+
mips_hpt_frequency = 0;
163
+
}
164
+
}
157
165
158
166
ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
159
167
}
+3
-1
arch/mips/include/asm/dec/ioasic.h
+3
-1
arch/mips/include/asm/dec/ioasic.h
···
31
31
return ioasic_base[reg / 4];
32
32
}
33
33
34
+
extern void clear_ioasic_dma_irq(unsigned int irq);
35
+
34
36
extern void init_ioasic_irqs(int base);
35
37
36
-
extern void dec_ioasic_clocksource_init(void);
38
+
extern int dec_ioasic_clocksource_init(void);
37
39
38
40
#endif /* __ASM_DEC_IOASIC_H */
+7
-1
arch/mips/kernel/csrc-ioasic.c
+7
-1
arch/mips/kernel/csrc-ioasic.c
···
37
37
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
38
38
};
39
39
40
-
void __init dec_ioasic_clocksource_init(void)
40
+
int __init dec_ioasic_clocksource_init(void)
41
41
{
42
42
unsigned int freq;
43
43
u32 start, end;
···
56
56
end = dec_ioasic_hpt_read(&clocksource_dec);
57
57
58
58
freq = (end - start) * 8;
59
+
60
+
/* An early revision of the I/O ASIC didn't have the counter. */
61
+
if (!freq)
62
+
return -ENXIO;
63
+
59
64
printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
60
65
61
66
clocksource_dec.rating = 200 + freq / 10000000;
62
67
clocksource_register_hz(&clocksource_dec, freq);
68
+
return 0;
63
69
}
+11
-2
arch/mips/kernel/smp-cmp.c
+11
-2
arch/mips/kernel/smp-cmp.c
···
99
99
100
100
c->core = (read_c0_ebase() >> 1) & 0x1ff;
101
101
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
102
-
c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
102
+
if (cpu_has_mipsmt)
103
+
c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
104
+
TCBIND_CURVPE;
103
105
#endif
104
106
#ifdef CONFIG_MIPS_MT_SMTC
105
107
c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
···
179
177
}
180
178
181
179
if (cpu_has_mipsmt) {
182
-
unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
180
+
unsigned int nvpe = 1;
181
+
#ifdef CONFIG_MIPS_MT_SMP
182
+
unsigned int mvpconf0 = read_c0_mvpconf0();
183
+
184
+
nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
185
+
#elif defined(CONFIG_MIPS_MT_SMTC)
186
+
unsigned int mvpconf0 = read_c0_mvpconf0();
183
187
184
188
nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
189
+
#endif
185
190
smp_num_siblings = nvpe;
186
191
}
187
192
pr_info("Detected %i available secondary CPU(s)\n", ncpu);
+1
-1
arch/mips/kernel/vpe.c
+1
-1
arch/mips/kernel/vpe.c