tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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sfc: update EF10 register definitions

The RX_L4_CLASS field has shrunk from 3 bits to 2 bits. The upper
bit was never used in previous hardware, so we can use the new
definition throughout.

The TSO OUTER_IPID field was previously spelt differently from the
external definitions.

Signed-off-by: Edward Cree <ecree@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Bert Kenward and committed by
David S. Miller d8d8ccf2 acaef3c1

+37 -25
+8 -8
drivers/net/ethernet/sfc/ef10.c
··· 3292 3292 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 3293 3293 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 3294 3294 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 3295 - (rx_l4_class != ESE_DZ_L4_CLASS_TCP && 3296 - rx_l4_class != ESE_DZ_L4_CLASS_UDP)))) 3295 + (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 3296 + rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 3297 3297 netdev_WARN(efx->net_dev, 3298 3298 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 3299 3299 EFX_QWORD_FMT "\n", ··· 3330 3330 EFX_QWORD_VAL(*event)); 3331 3331 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 3332 3332 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 3333 - (rx_l4_class != ESE_DZ_L4_CLASS_TCP && 3334 - rx_l4_class != ESE_DZ_L4_CLASS_UDP))) 3333 + (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 3334 + rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 3335 3335 netdev_WARN(efx->net_dev, 3336 3336 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 3337 3337 EFX_QWORD_FMT "\n", ··· 3366 3366 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 3367 3367 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 3368 3368 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 3369 - rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 3369 + rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 3370 3370 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 3371 3371 rx_encap_hdr = 3372 3372 nic_data->datapath_caps & ··· 3444 3444 rx_l3_class, rx_l4_class, 3445 3445 event); 3446 3446 } else { 3447 - bool tcpudp = rx_l4_class == ESE_DZ_L4_CLASS_TCP || 3448 - rx_l4_class == ESE_DZ_L4_CLASS_UDP; 3447 + bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 3448 + rx_l4_class == ESE_FZ_L4_CLASS_UDP; 3449 3449 3450 3450 switch (rx_encap_hdr) { 3451 3451 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ ··· 3466 3466 } 3467 3467 } 3468 3468 3469 - if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 3469 + if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 3470 3470 flags |= EFX_RX_PKT_TCP; 3471 3471 3472 3472 channel->irq_mod_score += 2 * n_packets;
+29 -17
drivers/net/ethernet/sfc/ef10_regs.h
··· 1 1 /**************************************************************************** 2 2 * Driver for Solarflare network controllers and boards 3 - * Copyright 2012-2015 Solarflare Communications Inc. 3 + * Copyright 2012-2017 Solarflare Communications Inc. 4 4 * 5 5 * This program is free software; you can redistribute it and/or modify it 6 6 * under the terms of the GNU General Public License version 2 as published ··· 79 79 #define ER_DZ_EVQ_TMR 0x00000420 80 80 #define ER_DZ_EVQ_TMR_STEP 8192 81 81 #define ER_DZ_EVQ_TMR_ROWS 2048 82 + #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 83 + #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 82 84 #define ERF_DZ_TC_TIMER_MODE_LBN 14 83 85 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 84 86 #define ERF_DZ_TC_TIMER_VAL_LBN 0 ··· 161 159 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 162 160 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 163 161 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 164 - #define ESF_DZ_RX_L4_CLASS_LBN 45 165 - #define ESF_DZ_RX_L4_CLASS_WIDTH 3 166 - #define ESE_DZ_L4_CLASS_RSVD7 7 167 - #define ESE_DZ_L4_CLASS_RSVD6 6 168 - #define ESE_DZ_L4_CLASS_RSVD5 5 169 - #define ESE_DZ_L4_CLASS_RSVD4 4 170 - #define ESE_DZ_L4_CLASS_RSVD3 3 171 - #define ESE_DZ_L4_CLASS_UDP 2 172 - #define ESE_DZ_L4_CLASS_TCP 1 173 - #define ESE_DZ_L4_CLASS_UNKNOWN 0 162 + #define ESF_DE_RX_L4_CLASS_LBN 45 163 + #define ESF_DE_RX_L4_CLASS_WIDTH 3 164 + #define ESE_DE_L4_CLASS_RSVD7 7 165 + #define ESE_DE_L4_CLASS_RSVD6 6 166 + #define ESE_DE_L4_CLASS_RSVD5 5 167 + #define ESE_DE_L4_CLASS_RSVD4 4 168 + #define ESE_DE_L4_CLASS_RSVD3 3 169 + #define ESE_DE_L4_CLASS_UDP 2 170 + #define ESE_DE_L4_CLASS_TCP 1 171 + #define ESE_DE_L4_CLASS_UNKNOWN 0 172 + #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 173 + #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 174 + #define ESF_FZ_RX_L4_CLASS_LBN 45 175 + #define ESF_FZ_RX_L4_CLASS_WIDTH 2 176 + #define ESE_FZ_L4_CLASS_RSVD3 3 177 + #define ESE_FZ_L4_CLASS_UDP 2 178 + #define ESE_FZ_L4_CLASS_TCP 1 179 + #define ESE_FZ_L4_CLASS_UNKNOWN 0 174 180 #define ESF_DZ_RX_L3_CLASS_LBN 42 175 181 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 176 182 #define ESE_DZ_L3_CLASS_RSVD7 7 ··· 225 215 #define ESF_EZ_RX_ABORT_WIDTH 1 226 216 #define ESF_DZ_RX_ECC_ERR_LBN 29 227 217 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 218 + #define ESF_DZ_RX_TRUNC_ERR_LBN 29 219 + #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 228 220 #define ESF_DZ_RX_CRC1_ERR_LBN 28 229 221 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 230 222 #define ESF_DZ_RX_CRC0_ERR_LBN 27 ··· 344 332 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 345 333 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 346 334 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 335 + #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 336 + #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 347 337 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 348 338 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 349 339 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 ··· 355 341 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 356 342 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 357 343 358 - /* TX_TSO_FATSO2A_DESC */ 344 + /* TX_TSO_V2_DESC_A */ 359 345 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 360 346 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 361 347 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 ··· 374 360 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 375 361 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 376 362 377 - 378 - /* TX_TSO_FATSO2B_DESC */ 363 + /* TX_TSO_V2_DESC_B */ 379 364 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 380 365 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 381 366 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 ··· 388 375 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 389 376 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 390 377 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 391 - #define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 0 392 - #define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16 393 378 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 394 379 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 395 - 380 + #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 381 + #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 396 382 397 383 /*************************************************************************/ 398 384