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linux
staging: iio: ad9832: Moved contents of the header to the source file
Moved the contents of the header(ad9832.h) into the corresponding source file
with the exception of the platform data struct which is supposed to be
used from somewhere else other than the driver.
Signed-off-by: Narcisa Ana Maria Vasile <narcisaanamaria12@gmail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
authored by
Narcisa Ana Maria Vasile
and committed by
Jonathan Cameron
d89aa245
a8baa3c0
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-92
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drivers/staging/iio/frequency/ad9832.c
+92
drivers/staging/iio/frequency/ad9832.c
···
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#include "ad9832.h"
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/* Registers */
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#define AD9832_FREQ0LL 0x0
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#define AD9832_FREQ0HL 0x1
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#define AD9832_FREQ0LM 0x2
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#define AD9832_FREQ0HM 0x3
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#define AD9832_FREQ1LL 0x4
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#define AD9832_FREQ1HL 0x5
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#define AD9832_FREQ1LM 0x6
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#define AD9832_FREQ1HM 0x7
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#define AD9832_PHASE0L 0x8
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#define AD9832_PHASE0H 0x9
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#define AD9832_PHASE1L 0xA
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#define AD9832_PHASE1H 0xB
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#define AD9832_PHASE2L 0xC
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#define AD9832_PHASE2H 0xD
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#define AD9832_PHASE3L 0xE
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#define AD9832_PHASE3H 0xF
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#define AD9832_PHASE_SYM 0x10
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#define AD9832_FREQ_SYM 0x11
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#define AD9832_PINCTRL_EN 0x12
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#define AD9832_OUTPUT_EN 0x13
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/* Command Control Bits */
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#define AD9832_CMD_PHA8BITSW 0x1
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#define AD9832_CMD_PHA16BITSW 0x0
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#define AD9832_CMD_FRE8BITSW 0x3
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#define AD9832_CMD_FRE16BITSW 0x2
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#define AD9832_CMD_FPSELECT 0x6
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#define AD9832_CMD_SYNCSELSRC 0x8
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#define AD9832_CMD_SLEEPRESCLR 0xC
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#define AD9832_FREQ BIT(11)
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#define AD9832_PHASE(x) (((x) & 3) << 9)
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#define AD9832_SYNC BIT(13)
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#define AD9832_SELSRC BIT(12)
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#define AD9832_SLEEP BIT(13)
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#define AD9832_RESET BIT(12)
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#define AD9832_CLR BIT(11)
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#define CMD_SHIFT 12
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#define ADD_SHIFT 8
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#define AD9832_FREQ_BITS 32
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#define AD9832_PHASE_BITS 12
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#define RES_MASK(bits) ((1 << (bits)) - 1)
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/**
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* struct ad9832_state - driver instance specific data
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* @spi: spi_device
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* @avdd: supply regulator for the analog section
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* @dvdd: supply regulator for the digital section
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* @mclk: external master clock
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* @ctrl_fp: cached frequency/phase control word
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* @ctrl_ss: cached sync/selsrc control word
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* @ctrl_src: cached sleep/reset/clr word
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* @xfer: default spi transfer
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* @msg: default spi message
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* @freq_xfer: tuning word spi transfer
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* @freq_msg: tuning word spi message
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* @phase_xfer: tuning word spi transfer
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* @phase_msg: tuning word spi message
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* @data: spi transmit buffer
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* @phase_data: tuning word spi transmit buffer
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* @freq_data: tuning word spi transmit buffer
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*/
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struct ad9832_state {
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struct spi_device *spi;
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struct regulator *avdd;
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struct regulator *dvdd;
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unsigned long mclk;
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unsigned short ctrl_fp;
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unsigned short ctrl_ss;
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unsigned short ctrl_src;
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struct spi_transfer xfer;
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struct spi_message msg;
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struct spi_transfer freq_xfer[4];
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struct spi_message freq_msg;
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struct spi_transfer phase_xfer[2];
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struct spi_message phase_msg;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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__be16 freq_data[4]____cacheline_aligned;
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__be16 phase_data[2];
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__be16 data;
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};
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};
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static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
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{
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unsigned long long freqreg = (u64)fout *
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drivers/staging/iio/frequency/ad9832.h
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drivers/staging/iio/frequency/ad9832.h
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#ifndef IIO_DDS_AD9832_H_
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#define IIO_DDS_AD9832_H_
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/* Registers */
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#define AD9832_FREQ0LL 0x0
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#define AD9832_FREQ0HL 0x1
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#define AD9832_FREQ0LM 0x2
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#define AD9832_FREQ0HM 0x3
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#define AD9832_FREQ1LL 0x4
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#define AD9832_FREQ1HL 0x5
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#define AD9832_FREQ1LM 0x6
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#define AD9832_FREQ1HM 0x7
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#define AD9832_PHASE0L 0x8
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#define AD9832_PHASE0H 0x9
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#define AD9832_PHASE1L 0xA
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#define AD9832_PHASE1H 0xB
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#define AD9832_PHASE2L 0xC
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#define AD9832_PHASE2H 0xD
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#define AD9832_PHASE3L 0xE
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#define AD9832_PHASE3H 0xF
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#define AD9832_PHASE_SYM 0x10
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#define AD9832_FREQ_SYM 0x11
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#define AD9832_PINCTRL_EN 0x12
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#define AD9832_OUTPUT_EN 0x13
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/* Command Control Bits */
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#define AD9832_CMD_PHA8BITSW 0x1
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#define AD9832_CMD_PHA16BITSW 0x0
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#define AD9832_CMD_FRE8BITSW 0x3
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#define AD9832_CMD_FRE16BITSW 0x2
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#define AD9832_CMD_FPSELECT 0x6
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#define AD9832_CMD_SYNCSELSRC 0x8
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#define AD9832_CMD_SLEEPRESCLR 0xC
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#define AD9832_FREQ BIT(11)
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#define AD9832_PHASE(x) (((x) & 3) << 9)
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#define AD9832_SYNC BIT(13)
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#define AD9832_SELSRC BIT(12)
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#define AD9832_SLEEP BIT(13)
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#define AD9832_RESET BIT(12)
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#define AD9832_CLR BIT(11)
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#define CMD_SHIFT 12
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#define ADD_SHIFT 8
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#define AD9832_FREQ_BITS 32
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#define AD9832_PHASE_BITS 12
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#define RES_MASK(bits) ((1 << (bits)) - 1)
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/**
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* struct ad9832_state - driver instance specific data
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* @spi: spi_device
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* @avdd: supply regulator for the analog section
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* @dvdd: supply regulator for the digital section
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* @mclk: external master clock
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* @ctrl_fp: cached frequency/phase control word
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* @ctrl_ss: cached sync/selsrc control word
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* @ctrl_src: cached sleep/reset/clr word
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* @xfer: default spi transfer
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* @msg: default spi message
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* @freq_xfer: tuning word spi transfer
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* @freq_msg: tuning word spi message
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* @phase_xfer: tuning word spi transfer
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* @phase_msg: tuning word spi message
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* @data: spi transmit buffer
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* @phase_data: tuning word spi transmit buffer
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* @freq_data: tuning word spi transmit buffer
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*/
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struct ad9832_state {
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struct spi_device *spi;
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struct regulator *avdd;
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struct regulator *dvdd;
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unsigned long mclk;
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unsigned short ctrl_fp;
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unsigned short ctrl_ss;
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unsigned short ctrl_src;
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struct spi_transfer xfer;
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struct spi_message msg;
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struct spi_transfer freq_xfer[4];
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struct spi_message freq_msg;
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struct spi_transfer phase_xfer[2];
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struct spi_message phase_msg;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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__be16 freq_data[4]____cacheline_aligned;
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__be16 phase_data[2];
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__be16 data;
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};
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};
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/*
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* TODO: struct ad9832_platform_data needs to go into include/linux/iio
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*/