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phy: qcom-qmp: qserdes-com-v3: add missing registers

Add missing registers, verified against:
- msm-4.4's phy-qcom-ufs-qmp-v3.h

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-23-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul d88b3058 f7c5cedb

+28
+25
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
··· 27 27 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 28 28 #define QSERDES_V3_COM_PLL_EN 0x044 29 29 #define QSERDES_V3_COM_PLL_IVCO 0x048 30 + #define QSERDES_V3_COM_CMN_IETRIM 0x04c 31 + #define QSERDES_V3_COM_CMN_IPTRIM 0x050 32 + #define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054 33 + #define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058 30 34 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 31 35 #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 32 36 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 ··· 38 34 #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 39 35 #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 40 36 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 37 + #define QSERDES_V3_COM_PLL_CNTRL 0x078 38 + #define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c 41 39 #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 40 + #define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084 42 41 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 43 42 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 44 43 #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 ··· 61 54 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 62 55 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 63 56 #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 57 + #define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4 64 58 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 65 59 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 66 60 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 67 61 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 62 + #define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8 68 63 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 69 64 #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 70 65 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 ··· 75 66 #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 76 67 #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 77 68 #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 69 + #define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c 70 + #define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110 71 + #define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114 72 + #define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118 78 73 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 79 74 #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 75 + #define QSERDES_V3_COM_CMN_STATUS 0x124 76 + #define QSERDES_V3_COM_RESET_SM_STATUS 0x128 77 + #define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c 78 + #define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130 79 + #define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134 80 80 #define QSERDES_V3_COM_CLK_SELECT 0x138 81 81 #define QSERDES_V3_COM_HSCLK_SEL 0x13c 82 + #define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140 83 + #define QSERDES_V3_COM_PLL_ANALOG 0x144 82 84 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 83 85 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 86 + #define QSERDES_V3_COM_SW_RESET 0x150 84 87 #define QSERDES_V3_COM_CORE_CLK_EN 0x154 85 88 #define QSERDES_V3_COM_C_READY_STATUS 0x158 86 89 #define QSERDES_V3_COM_CMN_CONFIG 0x15c 90 + #define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160 87 91 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 88 92 #define QSERDES_V3_COM_DEBUG_BUS0 0x168 89 93 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 90 94 #define QSERDES_V3_COM_DEBUG_BUS2 0x170 91 95 #define QSERDES_V3_COM_DEBUG_BUS3 0x174 92 96 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 97 + #define QSERDES_V3_COM_CMN_MISC1 0x17c 98 + #define QSERDES_V3_COM_CMN_MISC2 0x180 93 99 #define QSERDES_V3_COM_CMN_MODE 0x184 100 + #define QSERDES_V3_COM_CMN_VREG_SEL 0x188 94 101 95 102 #endif
+3
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
··· 26 26 #define QSERDES_V3_TX_TX_POL_INV 0x064 27 27 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 28 28 #define QSERDES_V3_TX_LANE_MODE_1 0x08c 29 + #define QSERDES_V3_TX_LANE_MODE_2 0x090 30 + #define QSERDES_V3_TX_LANE_MODE_3 0x094 29 31 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 30 32 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 31 33 #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 ··· 50 48 #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 51 49 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 52 50 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 51 + #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 53 52 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 54 53 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 55 54 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc