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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull some non-critical i.MX clk fixes from Shawn Guo:
* Fix the commit 3713e3f5e927 ("clk: imx35: define two clocks for rtc")
which messed up the clock enumeration when adding new clock.
* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx35: restore existing used clock enumeration
clk: imx6q: fix typo in CAN clock definition
+4
-3
+1
Documentation/devicetree/bindings/clock/imx35-clock.txt
+1
Documentation/devicetree/bindings/clock/imx35-clock.txt
+2
-2
drivers/clk/imx/clk-imx35.c
+2
-2
drivers/clk/imx/clk-imx35.c
···
66
66
static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
67
67
68
68
enum mx35_clks {
69
-
ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
69
+
ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
70
70
arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
71
71
esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
72
72
spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
···
79
79
rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
80
80
ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
81
81
wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
82
-
gpu2d_gate, clk_max
82
+
gpu2d_gate, ckil, clk_max
83
83
};
84
84
85
85
static struct clk *clk[clk_max];
+1
-1
drivers/clk/imx/clk-imx6q.c
+1
-1
drivers/clk/imx/clk-imx6q.c
···
394
394
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
395
395
} else {
396
396
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
397
-
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);
397
+
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
398
398
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
399
399
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
400
400
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);