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ARM: dts: rockchip: Add pin names for rk3288-veyron jaq, mickey, speedy

This is like commit 0ca87bd5baa6 ("ARM: dts: rockchip: Add pin names
for rk3288-veyron-jerry") and commit ca3516b32cd9 ("ARM: dts:
rockchip: Add pin names for rk3288-veyron-minnie") but for 3 more
veyron boards.

A few notes:
- While there is most certainly duplication between all the veyron
boards, it still feels like it is sane to just have each board have
a full list of its pin names. The format of "gpio-line-names" does
not lend itself to one-off overriding and besides it seems sane to
more fully match schematic names. Also note that the extra
duplication here is only in source code and is unlikely to ever
change (since these boards are shipped). Duplication in the .dtb
files is unavoidable.
- veyron-jaq and veyron-mighty are very closely related and so I have
shared a single list for them both with comments on how they are
different. This is just a typo fix on one of the boards, a possible
missing signal on one of the boards (or perhaps I was never given
the most recent schematics?) and dealing with the fact that one of
the two boards has full sized SD.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Douglas Anderson and committed by
Heiko Stuebner d85b2ad3 9dbf05bd

+565
+207
arch/arm/boot/dts/rk3288-veyron-jaq.dts
··· 135 135 pinctrl-0 = <&vcc50_hdmi_en>; 136 136 }; 137 137 138 + &gpio0 { 139 + gpio-line-names = "PMIC_SLEEP_AP", 140 + "DDRIO_PWROFF", 141 + "DDRIO_RETEN", 142 + "TS3A227E_INT_L", 143 + "PMIC_INT_L", 144 + "PWR_KEY_L", 145 + "AP_LID_INT_L", 146 + "EC_IN_RW", 147 + 148 + "AC_PRESENT_AP", 149 + /* 150 + * RECOVERY_SW_L is Chrome OS ABI. Schematics call 151 + * it REC_MODE_L. 152 + */ 153 + "RECOVERY_SW_L", 154 + "OTP_OUT", 155 + "HOST1_PWR_EN", 156 + "USBOTG_PWREN_H", 157 + "AP_WARM_RESET_H", 158 + "nFALUT2", 159 + "I2C0_SDA_PMIC", 160 + 161 + "I2C0_SCL_PMIC", 162 + "SUSPEND_L", 163 + "USB_INT"; 164 + }; 165 + 166 + &gpio2 { 167 + gpio-line-names = "CONFIG0", 168 + "CONFIG1", 169 + "CONFIG2", 170 + "", 171 + "", 172 + "", 173 + "", 174 + "CONFIG3", 175 + 176 + "", 177 + "EMMC_RST_L", 178 + "", 179 + "", 180 + "BL_PWR_EN", 181 + "AVDD_1V8_DISP_EN"; 182 + }; 183 + 184 + &gpio3 { 185 + gpio-line-names = "FLASH0_D0", 186 + "FLASH0_D1", 187 + "FLASH0_D2", 188 + "FLASH0_D3", 189 + "FLASH0_D4", 190 + "FLASH0_D5", 191 + "FLASH0_D6", 192 + "FLASH0_D7", 193 + 194 + "", 195 + "", 196 + "", 197 + "", 198 + "", 199 + "", 200 + "", 201 + "", 202 + 203 + "FLASH0_CS2/EMMC_CMD", 204 + "", 205 + "FLASH0_DQS/EMMC_CLKO"; 206 + }; 207 + 208 + &gpio4 { 209 + gpio-line-names = "", 210 + "", 211 + "", 212 + "", 213 + "", 214 + "", 215 + "", 216 + "", 217 + 218 + "", 219 + "", 220 + "", 221 + "", 222 + "", 223 + "", 224 + "", 225 + "", 226 + 227 + "UART0_RXD", 228 + "UART0_TXD", 229 + "UART0_CTS", 230 + "UART0_RTS", 231 + "SDIO0_D0", 232 + "SDIO0_D1", 233 + "SDIO0_D2", 234 + "SDIO0_D3", 235 + 236 + "SDIO0_CMD", 237 + "SDIO0_CLK", 238 + "BT_DEV_WAKE", /* Maybe missing from mighty? */ 239 + "", 240 + "WIFI_ENABLE_H", 241 + "BT_ENABLE_L", 242 + "WIFI_HOST_WAKE", 243 + "BT_HOST_WAKE"; 244 + }; 245 + 246 + &gpio5 { 247 + gpio-line-names = "", 248 + "", 249 + "", 250 + "", 251 + "", 252 + "", 253 + "", 254 + "", 255 + 256 + "", 257 + "", 258 + "", 259 + "", 260 + "SPI0_CLK", 261 + "SPI0_CS0", 262 + "SPI0_TXD", 263 + "SPI0_RXD", 264 + 265 + "", 266 + "", 267 + "", 268 + "VCC50_HDMI_EN"; 269 + }; 270 + 271 + &gpio6 { 272 + gpio-line-names = "I2S0_SCLK", 273 + "I2S0_LRCK_RX", 274 + "I2S0_LRCK_TX", 275 + "I2S0_SDI", 276 + "I2S0_SDO0", 277 + "HP_DET_H", 278 + "ALS_INT", 279 + "INT_CODEC", 280 + 281 + "I2S0_CLK", 282 + "I2C2_SDA", 283 + "I2C2_SCL", 284 + "MICDET", 285 + "", 286 + "", 287 + "", 288 + "", 289 + 290 + "SDMMC_D0", 291 + "SDMMC_D1", 292 + "SDMMC_D2", 293 + "SDMMC_D3", 294 + "SDMMC_CLK", 295 + "SDMMC_CMD"; 296 + }; 297 + 298 + &gpio7 { 299 + gpio-line-names = "LCDC_BL", 300 + "PWM_LOG", 301 + "BL_EN", 302 + "TRACKPAD_INT", 303 + "TPM_INT_H", 304 + "SDMMC_DET_L", 305 + /* 306 + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 307 + * it FW_WP_AP. 308 + */ 309 + "AP_FLASH_WP_L", 310 + "EC_INT", 311 + 312 + "CPU_NMI", 313 + "DVSOK", 314 + "SDMMC_WP", /* mighty only */ 315 + "EDP_HPD", 316 + "DVS1", 317 + "nFALUT1", /* nFAULT1 on jaq */ 318 + "LCD_EN", 319 + "DVS2", 320 + 321 + "VCC5V_GOOD_H", 322 + "I2C4_SDA_TP", 323 + "I2C4_SCL_TP", 324 + "I2C5_SDA_HDMI", 325 + "I2C5_SCL_HDMI", 326 + "5V_DRV", 327 + "UART2_RXD", 328 + "UART2_TXD"; 329 + }; 330 + 331 + &gpio8 { 332 + gpio-line-names = "RAM_ID0", 333 + "RAM_ID1", 334 + "RAM_ID2", 335 + "RAM_ID3", 336 + "I2C1_SDA_TPM", 337 + "I2C1_SCL_TPM", 338 + "SPI2_CLK", 339 + "SPI2_CS0", 340 + 341 + "SPI2_RXD", 342 + "SPI2_TXD"; 343 + }; 344 + 138 345 &pinctrl { 139 346 backlight { 140 347 bl_pwr_en: bl_pwr_en {
+151
arch/arm/boot/dts/rk3288-veyron-mickey.dts
··· 252 252 }; 253 253 }; 254 254 255 + &gpio0 { 256 + gpio-line-names = "PMIC_SLEEP_AP", 257 + "", 258 + "", 259 + "", 260 + "PMIC_INT_L", 261 + "POWER_BUTTON_L", 262 + "", 263 + "", 264 + 265 + "", 266 + /* 267 + * RECOVERY_SW_L is Chrome OS ABI. Schematics call 268 + * it REC_MODE_L. 269 + */ 270 + "RECOVERY_SW_L", 271 + "OT_RESET", 272 + "", 273 + "", 274 + "AP_WARM_RESET_H", 275 + "", 276 + "I2C0_SDA_PMIC", 277 + 278 + "I2C0_SCL_PMIC", 279 + "", 280 + "nFALUT"; 281 + }; 282 + 283 + &gpio2 { 284 + gpio-line-names = "CONFIG0", 285 + "CONFIG1", 286 + "CONFIG2", 287 + "", 288 + "", 289 + "", 290 + "", 291 + "CONFIG3", 292 + 293 + "", 294 + "EMMC_RST_L"; 295 + }; 296 + 297 + &gpio3 { 298 + gpio-line-names = "FLASH0_D0", 299 + "FLASH0_D1", 300 + "FLASH0_D2", 301 + "FLASH0_D3", 302 + "FLASH0_D4", 303 + "FLASH0_D5", 304 + "FLASH0_D6", 305 + "FLASH0_D7", 306 + 307 + "", 308 + "", 309 + "", 310 + "", 311 + "", 312 + "", 313 + "", 314 + "", 315 + 316 + "FLASH0_CS2/EMMC_CMD", 317 + "", 318 + "FLASH0_DQS/EMMC_CLKO"; 319 + }; 320 + 321 + &gpio4 { 322 + gpio-line-names = "", 323 + "", 324 + "", 325 + "", 326 + "", 327 + "", 328 + "", 329 + "", 330 + 331 + "", 332 + "", 333 + "", 334 + "", 335 + "", 336 + "", 337 + "", 338 + "", 339 + 340 + "UART0_RXD", 341 + "UART0_TXD", 342 + "UART0_CTS_L", 343 + "UART0_RTS_L", 344 + "SDIO0_D0", 345 + "SDIO0_D1", 346 + "SDIO0_D2", 347 + "SDIO0_D3", 348 + 349 + "SDIO0_CMD", 350 + "SDIO0_CLK", 351 + "BT_DEV_WAKE", 352 + "", 353 + "WIFI_ENABLE_H", 354 + "BT_ENABLE_L", 355 + "WIFI_HOST_WAKE", 356 + "BT_HOST_WAKE"; 357 + }; 358 + 359 + &gpio7 { 360 + gpio-line-names = "", 361 + "PWM_LOG", 362 + "", 363 + "", 364 + "TPM_INT_H", 365 + "SDMMC_DET_L", 366 + /* 367 + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 368 + * it FW_WP_AP. 369 + */ 370 + "AP_FLASH_WP_L", 371 + "", 372 + 373 + "CPU_NMI", 374 + "DVSOK", 375 + "HDMI_WAKE", 376 + "POWER_HDMI_ON", 377 + "DVS1", 378 + "", 379 + "", 380 + "DVS2", 381 + 382 + "HDMI_CEC", 383 + "", 384 + "", 385 + "I2C5_SDA_HDMI", 386 + "I2C5_SCL_HDMI", 387 + "", 388 + "UART2_RXD", 389 + "UART2_TXD"; 390 + }; 391 + 392 + &gpio8 { 393 + gpio-line-names = "RAM_ID0", 394 + "RAM_ID1", 395 + "RAM_ID2", 396 + "RAM_ID3", 397 + "I2C1_SDA_TPM", 398 + "I2C1_SCL_TPM", 399 + "SPI2_CLK", 400 + "SPI2_CS0", 401 + 402 + "SPI2_RXD", 403 + "SPI2_TXD"; 404 + }; 405 + 255 406 &pinctrl { 256 407 hdmi { 257 408 power_hdmi_on: power-hdmi-on {
+207
arch/arm/boot/dts/rk3288-veyron-speedy.dts
··· 113 113 pinctrl-0 = <&vcc50_hdmi_en>; 114 114 }; 115 115 116 + &gpio0 { 117 + gpio-line-names = "PMIC_SLEEP_AP", 118 + "DDRIO_PWROFF", 119 + "DDRIO_RETEN", 120 + "TS3A227E_INT_L", 121 + "PMIC_INT_L", 122 + "PWR_KEY_L", 123 + "AP_LID_INT_L", 124 + "EC_IN_RW", 125 + 126 + "AC_PRESENT_AP", 127 + /* 128 + * RECOVERY_SW_L is Chrome OS ABI. Schematics call 129 + * it REC_MODE_L. 130 + */ 131 + "RECOVERY_SW_L", 132 + "OTP_OUT", 133 + "HOST1_PWR_EN", 134 + "USBOTG_PWREN_H", 135 + "AP_WARM_RESET_H", 136 + "nFALUT2", 137 + "I2C0_SDA_PMIC", 138 + 139 + "I2C0_SCL_PMIC", 140 + "SUSPEND_L", 141 + "USB_INT"; 142 + }; 143 + 144 + &gpio2 { 145 + gpio-line-names = "CONFIG0", 146 + "CONFIG1", 147 + "CONFIG2", 148 + "", 149 + "", 150 + "", 151 + "", 152 + "CONFIG3", 153 + 154 + "PWRLIMIT#_CPU", 155 + "EMMC_RST_L", 156 + "", 157 + "", 158 + "BL_PWR_EN", 159 + "AVDD_1V8_DISP_EN"; 160 + }; 161 + 162 + &gpio3 { 163 + gpio-line-names = "FLASH0_D0", 164 + "FLASH0_D1", 165 + "FLASH0_D2", 166 + "FLASH0_D3", 167 + "FLASH0_D4", 168 + "FLASH0_D5", 169 + "FLASH0_D6", 170 + "FLASH0_D7", 171 + 172 + "", 173 + "", 174 + "", 175 + "", 176 + "", 177 + "", 178 + "", 179 + "", 180 + 181 + "FLASH0_CS2/EMMC_CMD", 182 + "", 183 + "FLASH0_DQS/EMMC_CLKO"; 184 + }; 185 + 186 + &gpio4 { 187 + gpio-line-names = "", 188 + "", 189 + "", 190 + "", 191 + "", 192 + "", 193 + "", 194 + "", 195 + 196 + "", 197 + "", 198 + "", 199 + "", 200 + "", 201 + "", 202 + "", 203 + "", 204 + 205 + "UART0_RXD", 206 + "UART0_TXD", 207 + "UART0_CTS", 208 + "UART0_RTS", 209 + "SDIO0_D0", 210 + "SDIO0_D1", 211 + "SDIO0_D2", 212 + "SDIO0_D3", 213 + 214 + "SDIO0_CMD", 215 + "SDIO0_CLK", 216 + "BT_DEV_WAKE", 217 + "", 218 + "WIFI_ENABLE_H", 219 + "BT_ENABLE_L", 220 + "WIFI_HOST_WAKE", 221 + "BT_HOST_WAKE"; 222 + }; 223 + 224 + &gpio5 { 225 + gpio-line-names = "", 226 + "", 227 + "", 228 + "", 229 + "", 230 + "", 231 + "", 232 + "", 233 + 234 + "", 235 + "", 236 + "", 237 + "", 238 + "SPI0_CLK", 239 + "SPI0_CS0", 240 + "SPI0_TXD", 241 + "SPI0_RXD", 242 + 243 + "", 244 + "", 245 + "", 246 + "VCC50_HDMI_EN"; 247 + }; 248 + 249 + &gpio6 { 250 + gpio-line-names = "I2S0_SCLK", 251 + "I2S0_LRCK_RX", 252 + "I2S0_LRCK_TX", 253 + "I2S0_SDI", 254 + "I2S0_SDO0", 255 + "HP_DET_H", 256 + "ALS_INT", /* not connected */ 257 + "INT_CODEC", 258 + 259 + "I2S0_CLK", 260 + "I2C2_SDA", 261 + "I2C2_SCL", 262 + "MICDET", 263 + "", 264 + "", 265 + "", 266 + "", 267 + 268 + "SDMMC_D0", 269 + "SDMMC_D1", 270 + "SDMMC_D2", 271 + "SDMMC_D3", 272 + "SDMMC_CLK", 273 + "SDMMC_CMD"; 274 + }; 275 + 276 + &gpio7 { 277 + gpio-line-names = "LCDC_BL", 278 + "PWM_LOG", 279 + "BL_EN", 280 + "TRACKPAD_INT", 281 + "TPM_INT_H", 282 + "SDMMC_DET_L", 283 + /* 284 + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 285 + * it FW_WP_AP. 286 + */ 287 + "AP_FLASH_WP_L", 288 + "EC_INT", 289 + 290 + "CPU_NMI", 291 + "DVS_OK", 292 + "", 293 + "EDP_HOTPLUG", 294 + "DVS1", 295 + "nFALUT1", 296 + "LCD_EN", 297 + "DVS2", 298 + 299 + "VCC5V_GOOD_H", 300 + "I2C4_SDA_TP", 301 + "I2C4_SCL_TP", 302 + "I2C5_SDA_HDMI", 303 + "I2C5_SCL_HDMI", 304 + "5V_DRV", 305 + "UART2_RXD", 306 + "UART2_TXD"; 307 + }; 308 + 309 + &gpio8 { 310 + gpio-line-names = "RAM_ID0", 311 + "RAM_ID1", 312 + "RAM_ID2", 313 + "RAM_ID3", 314 + "I2C1_SDA_TPM", 315 + "I2C1_SCL_TPM", 316 + "SPI2_CLK", 317 + "SPI2_CS0", 318 + 319 + "SPI2_RXD", 320 + "SPI2_TXD"; 321 + }; 322 + 116 323 &pinctrl { 117 324 backlight { 118 325 bl_pwr_en: bl_pwr_en {