drm/amd: Add dce-12.1 gpio aux registers (v2)

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Updating dce12 register headers by adding dc registers
required for potential DP LTTPR support.

v2: fix mode change

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Roman Li and committed by

Alex Deucher 7 years ago d82420b5 c6034aa2

+164

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

dce

dce_12_0_offset.h

dce_12_0_sh_mask.h

+12

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

··· 2095 2095 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 2096 2096 #define mmDC_GPIO_RXEN 0x212f 2097 2097 #define mmDC_GPIO_RXEN_BASE_IDX 2 2098 + #define mmDC_GPIO_AUX_CTRL_3 0x2130 2099 + #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 2100 + #define mmDC_GPIO_AUX_CTRL_4 0x2131 2101 + #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 2102 + #define mmDC_GPIO_AUX_CTRL_5 0x2132 2103 + #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 2104 + #define mmAUXI2C_PAD_ALL_PWR_OK 0x2133 2105 + #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 2106 + #define mmDC_GPIO_PULLUPEN 0x2134 2107 + #define mmDC_GPIO_PULLUPEN_BASE_IDX 2 2108 + #define mmDC_GPIO_AUX_CTRL_6 0x2135 2109 + #define mmDC_GPIO_AUX_CTRL_6_BASE_IDX 2 2098 2110 #define mmBPHYC_DAC_MACRO_CNTL 0x2136 2099 2111 #define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2 2100 2112 #define mmDAC_MACRO_CNTL_RESERVED0 0x2136

+152

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h

··· 10971 10971 #define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L 10972 10972 #define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L 10973 10973 #define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L 10974 + //DC_GPIO_AUX_CTRL_3 10975 + #define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 10976 + #define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 10977 + #define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 10978 + #define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 10979 + #define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 10980 + #define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 10981 + #define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 10982 + #define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 10983 + #define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa 10984 + #define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb 10985 + #define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc 10986 + #define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd 10987 + #define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 10988 + #define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 10989 + #define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 10990 + #define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 10991 + #define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 10992 + #define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a 10993 + #define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L 10994 + #define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L 10995 + #define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L 10996 + #define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L 10997 + #define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L 10998 + #define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L 10999 + #define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L 11000 + #define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L 11001 + #define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L 11002 + #define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L 11003 + #define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L 11004 + #define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L 11005 + #define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L 11006 + #define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L 11007 + #define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L 11008 + #define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L 11009 + #define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L 11010 + #define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L 11011 + //DC_GPIO_AUX_CTRL_4 11012 + #define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 11013 + #define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 11014 + #define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 11015 + #define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc 11016 + #define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 11017 + #define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 11018 + #define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL 11019 + #define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L 11020 + #define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L 11021 + #define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L 11022 + #define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L 11023 + #define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L 11024 + //DC_GPIO_AUX_CTRL_5 11025 + #define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 11026 + #define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 11027 + #define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 11028 + #define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 11029 + #define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 11030 + #define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa 11031 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc 11032 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd 11033 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe 11034 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf 11035 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 11036 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 11037 + #define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 11038 + #define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 11039 + #define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 11040 + #define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 11041 + #define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 11042 + #define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 11043 + #define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 11044 + #define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 11045 + #define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a 11046 + #define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b 11047 + #define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c 11048 + #define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d 11049 + #define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L 11050 + #define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL 11051 + #define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L 11052 + #define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L 11053 + #define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L 11054 + #define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L 11055 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L 11056 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L 11057 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L 11058 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L 11059 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L 11060 + #define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L 11061 + #define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L 11062 + #define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L 11063 + #define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L 11064 + #define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L 11065 + #define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L 11066 + #define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L 11067 + #define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L 11068 + #define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L 11069 + #define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L 11070 + #define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L 11071 + #define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L 11072 + #define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L 11073 + //AUXI2C_PAD_ALL_PWR_OK 11074 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 11075 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 11076 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 11077 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 11078 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 11079 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 11080 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L 11081 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L 11082 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L 11083 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L 11084 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L 11085 + #define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L 11086 + //DC_GPIO_PULLUPEN 11087 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 11088 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 11089 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 11090 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 11091 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 11092 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 11093 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 11094 + #define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 11095 + #define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 11096 + #define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe 11097 + #define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 11098 + #define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 11099 + #define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 11100 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L 11101 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L 11102 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L 11103 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L 11104 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L 11105 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L 11106 + #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L 11107 + #define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L 11108 + #define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L 11109 + #define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L 11110 + #define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L 11111 + #define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L 11112 + #define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L 11113 + //DC_GPIO_AUX_CTRL_6 11114 + #define DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL__SHIFT 0x0 11115 + #define DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL__SHIFT 0x2 11116 + #define DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL__SHIFT 0x4 11117 + #define DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL__SHIFT 0x6 11118 + #define DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL__SHIFT 0x8 11119 + #define DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL__SHIFT 0xa 11120 + #define DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL_MASK 0x00000003L 11121 + #define DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL_MASK 0x0000000CL 11122 + #define DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL_MASK 0x00000030L 11123 + #define DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL_MASK 0x000000C0L 11124 + #define DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL_MASK 0x00000300L 11125 + #define DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL_MASK 0x00000C00L 10974 11126 //BPHYC_DAC_MACRO_CNTL 10975 11127 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 10976 11128 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8