Merge tag 'asoc-fix-v6.5-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

+69 -69

sound/soc/codecs/cs43130.h

··· 381 381 382 382 /* frm_size = 16 */ 383 383 static const struct cs43130_clk_gen cs43130_16_clk_gen[] = { 384 - { 22579200, 32000, .v = { 441, 10, }, }, 385 - { 22579200, 44100, .v = { 32, 1, }, }, 386 - { 22579200, 48000, .v = { 147, 5, }, }, 387 - { 22579200, 88200, .v = { 16, 1, }, }, 388 - { 22579200, 96000, .v = { 147, 10, }, }, 389 - { 22579200, 176400, .v = { 8, 1, }, }, 390 - { 22579200, 192000, .v = { 147, 20, }, }, 391 - { 22579200, 352800, .v = { 4, 1, }, }, 392 - { 22579200, 384000, .v = { 147, 40, }, }, 393 - { 24576000, 32000, .v = { 48, 1, }, }, 394 - { 24576000, 44100, .v = { 5120, 147, }, }, 395 - { 24576000, 48000, .v = { 32, 1, }, }, 396 - { 24576000, 88200, .v = { 2560, 147, }, }, 397 - { 24576000, 96000, .v = { 16, 1, }, }, 398 - { 24576000, 176400, .v = { 1280, 147, }, }, 399 - { 24576000, 192000, .v = { 8, 1, }, }, 400 - { 24576000, 352800, .v = { 640, 147, }, }, 401 - { 24576000, 384000, .v = { 4, 1, }, }, 384 + { 22579200, 32000, .v = { 10, 441, }, }, 385 + { 22579200, 44100, .v = { 1, 32, }, }, 386 + { 22579200, 48000, .v = { 5, 147, }, }, 387 + { 22579200, 88200, .v = { 1, 16, }, }, 388 + { 22579200, 96000, .v = { 10, 147, }, }, 389 + { 22579200, 176400, .v = { 1, 8, }, }, 390 + { 22579200, 192000, .v = { 20, 147, }, }, 391 + { 22579200, 352800, .v = { 1, 4, }, }, 392 + { 22579200, 384000, .v = { 40, 147, }, }, 393 + { 24576000, 32000, .v = { 1, 48, }, }, 394 + { 24576000, 44100, .v = { 147, 5120, }, }, 395 + { 24576000, 48000, .v = { 1, 32, }, }, 396 + { 24576000, 88200, .v = { 147, 2560, }, }, 397 + { 24576000, 96000, .v = { 1, 16, }, }, 398 + { 24576000, 176400, .v = { 147, 1280, }, }, 399 + { 24576000, 192000, .v = { 1, 8, }, }, 400 + { 24576000, 352800, .v = { 147, 640, }, }, 401 + { 24576000, 384000, .v = { 1, 4, }, }, 402 402 }; 403 403 404 404 /* frm_size = 32 */ 405 405 static const struct cs43130_clk_gen cs43130_32_clk_gen[] = { 406 - { 22579200, 32000, .v = { 441, 20, }, }, 407 - { 22579200, 44100, .v = { 16, 1, }, }, 408 - { 22579200, 48000, .v = { 147, 10, }, }, 409 - { 22579200, 88200, .v = { 8, 1, }, }, 410 - { 22579200, 96000, .v = { 147, 20, }, }, 411 - { 22579200, 176400, .v = { 4, 1, }, }, 412 - { 22579200, 192000, .v = { 147, 40, }, }, 413 - { 22579200, 352800, .v = { 2, 1, }, }, 414 - { 22579200, 384000, .v = { 147, 80, }, }, 415 - { 24576000, 32000, .v = { 24, 1, }, }, 416 - { 24576000, 44100, .v = { 2560, 147, }, }, 417 - { 24576000, 48000, .v = { 16, 1, }, }, 418 - { 24576000, 88200, .v = { 1280, 147, }, }, 419 - { 24576000, 96000, .v = { 8, 1, }, }, 420 - { 24576000, 176400, .v = { 640, 147, }, }, 421 - { 24576000, 192000, .v = { 4, 1, }, }, 422 - { 24576000, 352800, .v = { 320, 147, }, }, 423 - { 24576000, 384000, .v = { 2, 1, }, }, 406 + { 22579200, 32000, .v = { 20, 441, }, }, 407 + { 22579200, 44100, .v = { 1, 16, }, }, 408 + { 22579200, 48000, .v = { 10, 147, }, }, 409 + { 22579200, 88200, .v = { 1, 8, }, }, 410 + { 22579200, 96000, .v = { 20, 147, }, }, 411 + { 22579200, 176400, .v = { 1, 4, }, }, 412 + { 22579200, 192000, .v = { 40, 147, }, }, 413 + { 22579200, 352800, .v = { 1, 2, }, }, 414 + { 22579200, 384000, .v = { 80, 147, }, }, 415 + { 24576000, 32000, .v = { 1, 24, }, }, 416 + { 24576000, 44100, .v = { 147, 2560, }, }, 417 + { 24576000, 48000, .v = { 1, 16, }, }, 418 + { 24576000, 88200, .v = { 147, 1280, }, }, 419 + { 24576000, 96000, .v = { 1, 8, }, }, 420 + { 24576000, 176400, .v = { 147, 640, }, }, 421 + { 24576000, 192000, .v = { 1, 4, }, }, 422 + { 24576000, 352800, .v = { 147, 320, }, }, 423 + { 24576000, 384000, .v = { 1, 2, }, }, 424 424 }; 425 425 426 426 /* frm_size = 48 */ 427 427 static const struct cs43130_clk_gen cs43130_48_clk_gen[] = { 428 - { 22579200, 32000, .v = { 147, 100, }, }, 429 - { 22579200, 44100, .v = { 32, 3, }, }, 430 - { 22579200, 48000, .v = { 49, 5, }, }, 431 - { 22579200, 88200, .v = { 16, 3, }, }, 432 - { 22579200, 96000, .v = { 49, 10, }, }, 433 - { 22579200, 176400, .v = { 8, 3, }, }, 434 - { 22579200, 192000, .v = { 49, 20, }, }, 435 - { 22579200, 352800, .v = { 4, 3, }, }, 436 - { 22579200, 384000, .v = { 49, 40, }, }, 437 - { 24576000, 32000, .v = { 16, 1, }, }, 438 - { 24576000, 44100, .v = { 5120, 441, }, }, 439 - { 24576000, 48000, .v = { 32, 3, }, }, 440 - { 24576000, 88200, .v = { 2560, 441, }, }, 441 - { 24576000, 96000, .v = { 16, 3, }, }, 442 - { 24576000, 176400, .v = { 1280, 441, }, }, 443 - { 24576000, 192000, .v = { 8, 3, }, }, 444 - { 24576000, 352800, .v = { 640, 441, }, }, 445 - { 24576000, 384000, .v = { 4, 3, }, }, 428 + { 22579200, 32000, .v = { 100, 147, }, }, 429 + { 22579200, 44100, .v = { 3, 32, }, }, 430 + { 22579200, 48000, .v = { 5, 49, }, }, 431 + { 22579200, 88200, .v = { 3, 16, }, }, 432 + { 22579200, 96000, .v = { 10, 49, }, }, 433 + { 22579200, 176400, .v = { 3, 8, }, }, 434 + { 22579200, 192000, .v = { 20, 49, }, }, 435 + { 22579200, 352800, .v = { 3, 4, }, }, 436 + { 22579200, 384000, .v = { 40, 49, }, }, 437 + { 24576000, 32000, .v = { 1, 16, }, }, 438 + { 24576000, 44100, .v = { 441, 5120, }, }, 439 + { 24576000, 48000, .v = { 3, 32, }, }, 440 + { 24576000, 88200, .v = { 441, 2560, }, }, 441 + { 24576000, 96000, .v = { 3, 16, }, }, 442 + { 24576000, 176400, .v = { 441, 1280, }, }, 443 + { 24576000, 192000, .v = { 3, 8, }, }, 444 + { 24576000, 352800, .v = { 441, 640, }, }, 445 + { 24576000, 384000, .v = { 3, 4, }, }, 446 446 }; 447 447 448 448 /* frm_size = 64 */ 449 449 static const struct cs43130_clk_gen cs43130_64_clk_gen[] = { 450 - { 22579200, 32000, .v = { 441, 40, }, }, 451 - { 22579200, 44100, .v = { 8, 1, }, }, 452 - { 22579200, 48000, .v = { 147, 20, }, }, 453 - { 22579200, 88200, .v = { 4, 1, }, }, 454 - { 22579200, 96000, .v = { 147, 40, }, }, 455 - { 22579200, 176400, .v = { 2, 1, }, }, 456 - { 22579200, 192000, .v = { 147, 80, }, }, 450 + { 22579200, 32000, .v = { 40, 441, }, }, 451 + { 22579200, 44100, .v = { 1, 8, }, }, 452 + { 22579200, 48000, .v = { 20, 147, }, }, 453 + { 22579200, 88200, .v = { 1, 4, }, }, 454 + { 22579200, 96000, .v = { 40, 147, }, }, 455 + { 22579200, 176400, .v = { 1, 2, }, }, 456 + { 22579200, 192000, .v = { 80, 147, }, }, 457 457 { 22579200, 352800, .v = { 1, 1, }, }, 458 - { 24576000, 32000, .v = { 12, 1, }, }, 459 - { 24576000, 44100, .v = { 1280, 147, }, }, 460 - { 24576000, 48000, .v = { 8, 1, }, }, 461 - { 24576000, 88200, .v = { 640, 147, }, }, 462 - { 24576000, 96000, .v = { 4, 1, }, }, 463 - { 24576000, 176400, .v = { 320, 147, }, }, 464 - { 24576000, 192000, .v = { 2, 1, }, }, 465 - { 24576000, 352800, .v = { 160, 147, }, }, 458 + { 24576000, 32000, .v = { 1, 12, }, }, 459 + { 24576000, 44100, .v = { 147, 1280, }, }, 460 + { 24576000, 48000, .v = { 1, 8, }, }, 461 + { 24576000, 88200, .v = { 147, 640, }, }, 462 + { 24576000, 96000, .v = { 1, 4, }, }, 463 + { 24576000, 176400, .v = { 147, 320, }, }, 464 + { 24576000, 192000, .v = { 1, 2, }, }, 465 + { 24576000, 352800, .v = { 147, 160, }, }, 466 466 { 24576000, 384000, .v = { 1, 1, }, }, 467 467 }; 468 468

+1

sound/soc/soc-compress.c

··· 193 193 snd_soc_dai_compr_shutdown(cpu_dai, cstream, 1); 194 194 out: 195 195 dpcm_path_put(&list); 196 + snd_soc_dpcm_mutex_unlock(fe); 196 197 be_err: 197 198 fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_NO; 198 199 snd_soc_card_mutex_unlock(fe->card);

+30 -1

sound/soc/tegra/tegra210_sfc.c

··· 2 2 // 3 3 // tegra210_sfc.c - Tegra210 SFC driver 4 4 // 5 - // Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. 5 + // Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6 6 7 7 #include <linux/clk.h> 8 8 #include <linux/device.h> ··· 42 42 32000, 43 43 44100, 44 44 48000, 45 + 64000, 45 46 88200, 46 47 96000, 47 48 176400, ··· 2858 2857 coef_8to32, 2859 2858 coef_8to44, 2860 2859 coef_8to48, 2860 + UNSUPP_CONV, 2861 2861 coef_8to88, 2862 2862 coef_8to96, 2863 2863 UNSUPP_CONV, ··· 2874 2872 coef_11to32, 2875 2873 coef_11to44, 2876 2874 coef_11to48, 2875 + UNSUPP_CONV, 2877 2876 coef_11to88, 2878 2877 coef_11to96, 2879 2878 UNSUPP_CONV, ··· 2890 2887 coef_16to32, 2891 2888 coef_16to44, 2892 2889 coef_16to48, 2890 + UNSUPP_CONV, 2893 2891 coef_16to88, 2894 2892 coef_16to96, 2895 2893 coef_16to176, ··· 2906 2902 coef_22to32, 2907 2903 coef_22to44, 2908 2904 coef_22to48, 2905 + UNSUPP_CONV, 2909 2906 coef_22to88, 2910 2907 coef_22to96, 2911 2908 coef_22to176, ··· 2922 2917 coef_24to32, 2923 2918 coef_24to44, 2924 2919 coef_24to48, 2920 + UNSUPP_CONV, 2925 2921 coef_24to88, 2926 2922 coef_24to96, 2927 2923 coef_24to176, ··· 2938 2932 BYPASS_CONV, 2939 2933 coef_32to44, 2940 2934 coef_32to48, 2935 + UNSUPP_CONV, 2941 2936 coef_32to88, 2942 2937 coef_32to96, 2943 2938 coef_32to176, ··· 2954 2947 coef_44to32, 2955 2948 BYPASS_CONV, 2956 2949 coef_44to48, 2950 + UNSUPP_CONV, 2957 2951 coef_44to88, 2958 2952 coef_44to96, 2959 2953 coef_44to176, ··· 2970 2962 coef_48to32, 2971 2963 coef_48to44, 2972 2964 BYPASS_CONV, 2965 + UNSUPP_CONV, 2973 2966 coef_48to88, 2974 2967 coef_48to96, 2975 2968 coef_48to176, 2976 2969 coef_48to192, 2970 + }, 2971 + /* Convertions from 64 kHz */ 2972 + { 2973 + UNSUPP_CONV, 2974 + UNSUPP_CONV, 2975 + UNSUPP_CONV, 2976 + UNSUPP_CONV, 2977 + UNSUPP_CONV, 2978 + UNSUPP_CONV, 2979 + UNSUPP_CONV, 2980 + UNSUPP_CONV, 2981 + UNSUPP_CONV, 2982 + UNSUPP_CONV, 2983 + UNSUPP_CONV, 2984 + UNSUPP_CONV, 2985 + UNSUPP_CONV, 2977 2986 }, 2978 2987 /* Convertions from 88.2 kHz */ 2979 2988 { ··· 3002 2977 coef_88to32, 3003 2978 coef_88to44, 3004 2979 coef_88to48, 2980 + UNSUPP_CONV, 3005 2981 BYPASS_CONV, 3006 2982 coef_88to96, 3007 2983 coef_88to176, ··· 3017 2991 coef_96to32, 3018 2992 coef_96to44, 3019 2993 coef_96to48, 2994 + UNSUPP_CONV, 3020 2995 coef_96to88, 3021 2996 BYPASS_CONV, 3022 2997 coef_96to176, ··· 3033 3006 coef_176to32, 3034 3007 coef_176to44, 3035 3008 coef_176to48, 3009 + UNSUPP_CONV, 3036 3010 coef_176to88, 3037 3011 coef_176to96, 3038 3012 BYPASS_CONV, ··· 3049 3021 coef_192to32, 3050 3022 coef_192to44, 3051 3023 coef_192to48, 3024 + UNSUPP_CONV, 3052 3025 coef_192to88, 3053 3026 coef_192to96, 3054 3027 coef_192to176,

+2 -2

sound/soc/tegra/tegra210_sfc.h

··· 2 2 /* 3 3 * tegra210_sfc.h - Definitions for Tegra210 SFC driver 4 4 * 5 - * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved. 5 + * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. 6 6 * 7 7 */ 8 8 ··· 47 47 #define TEGRA210_SFC_EN_SHIFT 0 48 48 #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT) 49 49 50 - #define TEGRA210_SFC_NUM_RATES 12 50 + #define TEGRA210_SFC_NUM_RATES 13 51 51 52 52 /* Fields in TEGRA210_SFC_COEF_RAM */ 53 53 #define TEGRA210_SFC_COEF_RAM_EN BIT(0)