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kernel
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linux
interconnect: qcom: Add EPSS L3 support on SM8250
Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SM8250 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200801123049.32398-6-sibis@codeaurora.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
authored by
Sibi Sankar
and committed by
Georgi Djakov
d7e19be6
c4877059
+25
+23
drivers/interconnect/qcom/osm-l3.c
+23
drivers/interconnect/qcom/osm-l3.c
···
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#include "sc7180.h"
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#include "sdm845.h"
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#include "sm8150.h"
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#include "sm8250.h"
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
···
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#define OSM_LUT_ROW_SIZE 32
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#define OSM_REG_FREQ_LUT 0x110
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#define OSM_REG_PERF_STATE 0x920
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/* EPSS Register offsets */
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#define EPSS_LUT_ROW_SIZE 4
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#define EPSS_REG_FREQ_LUT 0x100
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#define EPSS_REG_PERF_STATE 0x320
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#define OSM_L3_MAX_LINKS 1
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···
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.lut_row_size = OSM_LUT_ROW_SIZE,
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.reg_freq_lut = OSM_REG_FREQ_LUT,
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.reg_perf_state = OSM_REG_PERF_STATE,
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};
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DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
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DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
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static struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
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[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
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[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
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};
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static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
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.nodes = sm8250_epss_l3_nodes,
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.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
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.lut_row_size = EPSS_LUT_ROW_SIZE,
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.reg_freq_lut = EPSS_REG_FREQ_LUT,
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.reg_perf_state = EPSS_REG_PERF_STATE,
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};
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static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
···
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{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
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{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
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{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
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{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
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{ }
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};
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MODULE_DEVICE_TABLE(of, osm_l3_of_match);