tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung
Samsung clock patches for 3.17
1) non-critical fixes (without need to push to stable):
d5e136a clk: samsung: Register clk provider only after registering its all clocks
305cfab clk: samsung: Make of_device_id array const
e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend
f65d518 clk: samsung: trivial: Correct typo in author's name
2) Exynos CLKOUT driver:
800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data
3) Clock hierarchy extensions:
17d3f1d clk: exynos4: Add PPMU IP block source clocks.
ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data
4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:
42773b2 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
+599
-19
+30
Documentation/devicetree/bindings/arm/samsung/pmu.txt
+30
Documentation/devicetree/bindings/arm/samsung/pmu.txt
···
12
12
13
13
- reg : offset and length of the register set.
14
14
15
+
- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
16
+
The single specifier cell is used as index to list of clocks
17
+
provided by PMU, which is currently:
18
+
0 : SoC clock output (CLKOUT pin)
19
+
20
+
- clock-names : list of clock names for particular CLKOUT mux inputs in
21
+
following format:
22
+
"clkoutN", where N is a decimal number corresponding to
23
+
CLKOUT mux control bits value for given input, e.g.
24
+
"clkout0", "clkout7", "clkout15".
25
+
26
+
- clocks : list of phandles and specifiers to all input clocks listed in
27
+
clock-names property.
28
+
15
29
Example :
16
30
pmu_system_controller: system-controller@10040000 {
17
31
compatible = "samsung,exynos5250-pmu", "syscon";
18
32
reg = <0x10040000 0x5000>;
33
+
#clock-cells = <1>;
34
+
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
35
+
"clkout4", "clkout8", "clkout9";
36
+
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
37
+
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
38
+
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
39
+
<&clock CLK_XUSBXTI>;
40
+
};
41
+
42
+
Example of clock consumer :
43
+
44
+
usb3503: usb3503@08 {
45
+
/* ... */
46
+
clock-names = "refclk";
47
+
clocks = <&pmu_system_controller 0>;
48
+
/* ... */
19
49
};
+10
arch/arm/boot/dts/exynos4210.dtsi
+10
arch/arm/boot/dts/exynos4210.dtsi
···
31
31
pinctrl2 = &pinctrl_2;
32
32
};
33
33
34
+
pmu_system_controller: system-controller@10020000 {
35
+
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
36
+
"clkout4", "clkout8", "clkout9";
37
+
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
38
+
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
39
+
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
40
+
<&clock CLK_XUSBXTI>;
41
+
#clock-cells = <1>;
42
+
};
43
+
34
44
sysram@02020000 {
35
45
compatible = "mmio-sram";
36
46
reg = <0x02020000 0x20000>;
+7
arch/arm/boot/dts/exynos4x12.dtsi
+7
arch/arm/boot/dts/exynos4x12.dtsi
···
139
139
140
140
pmu_system_controller: system-controller@10020000 {
141
141
compatible = "samsung,exynos4212-pmu", "syscon";
142
+
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
143
+
"clkout4", "clkout8", "clkout9";
144
+
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
145
+
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
146
+
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
147
+
<&clock CLK_XUSBXTI>;
148
+
#clock-cells = <1>;
142
149
};
143
150
144
151
g2d@10800000 {
+3
arch/arm/boot/dts/exynos5250.dtsi
+3
arch/arm/boot/dts/exynos5250.dtsi
···
191
191
pmu_system_controller: system-controller@10040000 {
192
192
compatible = "samsung,exynos5250-pmu", "syscon";
193
193
reg = <0x10040000 0x5000>;
194
+
clock-names = "clkout16";
195
+
clocks = <&clock CLK_FIN_PLL>;
196
+
#clock-cells = <1>;
194
197
};
195
198
196
199
sysreg_system_controller: syscon@10050000 {
+3
arch/arm/boot/dts/exynos5420.dtsi
+3
arch/arm/boot/dts/exynos5420.dtsi
···
724
724
pmu_system_controller: system-controller@10040000 {
725
725
compatible = "samsung,exynos5420-pmu", "syscon";
726
726
reg = <0x10040000 0x5000>;
727
+
clock-names = "clkout16";
728
+
clocks = <&clock CLK_FIN_PLL>;
729
+
#clock-cells = <1>;
727
730
};
728
731
729
732
sysreg_system_controller: syscon@10050000 {
+1
drivers/clk/samsung/Makefile
+1
drivers/clk/samsung/Makefile
···
11
11
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
12
12
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
13
13
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
14
+
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
14
15
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
15
16
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
16
17
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
+153
drivers/clk/samsung/clk-exynos-clkout.c
+153
drivers/clk/samsung/clk-exynos-clkout.c
···
1
+
/*
2
+
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
3
+
* Author: Tomasz Figa <t.figa@samsung.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* Clock driver for Exynos clock output
10
+
*/
11
+
12
+
#include <linux/clk.h>
13
+
#include <linux/clkdev.h>
14
+
#include <linux/clk-provider.h>
15
+
#include <linux/of.h>
16
+
#include <linux/of_address.h>
17
+
#include <linux/syscore_ops.h>
18
+
19
+
#define EXYNOS_CLKOUT_NR_CLKS 1
20
+
#define EXYNOS_CLKOUT_PARENTS 32
21
+
22
+
#define EXYNOS_PMU_DEBUG_REG 0xa00
23
+
#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
24
+
#define EXYNOS_CLKOUT_MUX_SHIFT 8
25
+
#define EXYNOS4_CLKOUT_MUX_MASK 0xf
26
+
#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
27
+
28
+
struct exynos_clkout {
29
+
struct clk_gate gate;
30
+
struct clk_mux mux;
31
+
spinlock_t slock;
32
+
struct clk_onecell_data data;
33
+
struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
34
+
void __iomem *reg;
35
+
u32 pmu_debug_save;
36
+
};
37
+
38
+
static struct exynos_clkout *clkout;
39
+
40
+
static int exynos_clkout_suspend(void)
41
+
{
42
+
clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
43
+
44
+
return 0;
45
+
}
46
+
47
+
static void exynos_clkout_resume(void)
48
+
{
49
+
writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
50
+
}
51
+
52
+
static struct syscore_ops exynos_clkout_syscore_ops = {
53
+
.suspend = exynos_clkout_suspend,
54
+
.resume = exynos_clkout_resume,
55
+
};
56
+
57
+
static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
58
+
{
59
+
const char *parent_names[EXYNOS_CLKOUT_PARENTS];
60
+
struct clk *parents[EXYNOS_CLKOUT_PARENTS];
61
+
int parent_count;
62
+
int ret;
63
+
int i;
64
+
65
+
clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
66
+
if (!clkout)
67
+
return;
68
+
69
+
spin_lock_init(&clkout->slock);
70
+
71
+
parent_count = 0;
72
+
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
73
+
char name[] = "clkoutXX";
74
+
75
+
snprintf(name, sizeof(name), "clkout%d", i);
76
+
parents[i] = of_clk_get_by_name(node, name);
77
+
if (IS_ERR(parents[i])) {
78
+
parent_names[i] = "none";
79
+
continue;
80
+
}
81
+
82
+
parent_names[i] = __clk_get_name(parents[i]);
83
+
parent_count = i + 1;
84
+
}
85
+
86
+
if (!parent_count)
87
+
goto free_clkout;
88
+
89
+
clkout->reg = of_iomap(node, 0);
90
+
if (!clkout->reg)
91
+
goto clks_put;
92
+
93
+
clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
94
+
clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
95
+
clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
96
+
clkout->gate.lock = &clkout->slock;
97
+
98
+
clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
99
+
clkout->mux.mask = mux_mask;
100
+
clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
101
+
clkout->mux.lock = &clkout->slock;
102
+
103
+
clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
104
+
parent_names, parent_count, &clkout->mux.hw,
105
+
&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
106
+
&clk_gate_ops, CLK_SET_RATE_PARENT
107
+
| CLK_SET_RATE_NO_REPARENT);
108
+
if (IS_ERR(clkout->clk_table[0]))
109
+
goto err_unmap;
110
+
111
+
clkout->data.clks = clkout->clk_table;
112
+
clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
113
+
ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
114
+
if (ret)
115
+
goto err_clk_unreg;
116
+
117
+
register_syscore_ops(&exynos_clkout_syscore_ops);
118
+
119
+
return;
120
+
121
+
err_clk_unreg:
122
+
clk_unregister(clkout->clk_table[0]);
123
+
err_unmap:
124
+
iounmap(clkout->reg);
125
+
clks_put:
126
+
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
127
+
if (!IS_ERR(parents[i]))
128
+
clk_put(parents[i]);
129
+
free_clkout:
130
+
kfree(clkout);
131
+
132
+
pr_err("%s: failed to register clkout clock\n", __func__);
133
+
}
134
+
135
+
static void __init exynos4_clkout_init(struct device_node *node)
136
+
{
137
+
exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
138
+
}
139
+
CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu",
140
+
exynos4_clkout_init);
141
+
CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
142
+
exynos4_clkout_init);
143
+
CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
144
+
exynos4_clkout_init);
145
+
146
+
static void __init exynos5_clkout_init(struct device_node *node)
147
+
{
148
+
exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
149
+
}
150
+
CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
151
+
exynos5_clkout_init);
152
+
CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
153
+
exynos5_clkout_init);
+43
drivers/clk/samsung/clk-exynos3250.c
+43
drivers/clk/samsung/clk-exynos3250.c
···
87
87
#define SRC_CPU 0x14200
88
88
#define DIV_CPU0 0x14500
89
89
#define DIV_CPU1 0x14504
90
+
#define PWR_CTRL1 0x15020
91
+
#define PWR_CTRL2 0x15024
92
+
93
+
/* Below definitions are used for PWR_CTRL settings */
94
+
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
95
+
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
96
+
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
97
+
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
98
+
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
99
+
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
100
+
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
101
+
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
102
+
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
103
+
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
104
+
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105
+
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
90
106
91
107
/* list of PLLs to be registered */
92
108
enum exynos3250_plls {
···
184
168
SRC_CPU,
185
169
DIV_CPU0,
186
170
DIV_CPU1,
171
+
PWR_CTRL1,
172
+
PWR_CTRL2,
187
173
};
188
174
189
175
static int exynos3250_clk_suspend(void)
···
766
748
UPLL_LOCK, UPLL_CON0, NULL),
767
749
};
768
750
751
+
static void __init exynos3_core_down_clock(void)
752
+
{
753
+
unsigned int tmp;
754
+
755
+
/*
756
+
* Enable arm clock down (in idle) and set arm divider
757
+
* ratios in WFI/WFE state.
758
+
*/
759
+
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
760
+
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
761
+
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
762
+
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
763
+
__raw_writel(tmp, reg_base + PWR_CTRL1);
764
+
765
+
/*
766
+
* Disable the clock up feature on Exynos4x12, in case it was
767
+
* enabled by bootloader.
768
+
*/
769
+
__raw_writel(0x0, reg_base + PWR_CTRL2);
770
+
}
771
+
769
772
static void __init exynos3250_cmu_init(struct device_node *np)
770
773
{
771
774
struct samsung_clk_provider *ctx;
···
814
775
samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
815
776
samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
816
777
778
+
exynos3_core_down_clock();
779
+
817
780
exynos3250_clk_sleep_init();
781
+
782
+
samsung_clk_of_add_provider(np, ctx);
818
783
}
819
784
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
+230
-1
drivers/clk/samsung/clk-exynos4.c
+230
-1
drivers/clk/samsung/clk-exynos4.c
···
25
25
#define DIV_LEFTBUS 0x4500
26
26
#define GATE_IP_LEFTBUS 0x4800
27
27
#define E4X12_GATE_IP_IMAGE 0x4930
28
+
#define CLKOUT_CMU_LEFTBUS 0x4a00
28
29
#define SRC_RIGHTBUS 0x8200
29
30
#define DIV_RIGHTBUS 0x8500
30
31
#define GATE_IP_RIGHTBUS 0x8800
31
32
#define E4X12_GATE_IP_PERIR 0x8960
33
+
#define CLKOUT_CMU_RIGHTBUS 0x8a00
32
34
#define EPLL_LOCK 0xc010
33
35
#define VPLL_LOCK 0xc020
34
36
#define EPLL_CON0 0xc110
···
100
98
#define GATE_IP_PERIL 0xc950
101
99
#define E4210_GATE_IP_PERIR 0xc960
102
100
#define GATE_BLOCK 0xc970
101
+
#define CLKOUT_CMU_TOP 0xca00
103
102
#define E4X12_MPLL_LOCK 0x10008
104
103
#define E4X12_MPLL_CON0 0x10108
105
104
#define SRC_DMC 0x10200
···
108
105
#define DIV_DMC0 0x10500
109
106
#define DIV_DMC1 0x10504
110
107
#define GATE_IP_DMC 0x10900
108
+
#define CLKOUT_CMU_DMC 0x10a00
111
109
#define APLL_LOCK 0x14000
112
110
#define E4210_MPLL_LOCK 0x14008
113
111
#define APLL_CON0 0x14100
···
118
114
#define DIV_CPU1 0x14504
119
115
#define GATE_SCLK_CPU 0x14800
120
116
#define GATE_IP_CPU 0x14900
117
+
#define CLKOUT_CMU_CPU 0x14a00
118
+
#define PWR_CTRL1 0x15020
119
+
#define E4X12_PWR_CTRL2 0x15024
121
120
#define E4X12_DIV_ISP0 0x18300
122
121
#define E4X12_DIV_ISP1 0x18304
123
122
#define E4X12_GATE_ISP0 0x18800
124
123
#define E4X12_GATE_ISP1 0x18804
124
+
125
+
/* Below definitions are used for PWR_CTRL settings */
126
+
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
127
+
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
128
+
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
129
+
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
130
+
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
131
+
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
132
+
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
133
+
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
134
+
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
135
+
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
136
+
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
137
+
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
125
138
126
139
/* the exynos4 soc type */
127
140
enum exynos4_soc {
···
176
155
E4210_GATE_IP_LCD1,
177
156
E4210_GATE_IP_PERIR,
178
157
E4210_MPLL_CON0,
158
+
PWR_CTRL1,
179
159
};
180
160
181
161
static unsigned long exynos4x12_clk_save[] __initdata = {
···
186
164
E4X12_DIV_ISP,
187
165
E4X12_DIV_CAM1,
188
166
E4X12_MPLL_CON0,
167
+
PWR_CTRL1,
168
+
E4X12_PWR_CTRL2,
189
169
};
190
170
191
171
static unsigned long exynos4_clk_pll_regs[] __initdata = {
···
266
242
DIV_CPU1,
267
243
GATE_SCLK_CPU,
268
244
GATE_IP_CPU,
245
+
CLKOUT_CMU_LEFTBUS,
246
+
CLKOUT_CMU_RIGHTBUS,
247
+
CLKOUT_CMU_TOP,
248
+
CLKOUT_CMU_DMC,
249
+
CLKOUT_CMU_CPU,
269
250
};
270
251
271
252
static const struct samsung_clk_reg_dump src_mask_suspend[] = {
···
426
397
"sclk_epll", "sclk_vpll", };
427
398
PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
428
399
PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
400
+
PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
401
+
"sclk_usbphy1", "sclk_hdmiphy", "none",
402
+
"sclk_epll", "sclk_vpll" };
403
+
PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
404
+
"div_gdl", "div_gpl" };
405
+
PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
406
+
"div_gdr", "div_gpr" };
407
+
PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
408
+
"sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
409
+
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
410
+
"aclk160", "aclk133", "aclk200", "aclk100",
411
+
"sclk_mfc", "sclk_g3d", "sclk_g2d",
412
+
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
413
+
"s_rxbyteclkhs0_4l" };
414
+
PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
415
+
"div_dphy", "none", "div_pwi" };
416
+
PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
417
+
"none", "arm_clk_div_2", "div_corem0",
418
+
"div_corem1", "div_corem0", "div_atb",
419
+
"div_periph", "div_pclk_dbg", "div_hpm" };
429
420
430
421
/* Exynos 4x12-specific parent groups */
431
422
PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
432
423
PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
424
+
PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
425
+
PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
433
426
PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
434
427
PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
435
428
"none", "sclk_hdmiphy", "mout_mpll_user_t",
···
469
418
PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
470
419
PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
471
420
PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
421
+
PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
422
+
"none", "sclk_hdmiphy", "sclk_mpll",
423
+
"sclk_epll", "sclk_vpll" };
424
+
PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
425
+
"div_gdl", "div_gpl" };
426
+
PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
427
+
"div_gdr", "div_gpr" };
428
+
PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
429
+
"sclk_usbphy0", "none", "sclk_hdmiphy",
430
+
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
431
+
"aclk160", "aclk133", "aclk200", "aclk100",
432
+
"sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
433
+
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
434
+
"s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
435
+
"rx_half_byte_clk_csis1", "div_jpeg",
436
+
"sclk_pwm_isp", "sclk_spi0_isp",
437
+
"sclk_spi1_isp", "sclk_uart_isp",
438
+
"sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
439
+
"sclk_pcm0" };
440
+
PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
441
+
"div_dmc", "div_dphy", "fout_mpll_div_2",
442
+
"div_pwi", "none", "div_c2c", "div_c2c_aclk" };
443
+
PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
444
+
"arm_clk_div_2", "div_corem0", "div_corem1",
445
+
"div_cores", "div_atb", "div_periph",
446
+
"div_pclk_dbg", "div_hpm" };
472
447
473
448
/* fixed rate clocks generated outside the soc */
474
449
static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
···
513
436
FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
514
437
};
515
438
439
+
static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
440
+
FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
441
+
FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
442
+
FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
443
+
FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
444
+
};
445
+
446
+
static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
447
+
FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
448
+
};
449
+
450
+
static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {
451
+
FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
452
+
FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
453
+
FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
454
+
FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
455
+
};
456
+
516
457
/* list of mux clocks supported in all exynos4 soc's */
517
458
static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
518
459
MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
···
546
451
MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
547
452
MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
548
453
MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
454
+
455
+
MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
456
+
MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
549
457
};
550
458
551
459
/* list of mux clocks supported in exynos4210 soc */
···
557
459
};
558
460
559
461
static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
462
+
MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
463
+
MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
464
+
CLKOUT_CMU_LEFTBUS, 0, 5),
465
+
466
+
MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
467
+
MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
468
+
CLKOUT_CMU_RIGHTBUS, 0, 5),
469
+
560
470
MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
561
471
MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
562
472
MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
···
578
472
MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
579
473
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
580
474
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
475
+
MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
581
476
MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
582
477
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
583
478
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
···
610
503
MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
611
504
MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
612
505
MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
506
+
MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
507
+
508
+
MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
509
+
MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
510
+
511
+
MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
613
512
};
614
513
615
514
/* list of mux clocks supported in exynos4x12 soc */
616
515
static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
516
+
MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
517
+
MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
518
+
MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
519
+
CLKOUT_CMU_LEFTBUS, 0, 5),
520
+
521
+
MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
522
+
MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
523
+
MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
524
+
CLKOUT_CMU_RIGHTBUS, 0, 5),
525
+
617
526
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
618
527
SRC_CPU, 24, 1),
528
+
MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
529
+
619
530
MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
620
531
MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
621
532
MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
···
656
531
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
657
532
MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
658
533
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
534
+
MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
659
535
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
660
536
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
661
537
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
···
691
565
MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
692
566
MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
693
567
MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
568
+
MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
569
+
570
+
MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
571
+
MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
694
572
MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
695
573
MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
696
574
MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
575
+
MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
697
576
};
698
577
699
578
/* list of divider clocks supported in all exynos4 soc's */
700
579
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
580
+
DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
581
+
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
582
+
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
583
+
CLKOUT_CMU_LEFTBUS, 8, 6),
584
+
585
+
DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
586
+
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
587
+
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
588
+
CLKOUT_CMU_RIGHTBUS, 8, 6),
589
+
701
590
DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
591
+
DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
592
+
DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
593
+
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
594
+
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
595
+
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
702
596
DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
597
+
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
598
+
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
599
+
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
600
+
703
601
DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
704
602
DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
705
603
DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
···
781
631
CLK_SET_RATE_PARENT, 0),
782
632
DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
783
633
CLK_SET_RATE_PARENT, 0),
634
+
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
635
+
636
+
DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
637
+
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
638
+
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
639
+
DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
640
+
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
641
+
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
642
+
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
643
+
DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
784
644
};
785
645
786
646
/* list of divider clocks supported in exynos4210 soc */
···
831
671
DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
832
672
8, 3, CLK_GET_RATE_NOCACHE, 0),
833
673
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
674
+
DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
675
+
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
834
676
};
835
677
836
678
/* list of gate clocks supported in all exynos4 soc's */
···
842
680
* the device name and clock alias names specified below for some
843
681
* of the clocks can be removed.
844
682
*/
683
+
GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
684
+
GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
845
685
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
846
686
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
847
687
0),
···
859
695
GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
860
696
GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
861
697
CLK_SET_RATE_PARENT, 0),
698
+
GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
862
699
GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
863
700
GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
864
701
GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
865
702
GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
866
703
GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
704
+
GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
867
705
GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
868
706
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
869
707
CLK_SET_RATE_PARENT, 0),
···
947
781
0, 0),
948
782
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
949
783
0, 0),
784
+
GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
950
785
GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
951
786
GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
952
787
GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
953
788
0, 0),
789
+
GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
954
790
GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
955
791
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
956
792
0, 0),
957
793
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
958
794
0, 0),
795
+
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
796
+
GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
959
797
GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
960
798
0, 0),
961
799
GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
962
800
0, 0),
801
+
GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
963
802
GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
964
803
0, 0),
965
804
GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
···
977
806
0, 0),
978
807
GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
979
808
0, 0),
809
+
GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
980
810
GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
981
811
0, 0),
982
812
GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
···
1024
852
0, 0),
1025
853
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
1026
854
0, 0),
855
+
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
856
+
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
857
+
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
858
+
GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
859
+
860
+
GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
861
+
CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
862
+
GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
863
+
CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
864
+
GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
865
+
CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
866
+
GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
867
+
CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
868
+
GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
869
+
CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
1027
870
};
1028
871
1029
872
/* list of gate clocks supported in exynos4210 soc */
···
1050
863
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
1051
864
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
1052
865
0),
866
+
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
867
+
0),
868
+
GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
1053
869
GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
1054
870
GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
1055
871
GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
···
1095
905
GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
1096
906
GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
1097
907
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
908
+
0),
909
+
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
1098
910
0),
1099
911
GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
1100
912
GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
···
1254
1062
1255
1063
}
1256
1064
1257
-
static struct of_device_id ext_clk_match[] __initdata = {
1065
+
static const struct of_device_id ext_clk_match[] __initconst = {
1258
1066
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
1259
1067
{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1260
1068
{},
···
1356
1164
VPLL_LOCK, VPLL_CON0, NULL),
1357
1165
};
1358
1166
1167
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
1168
+
{
1169
+
unsigned int tmp;
1170
+
1171
+
/*
1172
+
* Enable arm clock down (in idle) and set arm divider
1173
+
* ratios in WFI/WFE state.
1174
+
*/
1175
+
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1176
+
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1177
+
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1178
+
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1179
+
/* On Exynos4412 enable it also on core 2 and 3 */
1180
+
if (num_possible_cpus() == 4)
1181
+
tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1182
+
PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1183
+
__raw_writel(tmp, reg_base + PWR_CTRL1);
1184
+
1185
+
/*
1186
+
* Disable the clock up feature on Exynos4x12, in case it was
1187
+
* enabled by bootloader.
1188
+
*/
1189
+
if (exynos4_soc == EXYNOS4X12)
1190
+
__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1191
+
}
1192
+
1359
1193
/* register exynos4 clocks */
1360
1194
static void __init exynos4_clk_init(struct device_node *np,
1361
1195
enum exynos4_soc soc)
···
1442
1224
ARRAY_SIZE(exynos4_div_clks));
1443
1225
samsung_clk_register_gate(ctx, exynos4_gate_clks,
1444
1226
ARRAY_SIZE(exynos4_gate_clks));
1227
+
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1228
+
ARRAY_SIZE(exynos4_fixed_factor_clks));
1445
1229
1446
1230
if (exynos4_soc == EXYNOS4210) {
1447
1231
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
···
1456
1236
ARRAY_SIZE(exynos4210_gate_clks));
1457
1237
samsung_clk_register_alias(ctx, exynos4210_aliases,
1458
1238
ARRAY_SIZE(exynos4210_aliases));
1239
+
samsung_clk_register_fixed_factor(ctx,
1240
+
exynos4210_fixed_factor_clks,
1241
+
ARRAY_SIZE(exynos4210_fixed_factor_clks));
1459
1242
} else {
1460
1243
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1461
1244
ARRAY_SIZE(exynos4x12_mux_clks));
···
1468
1245
ARRAY_SIZE(exynos4x12_gate_clks));
1469
1246
samsung_clk_register_alias(ctx, exynos4x12_aliases,
1470
1247
ARRAY_SIZE(exynos4x12_aliases));
1248
+
samsung_clk_register_fixed_factor(ctx,
1249
+
exynos4x12_fixed_factor_clks,
1250
+
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1471
1251
}
1472
1252
1473
1253
samsung_clk_register_alias(ctx, exynos4_aliases,
1474
1254
ARRAY_SIZE(exynos4_aliases));
1475
1255
1256
+
exynos4_core_down_clock(soc);
1476
1257
exynos4_clk_sleep_init();
1258
+
1259
+
samsung_clk_of_add_provider(np, ctx);
1477
1260
1478
1261
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1479
1262
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
+3
-1
drivers/clk/samsung/clk-exynos5250.c
+3
-1
drivers/clk/samsung/clk-exynos5250.c
···
748
748
VPLL_LOCK, VPLL_CON0, NULL),
749
749
};
750
750
751
-
static struct of_device_id ext_clk_match[] __initdata = {
751
+
static const struct of_device_id ext_clk_match[] __initconst = {
752
752
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
753
753
{ },
754
754
};
···
819
819
__raw_writel(tmp, reg_base + PWR_CTRL2);
820
820
821
821
exynos5250_clk_sleep_init();
822
+
823
+
samsung_clk_of_add_provider(np, ctx);
822
824
823
825
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
824
826
_get_rate("div_arm2"));
+2
drivers/clk/samsung/clk-exynos5260.c
+2
drivers/clk/samsung/clk-exynos5260.c
+2
drivers/clk/samsung/clk-exynos5410.c
+2
drivers/clk/samsung/clk-exynos5410.c
···
204
204
samsung_clk_register_gate(ctx, exynos5410_gate_clks,
205
205
ARRAY_SIZE(exynos5410_gate_clks));
206
206
207
+
samsung_clk_of_add_provider(np, ctx);
208
+
207
209
pr_debug("Exynos5410: clock setup completed.\n");
208
210
}
209
211
CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
+60
-1
drivers/clk/samsung/clk-exynos5420.c
+60
-1
drivers/clk/samsung/clk-exynos5420.c
···
28
28
#define GATE_BUS_CPU 0x700
29
29
#define GATE_SCLK_CPU 0x800
30
30
#define CLKOUT_CMU_CPU 0xa00
31
+
#define SRC_MASK_CPERI 0x4300
31
32
#define GATE_IP_G2D 0x8800
32
33
#define CPLL_LOCK 0x10020
33
34
#define DPLL_LOCK 0x10030
···
71
70
#define SRC_TOP11 0x10284
72
71
#define SRC_TOP12 0x10288
73
72
#define SRC_TOP13 0x1028c /* 5800 specific */
73
+
#define SRC_MASK_TOP0 0x10300
74
+
#define SRC_MASK_TOP1 0x10304
74
75
#define SRC_MASK_TOP2 0x10308
75
76
#define SRC_MASK_TOP7 0x1031c
76
77
#define SRC_MASK_DISP10 0x1032c
···
80
77
#define SRC_MASK_FSYS 0x10340
81
78
#define SRC_MASK_PERIC0 0x10350
82
79
#define SRC_MASK_PERIC1 0x10354
80
+
#define SRC_MASK_ISP 0x10370
83
81
#define DIV_TOP0 0x10500
84
82
#define DIV_TOP1 0x10504
85
83
#define DIV_TOP2 0x10508
···
102
98
#define DIV2_RATIO0 0x10590
103
99
#define DIV4_RATIO 0x105a0
104
100
#define GATE_BUS_TOP 0x10700
101
+
#define GATE_BUS_DISP1 0x10728
105
102
#define GATE_BUS_GEN 0x1073c
106
103
#define GATE_BUS_FSYS0 0x10740
107
104
#define GATE_BUS_FSYS2 0x10748
···
195
190
SRC_MASK_FSYS,
196
191
SRC_MASK_PERIC0,
197
192
SRC_MASK_PERIC1,
193
+
SRC_MASK_TOP0,
194
+
SRC_MASK_TOP1,
195
+
SRC_MASK_MAU,
196
+
SRC_MASK_ISP,
198
197
SRC_ISP,
199
198
DIV_TOP0,
200
199
DIV_TOP1,
···
217
208
SCLK_DIV_ISP1,
218
209
DIV2_RATIO0,
219
210
DIV4_RATIO,
211
+
GATE_BUS_DISP1,
220
212
GATE_BUS_TOP,
221
213
GATE_BUS_GEN,
222
214
GATE_BUS_FSYS0,
···
259
249
GATE_IP_CAM,
260
250
};
261
251
252
+
static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
253
+
{ .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
254
+
{ .offset = SRC_MASK_TOP0, .value = 0x11111111, },
255
+
{ .offset = SRC_MASK_TOP1, .value = 0x11101111, },
256
+
{ .offset = SRC_MASK_TOP2, .value = 0x11111110, },
257
+
{ .offset = SRC_MASK_TOP7, .value = 0x00111100, },
258
+
{ .offset = SRC_MASK_DISP10, .value = 0x11111110, },
259
+
{ .offset = SRC_MASK_MAU, .value = 0x10000000, },
260
+
{ .offset = SRC_MASK_FSYS, .value = 0x11111110, },
261
+
{ .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
262
+
{ .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
263
+
{ .offset = SRC_MASK_ISP, .value = 0x11111000, },
264
+
{ .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
265
+
{ .offset = GATE_IP_PERIC, .value = 0xffffffff, },
266
+
};
267
+
262
268
static int exynos5420_clk_suspend(void)
263
269
{
264
270
samsung_clk_save(reg_base, exynos5x_save,
···
283
257
if (exynos5x_soc == EXYNOS5800)
284
258
samsung_clk_save(reg_base, exynos5800_save,
285
259
ARRAY_SIZE(exynos5800_clk_regs));
260
+
261
+
samsung_clk_restore(reg_base, exynos5420_set_clksrc,
262
+
ARRAY_SIZE(exynos5420_set_clksrc));
286
263
287
264
return 0;
288
265
}
···
1196
1167
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1197
1168
};
1198
1169
1170
+
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
1171
+
PLL_35XX_RATE(2000000000, 250, 3, 0),
1172
+
PLL_35XX_RATE(1900000000, 475, 6, 0),
1173
+
PLL_35XX_RATE(1800000000, 225, 3, 0),
1174
+
PLL_35XX_RATE(1700000000, 425, 6, 0),
1175
+
PLL_35XX_RATE(1600000000, 200, 3, 0),
1176
+
PLL_35XX_RATE(1500000000, 250, 4, 0),
1177
+
PLL_35XX_RATE(1400000000, 175, 3, 0),
1178
+
PLL_35XX_RATE(1300000000, 325, 6, 0),
1179
+
PLL_35XX_RATE(1200000000, 200, 2, 1),
1180
+
PLL_35XX_RATE(1100000000, 275, 3, 1),
1181
+
PLL_35XX_RATE(1000000000, 250, 3, 1),
1182
+
PLL_35XX_RATE(900000000, 150, 2, 1),
1183
+
PLL_35XX_RATE(800000000, 200, 3, 1),
1184
+
PLL_35XX_RATE(700000000, 175, 3, 1),
1185
+
PLL_35XX_RATE(600000000, 200, 2, 2),
1186
+
PLL_35XX_RATE(500000000, 250, 3, 2),
1187
+
PLL_35XX_RATE(400000000, 200, 3, 2),
1188
+
PLL_35XX_RATE(300000000, 200, 2, 3),
1189
+
PLL_35XX_RATE(200000000, 200, 3, 3),
1190
+
};
1191
+
1199
1192
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1200
1193
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1201
1194
APLL_CON0, NULL),
···
1243
1192
KPLL_CON0, NULL),
1244
1193
};
1245
1194
1246
-
static struct of_device_id ext_clk_match[] __initdata = {
1195
+
static const struct of_device_id ext_clk_match[] __initconst = {
1247
1196
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1248
1197
{ },
1249
1198
};
···
1271
1220
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1272
1221
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1273
1222
ext_clk_match);
1223
+
1224
+
if (_get_rate("fin_pll") == 24 * MHZ) {
1225
+
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1226
+
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1227
+
}
1228
+
1274
1229
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1275
1230
reg_base);
1276
1231
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
···
1308
1251
}
1309
1252
1310
1253
exynos5420_clk_sleep_init();
1254
+
1255
+
samsung_clk_of_add_provider(np, ctx);
1311
1256
}
1312
1257
1313
1258
static void __init exynos5420_clk_init(struct device_node *np)
+3
-1
drivers/clk/samsung/clk-exynos5440.c
+3
-1
drivers/clk/samsung/clk-exynos5440.c
···
84
84
GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
85
85
};
86
86
87
-
static struct of_device_id ext_clk_match[] __initdata = {
87
+
static const struct of_device_id ext_clk_match[] __initconst = {
88
88
{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
89
89
{},
90
90
};
···
122
122
ARRAY_SIZE(exynos5440_div_clks));
123
123
samsung_clk_register_gate(ctx, exynos5440_gate_clks,
124
124
ARRAY_SIZE(exynos5440_gate_clks));
125
+
126
+
samsung_clk_of_add_provider(np, ctx);
125
127
126
128
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
127
129
pr_info("exynos5440 clock initialization complete\n");
+2
drivers/clk/samsung/clk-s3c2410.c
+2
drivers/clk/samsung/clk-s3c2410.c
+2
drivers/clk/samsung/clk-s3c2412.c
+2
drivers/clk/samsung/clk-s3c2412.c
+2
drivers/clk/samsung/clk-s3c2443.c
+2
drivers/clk/samsung/clk-s3c2443.c
+2
drivers/clk/samsung/clk-s3c64xx.c
+2
drivers/clk/samsung/clk-s3c64xx.c
+11
-10
drivers/clk/samsung/clk.c
+11
-10
drivers/clk/samsung/clk.c
···
53
53
{
54
54
struct samsung_clk_provider *ctx;
55
55
struct clk **clk_table;
56
-
int ret;
57
56
int i;
58
57
59
58
ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
···
71
72
ctx->clk_data.clk_num = nr_clks;
72
73
spin_lock_init(&ctx->lock);
73
74
74
-
if (!np)
75
-
return ctx;
76
-
77
-
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
78
-
&ctx->clk_data);
79
-
if (ret)
80
-
panic("could not register clock provide\n");
81
-
82
75
return ctx;
76
+
}
77
+
78
+
void __init samsung_clk_of_add_provider(struct device_node *np,
79
+
struct samsung_clk_provider *ctx)
80
+
{
81
+
if (np) {
82
+
if (of_clk_add_provider(np, of_clk_src_onecell_get,
83
+
&ctx->clk_data))
84
+
panic("could not register clk provider\n");
85
+
}
83
86
}
84
87
85
88
/* add a clock instance to the clock lookup table used for dt based lookup */
···
285
284
void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
286
285
struct samsung_fixed_rate_clock *fixed_rate_clk,
287
286
unsigned int nr_fixed_rate_clk,
288
-
struct of_device_id *clk_matches)
287
+
const struct of_device_id *clk_matches)
289
288
{
290
289
const struct of_device_id *match;
291
290
struct device_node *clk_np;
+3
-1
drivers/clk/samsung/clk.h
+3
-1
drivers/clk/samsung/clk.h
···
327
327
extern struct samsung_clk_provider *__init samsung_clk_init(
328
328
struct device_node *np, void __iomem *base,
329
329
unsigned long nr_clks);
330
+
extern void __init samsung_clk_of_add_provider(struct device_node *np,
331
+
struct samsung_clk_provider *ctx);
330
332
extern void __init samsung_clk_of_register_fixed_ext(
331
333
struct samsung_clk_provider *ctx,
332
334
struct samsung_fixed_rate_clock *fixed_rate_clk,
333
335
unsigned int nr_fixed_rate_clk,
334
-
struct of_device_id *clk_matches);
336
+
const struct of_device_id *clk_matches);
335
337
336
338
extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
337
339
struct clk *clk, unsigned int id);
+24
-1
include/dt-bindings/clock/exynos4.h
+24
-1
include/dt-bindings/clock/exynos4.h
···
1
1
/*
2
2
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
3
-
* Author: Andrzej Haja <a.hajda@samsung.com>
3
+
* Author: Andrzej Hajda <a.hajda@samsung.com>
4
4
*
5
5
* This program is free software; you can redistribute it and/or modify
6
6
* it under the terms of the GNU General Public License version 2 as
···
34
34
#define CLK_MOUT_CORE 19
35
35
#define CLK_MOUT_APLL 20
36
36
#define CLK_SCLK_HDMIPHY 22
37
+
#define CLK_OUT_DMC 23
38
+
#define CLK_OUT_TOP 24
39
+
#define CLK_OUT_LEFTBUS 25
40
+
#define CLK_OUT_RIGHTBUS 26
41
+
#define CLK_OUT_CPU 27
37
42
38
43
/* gate for special clocks (sclk) */
39
44
#define CLK_SCLK_FIMC0 128
···
234
229
#define CLK_MOUT_G3D1 393
235
230
#define CLK_MOUT_G3D 394
236
231
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
232
+
233
+
/* gate clocks - ppmu */
234
+
#define CLK_PPMULEFT 400
235
+
#define CLK_PPMURIGHT 401
236
+
#define CLK_PPMUCAMIF 402
237
+
#define CLK_PPMUTV 403
238
+
#define CLK_PPMUMFC_L 404
239
+
#define CLK_PPMUMFC_R 405
240
+
#define CLK_PPMUG3D 406
241
+
#define CLK_PPMUIMAGE 407
242
+
#define CLK_PPMULCD0 408
243
+
#define CLK_PPMULCD1 409 /* Exynos4210 only */
244
+
#define CLK_PPMUFILE 410
245
+
#define CLK_PPMUGPS 411
246
+
#define CLK_PPMUDMC0 412
247
+
#define CLK_PPMUDMC1 413
248
+
#define CLK_PPMUCPU 414
249
+
#define CLK_PPMUACP 415
237
250
238
251
/* div clocks */
239
252
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
+1
-1
include/dt-bindings/clock/exynos5250.h
+1
-1
include/dt-bindings/clock/exynos5250.h
···
1
1
/*
2
2
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
3
-
* Author: Andrzej Haja <a.hajda@samsung.com>
3
+
* Author: Andrzej Hajda <a.hajda@samsung.com>
4
4
*
5
5
* This program is free software; you can redistribute it and/or modify
6
6
* it under the terms of the GNU General Public License version 2 as
+1
-1
include/dt-bindings/clock/exynos5420.h
+1
-1
include/dt-bindings/clock/exynos5420.h
···
1
1
/*
2
2
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
3
-
* Author: Andrzej Haja <a.hajda@samsung.com>
3
+
* Author: Andrzej Hajda <a.hajda@samsung.com>
4
4
*
5
5
* This program is free software; you can redistribute it and/or modify
6
6
* it under the terms of the GNU General Public License version 2 as
+1
-1
include/dt-bindings/clock/exynos5440.h
+1
-1
include/dt-bindings/clock/exynos5440.h
···
1
1
/*
2
2
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
3
-
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
3
+
* Author: Andrzej Hajda <a.hajda@samsung.com>
4
4
*
5
5
* This program is free software; you can redistribute it and/or modify
6
6
* it under the terms of the GNU General Public License version 2 as