tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: at91/dt: split sama5d3 peripheral definitions

This patch splits the sama5d3 SoCs definition:
- a common base for all sama5d3 SoCs (sama5d3.dtsi)
- several optional peripheral definitions which will be included by sama5d3
specific SoCs (sama5d3_'periph name'.dtsi)
- sama5d3 specific SoC definitions (sama5d3x.dtsi)

This provides a better representation of the real hardware (drop unneed
dt nodes) and avoids peripheral id conflict (which is not the case for
current sama5d3 SoCs, but could be if other SoCs of this family are
released).

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
[nicolas.ferre@atmel.com: add more "sama5d3?" compatibility strings]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

authored by

Boris BREZILLON and committed by
Nicolas Ferre d7d1d45c d195608a

+429 -208
-203
arch/arm/boot/dts/sama5d3.dtsi
··· 31 31 gpio3 = &pioD; 32 32 gpio4 = &pioE; 33 33 tcb0 = &tcb0; 34 - tcb1 = &tcb1; 35 34 i2c0 = &i2c0; 36 35 i2c1 = &i2c1; 37 36 i2c2 = &i2c2; ··· 104 105 status = "disabled"; 105 106 }; 106 107 107 - can0: can@f000c000 { 108 - compatible = "atmel,at91sam9x5-can"; 109 - reg = <0xf000c000 0x300>; 110 - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 111 - pinctrl-names = "default"; 112 - pinctrl-0 = <&pinctrl_can0_rx_tx>; 113 - status = "disabled"; 114 - }; 115 - 116 108 tcb0: timer@f0010000 { 117 109 compatible = "atmel,at91sam9x5-tcb"; 118 110 reg = <0xf0010000 0x100>; ··· 156 166 status = "disabled"; 157 167 }; 158 168 159 - macb0: ethernet@f0028000 { 160 - compatible = "cdns,pc302-gem", "cdns,gem"; 161 - reg = <0xf0028000 0x100>; 162 - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; 163 - pinctrl-names = "default"; 164 - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; 165 - status = "disabled"; 166 - }; 167 - 168 169 isi: isi@f0034000 { 169 170 compatible = "atmel,at91sam9g45-isi"; 170 171 reg = <0xf0034000 0x4000>; ··· 171 190 dma-names = "rxtx"; 172 191 pinctrl-names = "default"; 173 192 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 174 - status = "disabled"; 175 - #address-cells = <1>; 176 - #size-cells = <0>; 177 - }; 178 - 179 - mmc2: mmc@f8004000 { 180 - compatible = "atmel,hsmci"; 181 - reg = <0xf8004000 0x600>; 182 - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 183 - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; 184 - dma-names = "rxtx"; 185 - pinctrl-names = "default"; 186 - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; 187 193 status = "disabled"; 188 194 #address-cells = <1>; 189 195 #size-cells = <0>; ··· 197 229 pinctrl-names = "default"; 198 230 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 199 231 status = "disabled"; 200 - }; 201 - 202 - can1: can@f8010000 { 203 - compatible = "atmel,at91sam9x5-can"; 204 - reg = <0xf8010000 0x300>; 205 - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 206 - pinctrl-names = "default"; 207 - pinctrl-0 = <&pinctrl_can1_rx_tx>; 208 - }; 209 - 210 - tcb1: timer@f8014000 { 211 - compatible = "atmel,at91sam9x5-tcb"; 212 - reg = <0xf8014000 0x100>; 213 - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 214 232 }; 215 233 216 234 adc0: adc@f8018000 { ··· 292 338 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 293 339 pinctrl-names = "default"; 294 340 pinctrl-0 = <&pinctrl_usart3>; 295 - status = "disabled"; 296 - }; 297 - 298 - macb1: ethernet@f802c000 { 299 - compatible = "cdns,at32ap7000-macb", "cdns,macb"; 300 - reg = <0xf802c000 0x100>; 301 - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; 302 - pinctrl-names = "default"; 303 - pinctrl-0 = <&pinctrl_macb1_rmii>; 304 341 status = "disabled"; 305 342 }; 306 343 ··· 419 474 }; 420 475 }; 421 476 422 - can0 { 423 - pinctrl_can0_rx_tx: can0_rx_tx { 424 - atmel,pins = 425 - <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ 426 - AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ 427 - }; 428 - }; 429 - 430 - can1 { 431 - pinctrl_can1_rx_tx: can1_rx_tx { 432 - atmel,pins = 433 - <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ 434 - AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ 435 - }; 436 - }; 437 - 438 477 dbgu { 439 478 pinctrl_dbgu: dbgu-0 { 440 479 atmel,pins = ··· 466 537 }; 467 538 }; 468 539 469 - lcd { 470 - pinctrl_lcd: lcd-0 { 471 - atmel,pins = 472 - <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ 473 - AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ 474 - AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ 475 - AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ 476 - AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ 477 - AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ 478 - AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ 479 - AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ 480 - AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ 481 - AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ 482 - AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ 483 - AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ 484 - AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ 485 - AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ 486 - AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ 487 - AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ 488 - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ 489 - AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ 490 - AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ 491 - AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ 492 - AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ 493 - AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ 494 - AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ 495 - AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ 496 - AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ 497 - AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ 498 - AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ 499 - AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ 500 - AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ 501 - AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ 502 - }; 503 - }; 504 - 505 - macb0 { 506 - pinctrl_macb0_data_rgmii: macb0_data_rgmii { 507 - atmel,pins = 508 - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ 509 - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ 510 - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ 511 - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ 512 - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ 513 - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ 514 - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ 515 - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ 516 - }; 517 - pinctrl_macb0_data_gmii: macb0_data_gmii { 518 - atmel,pins = 519 - <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ 520 - AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ 521 - AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ 522 - AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ 523 - AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ 524 - AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ 525 - AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ 526 - AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ 527 - }; 528 - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { 529 - atmel,pins = 530 - <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ 531 - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ 532 - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ 533 - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ 534 - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ 535 - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ 536 - AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ 537 - }; 538 - pinctrl_macb0_signal_gmii: macb0_signal_gmii { 539 - atmel,pins = 540 - <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ 541 - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ 542 - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ 543 - AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ 544 - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ 545 - AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ 546 - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ 547 - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ 548 - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ 549 - AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ 550 - }; 551 - 552 - }; 553 - 554 - macb1 { 555 - pinctrl_macb1_rmii: macb1_rmii-0 { 556 - atmel,pins = 557 - <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ 558 - AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ 559 - AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ 560 - AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ 561 - AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ 562 - AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ 563 - AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ 564 - AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ 565 - AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ 566 - AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ 567 - }; 568 - }; 569 - 570 540 mmc0 { 571 541 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 572 542 atmel,pins = ··· 500 672 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 501 673 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 502 674 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 503 - }; 504 - }; 505 - 506 - mmc2 { 507 - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { 508 - atmel,pins = 509 - <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ 510 - AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ 511 - AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ 512 - }; 513 - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { 514 - atmel,pins = 515 - <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ 516 - AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ 517 - AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ 518 675 }; 519 676 }; 520 677 ··· 558 745 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ 559 746 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ 560 747 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ 561 - }; 562 - }; 563 - 564 - uart0 { 565 - pinctrl_uart0: uart0-0 { 566 - atmel,pins = 567 - <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ 568 - AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ 569 - }; 570 - }; 571 - 572 - uart1 { 573 - pinctrl_uart1: uart1-0 { 574 - atmel,pins = 575 - <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ 576 - AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ 577 748 }; 578 749 }; 579 750
+16
arch/arm/boot/dts/sama5d31.dtsi
··· 1 + /* 2 + * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC 3 + * 4 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 + * 6 + * Licensed under GPLv2 or later. 7 + */ 8 + #include "sama5d3.dtsi" 9 + #include "sama5d3_lcd.dtsi" 10 + #include "sama5d3_emac.dtsi" 11 + #include "sama5d3_mci2.dtsi" 12 + #include "sama5d3_uart.dtsi" 13 + 14 + / { 15 + compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5"; 16 + };
+2 -1
arch/arm/boot/dts/sama5d31ek.dts
··· 7 7 * Licensed under GPLv2 or later. 8 8 */ 9 9 /dts-v1/; 10 + #include "sama5d31.dtsi" 10 11 #include "sama5d3xmb.dtsi" 11 12 #include "sama5d3xdm.dtsi" 12 13 13 14 / { 14 15 model = "Atmel SAMA5D31-EK"; 15 - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; 16 17 17 18 ahb { 18 19 apb {
+14
arch/arm/boot/dts/sama5d33.dtsi
··· 1 + /* 2 + * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC 3 + * 4 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 + * 6 + * Licensed under GPLv2 or later. 7 + */ 8 + #include "sama5d3.dtsi" 9 + #include "sama5d3_lcd.dtsi" 10 + #include "sama5d3_gmac.dtsi" 11 + 12 + / { 13 + compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5"; 14 + };
+2 -1
arch/arm/boot/dts/sama5d33ek.dts
··· 7 7 * Licensed under GPLv2 or later. 8 8 */ 9 9 /dts-v1/; 10 + #include "sama5d33.dtsi" 10 11 #include "sama5d3xmb.dtsi" 11 12 #include "sama5d3xdm.dtsi" 12 13 13 14 / { 14 15 model = "Atmel SAMA5D33-EK"; 15 - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; 16 17 17 18 ahb { 18 19 apb {
+16
arch/arm/boot/dts/sama5d34.dtsi
··· 1 + /* 2 + * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC 3 + * 4 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 + * 6 + * Licensed under GPLv2 or later. 7 + */ 8 + #include "sama5d3.dtsi" 9 + #include "sama5d3_lcd.dtsi" 10 + #include "sama5d3_gmac.dtsi" 11 + #include "sama5d3_can.dtsi" 12 + #include "sama5d3_mci2.dtsi" 13 + 14 + / { 15 + compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5"; 16 + };
+2 -1
arch/arm/boot/dts/sama5d34ek.dts
··· 7 7 * Licensed under GPLv2 or later. 8 8 */ 9 9 /dts-v1/; 10 + #include "sama5d34.dtsi" 10 11 #include "sama5d3xmb.dtsi" 11 12 #include "sama5d3xdm.dtsi" 12 13 13 14 / { 14 15 model = "Atmel SAMA5D34-EK"; 15 - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 16 + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; 16 17 17 18 ahb { 18 19 apb {
+18
arch/arm/boot/dts/sama5d35.dtsi
··· 1 + /* 2 + * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC 3 + * 4 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 + * 6 + * Licensed under GPLv2 or later. 7 + */ 8 + #include "sama5d3.dtsi" 9 + #include "sama5d3_gmac.dtsi" 10 + #include "sama5d3_emac.dtsi" 11 + #include "sama5d3_can.dtsi" 12 + #include "sama5d3_mci2.dtsi" 13 + #include "sama5d3_uart.dtsi" 14 + #include "sama5d3_tcb1.dtsi" 15 + 16 + / { 17 + compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5"; 18 + };
+2 -1
arch/arm/boot/dts/sama5d35ek.dts
··· 7 7 * Licensed under GPLv2 or later. 8 8 */ 9 9 /dts-v1/; 10 + #include "sama5d35.dtsi" 10 11 #include "sama5d3xmb.dtsi" 11 12 12 13 / { 13 14 model = "Atmel SAMA5D35-EK"; 14 - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; 15 + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; 15 16 16 17 ahb { 17 18 apb {
+54
arch/arm/boot/dts/sama5d3_can.dtsi
··· 1 + /* 2 + * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * CAN support 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + can0 { 18 + pinctrl_can0_rx_tx: can0_rx_tx { 19 + atmel,pins = 20 + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ 21 + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ 22 + }; 23 + }; 24 + 25 + can1 { 26 + pinctrl_can1_rx_tx: can1_rx_tx { 27 + atmel,pins = 28 + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ 29 + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ 30 + }; 31 + }; 32 + 33 + }; 34 + 35 + can0: can@f000c000 { 36 + compatible = "atmel,at91sam9x5-can"; 37 + reg = <0xf000c000 0x300>; 38 + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&pinctrl_can0_rx_tx>; 41 + status = "disabled"; 42 + }; 43 + 44 + can1: can@f8010000 { 45 + compatible = "atmel,at91sam9x5-can"; 46 + reg = <0xf8010000 0x300>; 47 + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 48 + pinctrl-names = "default"; 49 + pinctrl-0 = <&pinctrl_can1_rx_tx>; 50 + status = "disabled"; 51 + }; 52 + }; 53 + }; 54 + };
+44
arch/arm/boot/dts/sama5d3_emac.dtsi
··· 1 + /* 2 + * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * Ethernet. 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + macb1 { 18 + pinctrl_macb1_rmii: macb1_rmii-0 { 19 + atmel,pins = 20 + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ 21 + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ 22 + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ 23 + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ 24 + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ 25 + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ 26 + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ 27 + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ 28 + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ 29 + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ 30 + }; 31 + }; 32 + }; 33 + 34 + macb1: ethernet@f802c000 { 35 + compatible = "cdns,at32ap7000-macb", "cdns,macb"; 36 + reg = <0xf802c000 0x100>; 37 + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; 38 + pinctrl-names = "default"; 39 + pinctrl-0 = <&pinctrl_macb1_rmii>; 40 + status = "disabled"; 41 + }; 42 + }; 43 + }; 44 + };
+77
arch/arm/boot/dts/sama5d3_gmac.dtsi
··· 1 + /* 2 + * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * Gigabit Ethernet. 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + macb0 { 18 + pinctrl_macb0_data_rgmii: macb0_data_rgmii { 19 + atmel,pins = 20 + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ 21 + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ 22 + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ 23 + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ 24 + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ 25 + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ 26 + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ 27 + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ 28 + }; 29 + pinctrl_macb0_data_gmii: macb0_data_gmii { 30 + atmel,pins = 31 + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ 32 + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ 33 + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ 34 + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ 35 + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ 36 + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ 37 + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ 38 + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ 39 + }; 40 + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { 41 + atmel,pins = 42 + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ 43 + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ 44 + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ 45 + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ 46 + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ 47 + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ 48 + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ 49 + }; 50 + pinctrl_macb0_signal_gmii: macb0_signal_gmii { 51 + atmel,pins = 52 + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ 53 + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ 54 + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ 55 + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ 56 + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ 57 + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ 58 + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ 59 + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ 60 + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ 61 + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ 62 + }; 63 + 64 + }; 65 + }; 66 + 67 + macb0: ethernet@f0028000 { 68 + compatible = "cdns,pc302-gem", "cdns,gem"; 69 + reg = <0xf0028000 0x100>; 70 + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; 71 + pinctrl-names = "default"; 72 + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; 73 + status = "disabled"; 74 + }; 75 + }; 76 + }; 77 + };
+55
arch/arm/boot/dts/sama5d3_lcd.dtsi
··· 1 + /* 2 + * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * LCD support 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + lcd { 18 + pinctrl_lcd: lcd-0 { 19 + atmel,pins = 20 + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ 21 + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ 22 + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ 23 + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ 24 + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ 25 + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ 26 + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ 27 + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ 28 + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ 29 + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ 30 + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ 31 + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ 32 + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ 33 + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ 34 + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ 35 + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ 36 + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ 37 + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ 38 + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ 39 + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ 40 + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ 41 + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ 42 + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ 43 + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ 44 + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ 45 + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ 46 + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ 47 + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ 48 + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ 49 + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ 50 + }; 51 + }; 52 + }; 53 + }; 54 + }; 55 + };
+47
arch/arm/boot/dts/sama5d3_mci2.dtsi
··· 1 + /* 2 + * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * 3 MMC ports 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + mmc2 { 18 + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { 19 + atmel,pins = 20 + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ 21 + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ 22 + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ 23 + }; 24 + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { 25 + atmel,pins = 26 + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ 27 + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ 28 + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ 29 + }; 30 + }; 31 + }; 32 + 33 + mmc2: mmc@f8004000 { 34 + compatible = "atmel,hsmci"; 35 + reg = <0xf8004000 0x600>; 36 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 37 + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; 38 + dma-names = "rxtx"; 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; 41 + status = "disabled"; 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + }; 45 + }; 46 + }; 47 + };
+27
arch/arm/boot/dts/sama5d3_tcb1.dtsi
··· 1 + /* 2 + * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * 2 TC blocks. 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + aliases { 15 + tcb1 = &tcb1; 16 + }; 17 + 18 + ahb { 19 + apb { 20 + tcb1: timer@f8014000 { 21 + compatible = "atmel,at91sam9x5-tcb"; 22 + reg = <0xf8014000 0x100>; 23 + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 24 + }; 25 + }; 26 + }; 27 + };
+53
arch/arm/boot/dts/sama5d3_uart.dtsi
··· 1 + /* 2 + * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 3 + * UART support 4 + * 5 + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 + * 7 + * Licensed under GPLv2. 8 + */ 9 + 10 + #include <dt-bindings/pinctrl/at91.h> 11 + #include <dt-bindings/interrupt-controller/irq.h> 12 + 13 + / { 14 + ahb { 15 + apb { 16 + pinctrl@fffff200 { 17 + uart0 { 18 + pinctrl_uart0: uart0-0 { 19 + atmel,pins = 20 + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ 21 + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ 22 + }; 23 + }; 24 + 25 + uart1 { 26 + pinctrl_uart1: uart1-0 { 27 + atmel,pins = 28 + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ 29 + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ 30 + }; 31 + }; 32 + }; 33 + 34 + uart0: serial@f0024000 { 35 + compatible = "atmel,at91sam9260-usart"; 36 + reg = <0xf0024000 0x200>; 37 + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 38 + pinctrl-names = "default"; 39 + pinctrl-0 = <&pinctrl_uart0>; 40 + status = "disabled"; 41 + }; 42 + 43 + uart1: serial@f8028000 { 44 + compatible = "atmel,at91sam9260-usart"; 45 + reg = <0xf8028000 0x200>; 46 + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 47 + pinctrl-names = "default"; 48 + pinctrl-0 = <&pinctrl_uart1>; 49 + status = "disabled"; 50 + }; 51 + }; 52 + }; 53 + };
-1
arch/arm/boot/dts/sama5d3xcm.dtsi
··· 6 6 * 7 7 * Licensed under GPLv2 or later. 8 8 */ 9 - #include "sama5d3.dtsi" 10 9 11 10 / { 12 11 compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";