tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'at91-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/cleanup

Merge "First batch of cleanup for 4.2" from Alexandre Belloni:

- use syscon in the ata and cf drivers to configure the SMC and drop
sam9_smc.c
- switch the at91rm9200 memory controller to syscon
- remove last useless headers
- remove now useless Makefile.boot

* tag 'at91-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: at91: remove useless Makefile.boot
ARM: at91: remove at91rm9200_sdramc.h
ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
ARM: at91/pm: use the atmel-mc syscon defines
pcmcia: at91_cf: Use syscon to configure the MC/smc
ARM: at91: declare the at91rm9200 memory controller as a syscon
mfd: syscon: Add Atmel MC (Memory Controller) registers definition
ARM: at91: drop sam9_smc.c
ata: at91: use syscon to configure the smc

Arnd Bergmann d7c82daf 2ed25580

+249 -508
+1 -1
Documentation/devicetree/bindings/arm/atmel-at91.txt
··· 98 98 }; 99 99 100 100 RAMC SDRAM/DDR Controller required properties: 101 - - compatible: Should be "atmel,at91rm9200-sdramc", 101 + - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" 102 102 "atmel,at91sam9260-sdramc", 103 103 "atmel,at91sam9g45-ddramc", 104 104 "atmel,sama5d3-ddramc",
+1 -1
arch/arm/boot/dts/at91rm9200.dtsi
··· 92 92 }; 93 93 94 94 ramc0: ramc@ffffff00 { 95 - compatible = "atmel,at91rm9200-sdramc"; 95 + compatible = "atmel,at91rm9200-sdramc", "syscon"; 96 96 reg = <0xffffff00 0x100>; 97 97 }; 98 98
-5
arch/arm/mach-at91/Makefile
··· 1 1 # 2 2 # Makefile for the linux kernel. 3 3 # 4 - ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 5 - asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 6 - 7 4 obj-y := soc.o 8 - 9 - obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 10 5 11 6 # CPU-specific support 12 7 obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
-8
arch/arm/mach-at91/Makefile.boot
··· 1 - # Note: the following conditions must always be true: 2 - # ZRELADDR == virt_to_phys(TEXTADDR) 3 - # PARAMS_PHYS must be within 4MB of ZRELADDR 4 - # INITRD_PHYS must be in RAM 5 - 6 - zreladdr-y += 0x20008000 7 - params_phys-y := 0x20000100 8 - initrd_phys-y := 0x20410000
-28
arch/arm/mach-at91/include/mach/at91_ramc.h
··· 1 - /* 2 - * Header file for the Atmel RAM Controller 3 - * 4 - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 - * 6 - * Under GPLv2 only 7 - */ 8 - 9 - #ifndef __AT91_RAMC_H__ 10 - #define __AT91_RAMC_H__ 11 - 12 - #ifndef __ASSEMBLY__ 13 - extern void __iomem *at91_ramc_base[]; 14 - 15 - #define at91_ramc_read(id, field) \ 16 - __raw_readl(at91_ramc_base[id] + field) 17 - 18 - #define at91_ramc_write(id, field, value) \ 19 - __raw_writel(value, at91_ramc_base[id] + field) 20 - #else 21 - .extern at91_ramc_base 22 - #endif 23 - 24 - #include <soc/at91/at91rm9200_sdramc.h> 25 - #include <soc/at91/at91sam9_ddrsdr.h> 26 - #include <soc/at91/at91sam9_sdramc.h> 27 - 28 - #endif /* __AT91_RAMC_H__ */
-116
arch/arm/mach-at91/include/mach/at91rm9200_mc.h
··· 1 - /* 2 - * arch/arm/mach-at91/include/mach/at91rm9200_mc.h 3 - * 4 - * Copyright (C) 2005 Ivan Kokshaysky 5 - * Copyright (C) SAN People 6 - * 7 - * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. 8 - * Based on AT91RM9200 datasheet revision E. 9 - * 10 - * This program is free software; you can redistribute it and/or modify 11 - * it under the terms of the GNU General Public License as published by 12 - * the Free Software Foundation; either version 2 of the License, or 13 - * (at your option) any later version. 14 - */ 15 - 16 - #ifndef AT91RM9200_MC_H 17 - #define AT91RM9200_MC_H 18 - 19 - /* Memory Controller */ 20 - #define AT91_MC_RCR 0x00 /* MC Remap Control Register */ 21 - #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 22 - 23 - #define AT91_MC_ASR 0x04 /* MC Abort Status Register */ 24 - #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ 25 - #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ 26 - #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ 27 - #define AT91_MC_ABTSZ_BYTE (0 << 8) 28 - #define AT91_MC_ABTSZ_HALFWORD (1 << 8) 29 - #define AT91_MC_ABTSZ_WORD (2 << 8) 30 - #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ 31 - #define AT91_MC_ABTTYP_DATAREAD (0 << 10) 32 - #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) 33 - #define AT91_MC_ABTTYP_FETCH (2 << 10) 34 - #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ 35 - #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ 36 - #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ 37 - #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ 38 - #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ 39 - #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ 40 - #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ 41 - #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ 42 - 43 - #define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */ 44 - 45 - #define AT91_MC_MPR 0x0c /* MC Master Priority Register */ 46 - #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ 47 - #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ 48 - #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ 49 - #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ 50 - 51 - /* External Bus Interface (EBI) registers */ 52 - #define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */ 53 - #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ 54 - #define AT91_EBI_CS0A_SMC (0 << 0) 55 - #define AT91_EBI_CS0A_BFC (1 << 0) 56 - #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 57 - #define AT91_EBI_CS1A_SMC (0 << 1) 58 - #define AT91_EBI_CS1A_SDRAMC (1 << 1) 59 - #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ 60 - #define AT91_EBI_CS3A_SMC (0 << 3) 61 - #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 62 - #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ 63 - #define AT91_EBI_CS4A_SMC (0 << 4) 64 - #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) 65 - #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ 66 - #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ 67 - 68 - /* Static Memory Controller (SMC) registers */ 69 - #define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */ 70 - #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 71 - #define AT91_SMC_NWS_(x) ((x) << 0) 72 - #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 73 - #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ 74 - #define AT91_SMC_TDF_(x) ((x) << 8) 75 - #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ 76 - #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ 77 - #define AT91_SMC_DBW_16 (1 << 13) 78 - #define AT91_SMC_DBW_8 (2 << 13) 79 - #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ 80 - #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ 81 - #define AT91_SMC_ACSS_STD (0 << 16) 82 - #define AT91_SMC_ACSS_1 (1 << 16) 83 - #define AT91_SMC_ACSS_2 (2 << 16) 84 - #define AT91_SMC_ACSS_3 (3 << 16) 85 - #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ 86 - #define AT91_SMC_RWSETUP_(x) ((x) << 24) 87 - #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 88 - #define AT91_SMC_RWHOLD_(x) ((x) << 28) 89 - 90 - /* Burst Flash Controller register */ 91 - #define AT91_BFC_MR 0xc0 /* Mode Register */ 92 - #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ 93 - #define AT91_BFC_BFCOM_DISABLED (0 << 0) 94 - #define AT91_BFC_BFCOM_ASYNC (1 << 0) 95 - #define AT91_BFC_BFCOM_BURST (2 << 0) 96 - #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ 97 - #define AT91_BFC_BFCC_MCK (1 << 2) 98 - #define AT91_BFC_BFCC_DIV2 (2 << 2) 99 - #define AT91_BFC_BFCC_DIV4 (3 << 2) 100 - #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ 101 - #define AT91_BFC_PAGES (7 << 8) /* Page Size */ 102 - #define AT91_BFC_PAGES_NO_PAGE (0 << 8) 103 - #define AT91_BFC_PAGES_16 (1 << 8) 104 - #define AT91_BFC_PAGES_32 (2 << 8) 105 - #define AT91_BFC_PAGES_64 (3 << 8) 106 - #define AT91_BFC_PAGES_128 (4 << 8) 107 - #define AT91_BFC_PAGES_256 (5 << 8) 108 - #define AT91_BFC_PAGES_512 (6 << 8) 109 - #define AT91_BFC_PAGES_1024 (7 << 8) 110 - #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ 111 - #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ 112 - #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ 113 - #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ 114 - #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ 115 - 116 - #endif
-98
arch/arm/mach-at91/include/mach/at91sam9_smc.h
··· 1 - /* 2 - * arch/arm/mach-at91/include/mach/at91sam9_smc.h 3 - * 4 - * Copyright (C) 2007 Andrew Victor 5 - * Copyright (C) 2007 Atmel Corporation. 6 - * 7 - * Static Memory Controllers (SMC) - System peripherals registers. 8 - * Based on AT91SAM9261 datasheet revision D. 9 - * 10 - * This program is free software; you can redistribute it and/or modify 11 - * it under the terms of the GNU General Public License as published by 12 - * the Free Software Foundation; either version 2 of the License, or 13 - * (at your option) any later version. 14 - */ 15 - 16 - #ifndef AT91SAM9_SMC_H 17 - #define AT91SAM9_SMC_H 18 - 19 - #ifndef __ASSEMBLY__ 20 - struct sam9_smc_config { 21 - /* Setup register */ 22 - u8 ncs_read_setup; 23 - u8 nrd_setup; 24 - u8 ncs_write_setup; 25 - u8 nwe_setup; 26 - 27 - /* Pulse register */ 28 - u8 ncs_read_pulse; 29 - u8 nrd_pulse; 30 - u8 ncs_write_pulse; 31 - u8 nwe_pulse; 32 - 33 - /* Cycle register */ 34 - u16 read_cycle; 35 - u16 write_cycle; 36 - 37 - /* Mode register */ 38 - u32 mode; 39 - u8 tdf_cycles:4; 40 - }; 41 - 42 - extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); 43 - extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); 44 - extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); 45 - extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); 46 - #endif 47 - 48 - #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 49 - #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 50 - #define AT91_SMC_NWESETUP_(x) ((x) << 0) 51 - #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ 52 - #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) 53 - #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ 54 - #define AT91_SMC_NRDSETUP_(x) ((x) << 16) 55 - #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ 56 - #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) 57 - 58 - #define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ 59 - #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ 60 - #define AT91_SMC_NWEPULSE_(x) ((x) << 0) 61 - #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ 62 - #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) 63 - #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ 64 - #define AT91_SMC_NRDPULSE_(x) ((x) << 16) 65 - #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ 66 - #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) 67 - 68 - #define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ 69 - #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ 70 - #define AT91_SMC_NWECYCLE_(x) ((x) << 0) 71 - #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ 72 - #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) 73 - 74 - #define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ 75 - #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 76 - #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 77 - #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ 78 - #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) 79 - #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) 80 - #define AT91_SMC_EXNWMODE_READY (3 << 4) 81 - #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ 82 - #define AT91_SMC_BAT_SELECT (0 << 8) 83 - #define AT91_SMC_BAT_WRITE (1 << 8) 84 - #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ 85 - #define AT91_SMC_DBW_8 (0 << 12) 86 - #define AT91_SMC_DBW_16 (1 << 12) 87 - #define AT91_SMC_DBW_32 (2 << 12) 88 - #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ 89 - #define AT91_SMC_TDF_(x) ((x) << 16) 90 - #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ 91 - #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ 92 - #define AT91_SMC_PS (3 << 28) /* Page Size */ 93 - #define AT91_SMC_PS_4 (0 << 28) 94 - #define AT91_SMC_PS_8 (1 << 28) 95 - #define AT91_SMC_PS_16 (2 << 28) 96 - #define AT91_SMC_PS_32 (3 << 28) 97 - 98 - #endif
+4 -4
arch/arm/mach-at91/pm.c
··· 233 233 */ 234 234 static void at91rm9200_standby(void) 235 235 { 236 - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); 236 + u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR); 237 237 238 238 asm volatile( 239 239 "b 1f\n\t" ··· 244 244 " mcr p15, 0, %0, c7, c0, 4\n\t" 245 245 " str %5, [%1, %2]" 246 246 : 247 - : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), 248 - "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 247 + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR), 248 + "r" (1), "r" (AT91_MC_SDRAMC_SRR), 249 249 "r" (lpr)); 250 250 } 251 251 ··· 414 414 /* 415 415 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 416 416 */ 417 - at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); 417 + at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 418 418 419 419 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 420 420 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
+13 -1
arch/arm/mach-at91/pm.h
··· 13 13 14 14 #include <asm/proc-fns.h> 15 15 16 - #include <mach/at91_ramc.h> 16 + #include <linux/mfd/syscon/atmel-mc.h> 17 + #include <soc/at91/at91sam9_ddrsdr.h> 18 + #include <soc/at91/at91sam9_sdramc.h> 19 + 20 + #ifndef __ASSEMBLY__ 21 + extern void __iomem *at91_ramc_base[]; 22 + 23 + #define at91_ramc_read(id, field) \ 24 + __raw_readl(at91_ramc_base[id] + field) 25 + 26 + #define at91_ramc_write(id, field, value) \ 27 + __raw_writel(value, at91_ramc_base[id] + field) 28 + #endif 17 29 18 30 #define AT91_MEMCTRL_MC 0 19 31 #define AT91_MEMCTRL_SDRAMC 1
+1 -2
arch/arm/mach-at91/pm_suspend.S
··· 13 13 */ 14 14 #include <linux/linkage.h> 15 15 #include <linux/clk/at91_pmc.h> 16 - #include <mach/at91_ramc.h> 17 16 #include "pm.h" 18 17 19 18 #define SRAMC_SELF_FRESH_ACTIVE 0x01 ··· 215 216 216 217 /* Active SDRAM self-refresh mode */ 217 218 mov r3, #1 218 - str r3, [r2, #AT91RM9200_SDRAMC_SRR] 219 + str r3, [r2, #AT91_MC_SDRAMC_SRR] 219 220 b exit_sramc_sf 220 221 221 222 ddrc_sf:
-136
arch/arm/mach-at91/sam9_smc.c
··· 1 - /* 2 - * linux/arch/arm/mach-at91/sam9_smc.c 3 - * 4 - * Copyright (C) 2008 Andrew Victor 5 - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License version 2 as 9 - * published by the Free Software Foundation. 10 - */ 11 - 12 - #include <linux/module.h> 13 - #include <linux/io.h> 14 - #include <linux/of.h> 15 - #include <linux/of_address.h> 16 - 17 - #include <mach/at91sam9_smc.h> 18 - 19 - #include "sam9_smc.h" 20 - 21 - 22 - #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10)) 23 - 24 - static void __iomem *smc_base_addr[2]; 25 - 26 - static void sam9_smc_cs_write_mode(void __iomem *base, 27 - struct sam9_smc_config *config) 28 - { 29 - __raw_writel(config->mode 30 - | AT91_SMC_TDF_(config->tdf_cycles), 31 - base + AT91_SMC_MODE); 32 - } 33 - 34 - void sam9_smc_write_mode(int id, int cs, 35 - struct sam9_smc_config *config) 36 - { 37 - sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); 38 - } 39 - EXPORT_SYMBOL_GPL(sam9_smc_write_mode); 40 - 41 - static void sam9_smc_cs_configure(void __iomem *base, 42 - struct sam9_smc_config *config) 43 - { 44 - 45 - /* Setup register */ 46 - __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) 47 - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) 48 - | AT91_SMC_NRDSETUP_(config->nrd_setup) 49 - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), 50 - base + AT91_SMC_SETUP); 51 - 52 - /* Pulse register */ 53 - __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) 54 - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) 55 - | AT91_SMC_NRDPULSE_(config->nrd_pulse) 56 - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), 57 - base + AT91_SMC_PULSE); 58 - 59 - /* Cycle register */ 60 - __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) 61 - | AT91_SMC_NRDCYCLE_(config->read_cycle), 62 - base + AT91_SMC_CYCLE); 63 - 64 - /* Mode register */ 65 - sam9_smc_cs_write_mode(base, config); 66 - } 67 - 68 - void sam9_smc_configure(int id, int cs, 69 - struct sam9_smc_config *config) 70 - { 71 - sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 72 - } 73 - EXPORT_SYMBOL_GPL(sam9_smc_configure); 74 - 75 - static void sam9_smc_cs_read_mode(void __iomem *base, 76 - struct sam9_smc_config *config) 77 - { 78 - u32 val = __raw_readl(base + AT91_SMC_MODE); 79 - 80 - config->mode = (val & ~AT91_SMC_NWECYCLE); 81 - config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; 82 - } 83 - 84 - void sam9_smc_read_mode(int id, int cs, 85 - struct sam9_smc_config *config) 86 - { 87 - sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); 88 - } 89 - EXPORT_SYMBOL_GPL(sam9_smc_read_mode); 90 - 91 - static void sam9_smc_cs_read(void __iomem *base, 92 - struct sam9_smc_config *config) 93 - { 94 - u32 val; 95 - 96 - /* Setup register */ 97 - val = __raw_readl(base + AT91_SMC_SETUP); 98 - 99 - config->nwe_setup = val & AT91_SMC_NWESETUP; 100 - config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; 101 - config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; 102 - config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; 103 - 104 - /* Pulse register */ 105 - val = __raw_readl(base + AT91_SMC_PULSE); 106 - 107 - config->nwe_pulse = val & AT91_SMC_NWEPULSE; 108 - config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; 109 - config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; 110 - config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; 111 - 112 - /* Cycle register */ 113 - val = __raw_readl(base + AT91_SMC_CYCLE); 114 - 115 - config->write_cycle = val & AT91_SMC_NWECYCLE; 116 - config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; 117 - 118 - /* Mode register */ 119 - sam9_smc_cs_read_mode(base, config); 120 - } 121 - 122 - void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) 123 - { 124 - sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); 125 - } 126 - 127 - void __init at91sam9_ioremap_smc(int id, u32 addr) 128 - { 129 - if (id > 1) { 130 - pr_warn("%s: id > 2\n", __func__); 131 - return; 132 - } 133 - smc_base_addr[id] = ioremap(addr, 512); 134 - if (!smc_base_addr[id]) 135 - pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr); 136 - }
-11
arch/arm/mach-at91/sam9_smc.h
··· 1 - /* 2 - * linux/arch/arm/mach-at91/sam9_smc. 3 - * 4 - * Copyright (C) 2008 Andrew Victor 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License version 2 as 8 - * published by the Free Software Foundation. 9 - */ 10 - 11 - extern void __init at91sam9_ioremap_smc(int id, u32 addr);
-1
drivers/ata/Kconfig
··· 835 835 config PATA_AT91 836 836 tristate "PATA support for AT91SAM9260" 837 837 depends on ARM && SOC_AT91SAM9 838 - depends on !ARCH_MULTIPLATFORM 839 838 help 840 839 This option enables support for IDE devices on the Atmel AT91SAM9260 SoC. 841 840
+71 -21
drivers/ata/pata_at91.c
··· 24 24 #include <linux/ata.h> 25 25 #include <linux/clk.h> 26 26 #include <linux/libata.h> 27 + #include <linux/mfd/syscon.h> 28 + #include <linux/mfd/syscon/atmel-smc.h> 27 29 #include <linux/platform_device.h> 28 30 #include <linux/ata_platform.h> 29 31 #include <linux/platform_data/atmel.h> 32 + #include <linux/regmap.h> 30 33 31 - #include <mach/at91sam9_smc.h> 32 34 #include <asm/gpio.h> 33 35 34 36 #define DRV_NAME "pata_at91" ··· 58 56 int min; 59 57 int max; 60 58 }; 59 + 60 + struct regmap *smc; 61 + 62 + struct at91sam9_smc_generic_fields { 63 + struct regmap_field *setup; 64 + struct regmap_field *pulse; 65 + struct regmap_field *cycle; 66 + struct regmap_field *mode; 67 + } fields; 61 68 62 69 /** 63 70 * adjust_smc_value - adjust value for one of SMC registers. ··· 217 206 { 218 207 int ret = 0; 219 208 int use_iordy; 220 - struct sam9_smc_config smc; 221 209 unsigned int t6z; /* data tristate time in ns */ 222 210 unsigned int cycle; /* SMC Cycle width in MCK ticks */ 223 211 unsigned int setup; /* SMC Setup width in MCK ticks */ ··· 254 244 255 245 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); 256 246 257 - /* SMC Setup Register */ 258 - smc.nwe_setup = smc.nrd_setup = setup; 259 - smc.ncs_write_setup = smc.ncs_read_setup = 0; 260 - /* SMC Pulse Register */ 261 - smc.nwe_pulse = smc.nrd_pulse = pulse; 262 - smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse; 263 - /* SMC Cycle Register */ 264 - smc.write_cycle = smc.read_cycle = cycle; 265 - /* SMC Mode Register*/ 266 - smc.tdf_cycles = tdf_cycles; 267 - smc.mode = info->mode; 268 - 269 - sam9_smc_configure(0, info->cs, &smc); 247 + regmap_fields_write(fields.setup, info->cs, 248 + AT91SAM9_SMC_NRDSETUP(setup) | 249 + AT91SAM9_SMC_NWESETUP(setup) | 250 + AT91SAM9_SMC_NCS_NRDSETUP(0) | 251 + AT91SAM9_SMC_NCS_WRSETUP(0)); 252 + regmap_fields_write(fields.pulse, info->cs, 253 + AT91SAM9_SMC_NRDPULSE(pulse) | 254 + AT91SAM9_SMC_NWEPULSE(pulse) | 255 + AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) | 256 + AT91SAM9_SMC_NCS_WRPULSE(cs_pulse)); 257 + regmap_fields_write(fields.cycle, info->cs, 258 + AT91SAM9_SMC_NRDCYCLE(cycle) | 259 + AT91SAM9_SMC_NWECYCLE(cycle)); 260 + regmap_fields_write(fields.mode, info->cs, info->mode | 261 + AT91_SMC_TDF_(tdf_cycles)); 270 262 } 271 263 272 264 static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) ··· 292 280 { 293 281 struct at91_ide_info *info = dev->link->ap->host->private_data; 294 282 unsigned int consumed; 283 + unsigned int mode; 295 284 unsigned long flags; 296 - struct sam9_smc_config smc; 297 285 298 286 local_irq_save(flags); 299 - sam9_smc_read_mode(0, info->cs, &smc); 287 + regmap_fields_read(fields.mode, info->cs, &mode); 300 288 301 289 /* set 16bit mode before writing data */ 302 - smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16; 303 - sam9_smc_write_mode(0, info->cs, &smc); 290 + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | 291 + AT91_SMC_DBW_16); 304 292 305 293 consumed = ata_sff_data_xfer(dev, buf, buflen, rw); 306 294 307 295 /* restore 8bit mode after data is written */ 308 - smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8; 309 - sam9_smc_write_mode(0, info->cs, &smc); 296 + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) | 297 + AT91_SMC_DBW_8); 310 298 311 299 local_irq_restore(flags); 312 300 return consumed; ··· 323 311 .set_piomode = pata_at91_set_piomode, 324 312 .cable_detect = ata_cable_40wire, 325 313 }; 314 + 315 + static int at91sam9_smc_fields_init(struct device *dev) 316 + { 317 + struct reg_field field = REG_FIELD(0, 0, 31); 318 + 319 + field.id_size = 8; 320 + field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ; 321 + 322 + field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC); 323 + fields.setup = devm_regmap_field_alloc(dev, smc, field); 324 + if (IS_ERR(fields.setup)) 325 + return PTR_ERR(fields.setup); 326 + 327 + field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC); 328 + fields.pulse = devm_regmap_field_alloc(dev, smc, field); 329 + if (IS_ERR(fields.pulse)) 330 + return PTR_ERR(fields.pulse); 331 + 332 + field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC); 333 + fields.cycle = devm_regmap_field_alloc(dev, smc, field); 334 + if (IS_ERR(fields.cycle)) 335 + return PTR_ERR(fields.cycle); 336 + 337 + field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC); 338 + fields.mode = devm_regmap_field_alloc(dev, smc, field); 339 + if (IS_ERR(fields.mode)) 340 + return PTR_ERR(fields.mode); 341 + 342 + return 0; 343 + } 326 344 327 345 static int pata_at91_probe(struct platform_device *pdev) 328 346 { ··· 382 340 } 383 341 384 342 irq = board->irq_pin; 343 + 344 + smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc"); 345 + if (IS_ERR(smc)) 346 + return PTR_ERR(smc); 347 + 348 + ret = at91sam9_smc_fields_init(dev); 349 + if (ret < 0) 350 + return ret; 385 351 386 352 /* init ata host */ 387 353
-1
drivers/pcmcia/Kconfig
··· 277 277 tristate "AT91 CompactFlash Controller" 278 278 depends on PCI 279 279 depends on PCMCIA && ARCH_AT91 280 - depends on !ARCH_MULTIPLATFORM 281 280 help 282 281 Say Y here to support the CompactFlash controller on AT91 chips. 283 282 Or choose M to compile the driver as a module named "at91_cf".
+14 -11
drivers/pcmcia/at91_cf.c
··· 20 20 #include <linux/platform_data/atmel.h> 21 21 #include <linux/io.h> 22 22 #include <linux/sizes.h> 23 + #include <linux/mfd/syscon.h> 24 + #include <linux/mfd/syscon/atmel-mc.h> 23 25 #include <linux/of.h> 24 26 #include <linux/of_device.h> 25 27 #include <linux/of_gpio.h> 28 + #include <linux/regmap.h> 26 29 27 30 #include <pcmcia/ss.h> 28 - 29 - #include <mach/at91rm9200_mc.h> 30 - #include <mach/at91_ramc.h> 31 - 32 31 33 32 /* 34 33 * A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW; ··· 38 39 #define CF_ATTR_PHYS (0) 39 40 #define CF_IO_PHYS (1 << 23) 40 41 #define CF_MEM_PHYS (0x017ff800) 42 + 43 + struct regmap *mc; 41 44 42 45 /*--------------------------------------------------------------------------*/ 43 46 ··· 156 155 157 156 /* 158 157 * Use 16 bit accesses unless/until we need 8-bit i/o space. 159 - */ 160 - csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW; 161 - 162 - /* 158 + * 163 159 * NOTE: this CF controller ignores IOIS16, so we can't really do 164 160 * MAP_AUTOSZ. The 16bit mode allows single byte access on either 165 161 * D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many ··· 167 169 * CF 3.0 spec table 35 also giving the D8-D15 option. 168 170 */ 169 171 if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) { 170 - csr |= AT91_SMC_DBW_8; 172 + csr = AT91_MC_SMC_DBW_8; 171 173 dev_dbg(&cf->pdev->dev, "8bit i/o bus\n"); 172 174 } else { 173 - csr |= AT91_SMC_DBW_16; 175 + csr = AT91_MC_SMC_DBW_16; 174 176 dev_dbg(&cf->pdev->dev, "16bit i/o bus\n"); 175 177 } 176 - at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr); 178 + regmap_update_bits(mc, AT91_MC_SMC_CSR(cf->board->chipselect), 179 + AT91_MC_SMC_DBW, csr); 177 180 178 181 io->start = cf->socket.io_offset; 179 182 io->stop = io->start + SZ_2K - 1; ··· 234 235 board->rst_pin = of_get_gpio(pdev->dev.of_node, 3); 235 236 236 237 pdev->dev.platform_data = board; 238 + 239 + mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc"); 240 + if (IS_ERR(mc)) 241 + return PTR_ERR(mc); 237 242 238 243 return 0; 239 244 }
+144
include/linux/mfd/syscon/atmel-mc.h
··· 1 + /* 2 + * Copyright (C) 2005 Ivan Kokshaysky 3 + * Copyright (C) SAN People 4 + * 5 + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals 6 + * registers. 7 + * Based on AT91RM9200 datasheet revision E. 8 + * 9 + * This program is free software; you can redistribute it and/or modify 10 + * it under the terms of the GNU General Public License as published by 11 + * the Free Software Foundation; either version 2 of the License, or 12 + * (at your option) any later version. 13 + */ 14 + 15 + #ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_ 16 + #define _LINUX_MFD_SYSCON_ATMEL_MC_H_ 17 + 18 + /* Memory Controller */ 19 + #define AT91_MC_RCR 0x00 20 + #define AT91_MC_RCB BIT(0) 21 + 22 + #define AT91_MC_ASR 0x04 23 + #define AT91_MC_UNADD BIT(0) 24 + #define AT91_MC_MISADD BIT(1) 25 + #define AT91_MC_ABTSZ GENMASK(9, 8) 26 + #define AT91_MC_ABTSZ_BYTE (0 << 8) 27 + #define AT91_MC_ABTSZ_HALFWORD (1 << 8) 28 + #define AT91_MC_ABTSZ_WORD (2 << 8) 29 + #define AT91_MC_ABTTYP GENMASK(11, 10) 30 + #define AT91_MC_ABTTYP_DATAREAD (0 << 10) 31 + #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) 32 + #define AT91_MC_ABTTYP_FETCH (2 << 10) 33 + #define AT91_MC_MST(n) BIT(16 + (n)) 34 + #define AT91_MC_SVMST(n) BIT(24 + (n)) 35 + 36 + #define AT91_MC_AASR 0x08 37 + 38 + #define AT91_MC_MPR 0x0c 39 + #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4)) 40 + 41 + /* External Bus Interface (EBI) registers */ 42 + #define AT91_MC_EBI_CSA 0x60 43 + #define AT91_MC_EBI_CS(n) BIT(x) 44 + #define AT91_MC_EBI_NUM_CS 8 45 + 46 + #define AT91_MC_EBI_CFGR 0x64 47 + #define AT91_MC_EBI_DBPUC BIT(0) 48 + 49 + /* Static Memory Controller (SMC) registers */ 50 + #define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4)) 51 + #define AT91_MC_SMC_NWS GENMASK(6, 0) 52 + #define AT91_MC_SMC_NWS_(x) ((x) << 0) 53 + #define AT91_MC_SMC_WSEN BIT(7) 54 + #define AT91_MC_SMC_TDF GENMASK(11, 8) 55 + #define AT91_MC_SMC_TDF_(x) ((x) << 8) 56 + #define AT91_MC_SMC_TDF_MAX 0xf 57 + #define AT91_MC_SMC_BAT BIT(12) 58 + #define AT91_MC_SMC_DBW GENMASK(14, 13) 59 + #define AT91_MC_SMC_DBW_16 (1 << 13) 60 + #define AT91_MC_SMC_DBW_8 (2 << 13) 61 + #define AT91_MC_SMC_DPR BIT(15) 62 + #define AT91_MC_SMC_ACSS GENMASK(17, 16) 63 + #define AT91_MC_SMC_ACSS_(x) ((x) << 16) 64 + #define AT91_MC_SMC_ACSS_MAX 3 65 + #define AT91_MC_SMC_RWSETUP GENMASK(26, 24) 66 + #define AT91_MC_SMC_RWSETUP_(x) ((x) << 24) 67 + #define AT91_MC_SMC_RWHOLD GENMASK(30, 28) 68 + #define AT91_MC_SMC_RWHOLD_(x) ((x) << 28) 69 + #define AT91_MC_SMC_RWHOLDSETUP_MAX 7 70 + 71 + /* SDRAM Controller registers */ 72 + #define AT91_MC_SDRAMC_MR 0x90 73 + #define AT91_MC_SDRAMC_MODE GENMASK(3, 0) 74 + #define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0) 75 + #define AT91_MC_SDRAMC_MODE_NOP (1 << 0) 76 + #define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0) 77 + #define AT91_MC_SDRAMC_MODE_LMR (3 << 0) 78 + #define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0) 79 + #define AT91_MC_SDRAMC_DBW_16 BIT(4) 80 + 81 + #define AT91_MC_SDRAMC_TR 0x94 82 + #define AT91_MC_SDRAMC_COUNT GENMASK(11, 0) 83 + 84 + #define AT91_MC_SDRAMC_CR 0x98 85 + #define AT91_MC_SDRAMC_NC GENMASK(1, 0) 86 + #define AT91_MC_SDRAMC_NC_8 (0 << 0) 87 + #define AT91_MC_SDRAMC_NC_9 (1 << 0) 88 + #define AT91_MC_SDRAMC_NC_10 (2 << 0) 89 + #define AT91_MC_SDRAMC_NC_11 (3 << 0) 90 + #define AT91_MC_SDRAMC_NR GENMASK(3, 2) 91 + #define AT91_MC_SDRAMC_NR_11 (0 << 2) 92 + #define AT91_MC_SDRAMC_NR_12 (1 << 2) 93 + #define AT91_MC_SDRAMC_NR_13 (2 << 2) 94 + #define AT91_MC_SDRAMC_NB BIT(4) 95 + #define AT91_MC_SDRAMC_NB_2 (0 << 4) 96 + #define AT91_MC_SDRAMC_NB_4 (1 << 4) 97 + #define AT91_MC_SDRAMC_CAS GENMASK(6, 5) 98 + #define AT91_MC_SDRAMC_CAS_2 (2 << 5) 99 + #define AT91_MC_SDRAMC_TWR GENMASK(10, 7) 100 + #define AT91_MC_SDRAMC_TRC GENMASK(14, 11) 101 + #define AT91_MC_SDRAMC_TRP GENMASK(18, 15) 102 + #define AT91_MC_SDRAMC_TRCD GENMASK(22, 19) 103 + #define AT91_MC_SDRAMC_TRAS GENMASK(26, 23) 104 + #define AT91_MC_SDRAMC_TXSR GENMASK(30, 27) 105 + 106 + #define AT91_MC_SDRAMC_SRR 0x9c 107 + #define AT91_MC_SDRAMC_SRCB BIT(0) 108 + 109 + #define AT91_MC_SDRAMC_LPR 0xa0 110 + #define AT91_MC_SDRAMC_LPCB BIT(0) 111 + 112 + #define AT91_MC_SDRAMC_IER 0xa4 113 + #define AT91_MC_SDRAMC_IDR 0xa8 114 + #define AT91_MC_SDRAMC_IMR 0xac 115 + #define AT91_MC_SDRAMC_ISR 0xb0 116 + #define AT91_MC_SDRAMC_RES BIT(0) 117 + 118 + /* Burst Flash Controller register */ 119 + #define AT91_MC_BFC_MR 0xc0 120 + #define AT91_MC_BFC_BFCOM GENMASK(1, 0) 121 + #define AT91_MC_BFC_BFCOM_DISABLED (0 << 0) 122 + #define AT91_MC_BFC_BFCOM_ASYNC (1 << 0) 123 + #define AT91_MC_BFC_BFCOM_BURST (2 << 0) 124 + #define AT91_MC_BFC_BFCC GENMASK(3, 2) 125 + #define AT91_MC_BFC_BFCC_MCK (1 << 2) 126 + #define AT91_MC_BFC_BFCC_DIV2 (2 << 2) 127 + #define AT91_MC_BFC_BFCC_DIV4 (3 << 2) 128 + #define AT91_MC_BFC_AVL GENMASK(7, 4) 129 + #define AT91_MC_BFC_PAGES GENMASK(10, 8) 130 + #define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8) 131 + #define AT91_MC_BFC_PAGES_16 (1 << 8) 132 + #define AT91_MC_BFC_PAGES_32 (2 << 8) 133 + #define AT91_MC_BFC_PAGES_64 (3 << 8) 134 + #define AT91_MC_BFC_PAGES_128 (4 << 8) 135 + #define AT91_MC_BFC_PAGES_256 (5 << 8) 136 + #define AT91_MC_BFC_PAGES_512 (6 << 8) 137 + #define AT91_MC_BFC_PAGES_1024 (7 << 8) 138 + #define AT91_MC_BFC_OEL GENMASK(13, 12) 139 + #define AT91_MC_BFC_BAAEN BIT(16) 140 + #define AT91_MC_BFC_BFOEH BIT(17) 141 + #define AT91_MC_BFC_MUXEN BIT(18) 142 + #define AT91_MC_BFC_RDYEN BIT(19) 143 + 144 + #endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
-63
include/soc/at91/at91rm9200_sdramc.h
··· 1 - /* 2 - * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h 3 - * 4 - * Copyright (C) 2005 Ivan Kokshaysky 5 - * Copyright (C) SAN People 6 - * 7 - * Memory Controllers (SDRAMC only) - System peripherals registers. 8 - * Based on AT91RM9200 datasheet revision E. 9 - * 10 - * This program is free software; you can redistribute it and/or modify 11 - * it under the terms of the GNU General Public License as published by 12 - * the Free Software Foundation; either version 2 of the License, or 13 - * (at your option) any later version. 14 - */ 15 - 16 - #ifndef AT91RM9200_SDRAMC_H 17 - #define AT91RM9200_SDRAMC_H 18 - 19 - /* SDRAM Controller registers */ 20 - #define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */ 21 - #define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */ 22 - #define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0) 23 - #define AT91RM9200_SDRAMC_MODE_NOP (1 << 0) 24 - #define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0) 25 - #define AT91RM9200_SDRAMC_MODE_LMR (3 << 0) 26 - #define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0) 27 - #define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */ 28 - #define AT91RM9200_SDRAMC_DBW_32 (0 << 4) 29 - #define AT91RM9200_SDRAMC_DBW_16 (1 << 4) 30 - 31 - #define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */ 32 - #define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ 33 - 34 - #define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */ 35 - #define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */ 36 - #define AT91RM9200_SDRAMC_NC_8 (0 << 0) 37 - #define AT91RM9200_SDRAMC_NC_9 (1 << 0) 38 - #define AT91RM9200_SDRAMC_NC_10 (2 << 0) 39 - #define AT91RM9200_SDRAMC_NC_11 (3 << 0) 40 - #define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */ 41 - #define AT91RM9200_SDRAMC_NR_11 (0 << 2) 42 - #define AT91RM9200_SDRAMC_NR_12 (1 << 2) 43 - #define AT91RM9200_SDRAMC_NR_13 (2 << 2) 44 - #define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */ 45 - #define AT91RM9200_SDRAMC_NB_2 (0 << 4) 46 - #define AT91RM9200_SDRAMC_NB_4 (1 << 4) 47 - #define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */ 48 - #define AT91RM9200_SDRAMC_CAS_2 (2 << 5) 49 - #define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ 50 - #define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ 51 - #define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ 52 - #define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ 53 - #define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ 54 - #define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ 55 - 56 - #define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */ 57 - #define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */ 58 - #define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */ 59 - #define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */ 60 - #define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */ 61 - #define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */ 62 - 63 - #endif