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amd-xgbe: Update DMA coherency values

Based on the IOMMU configuration, the current cache control settings can
result in possible coherency issues. The hardware team has recommended
new settings for the PCI device path to eliminate the issue.

Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance")
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Shyam Sundar S K and committed by
David S. Miller d7513508 3e6fdeb2

+3 -3
+3 -3
drivers/net/ethernet/amd/xgbe/xgbe.h
··· 180 180 #define XGBE_DMA_SYS_AWCR 0x30303030 181 181 182 182 /* DMA cache settings - PCI device */ 183 - #define XGBE_DMA_PCI_ARCR 0x00000003 184 - #define XGBE_DMA_PCI_AWCR 0x13131313 185 - #define XGBE_DMA_PCI_AWARCR 0x00000313 183 + #define XGBE_DMA_PCI_ARCR 0x000f0f0f 184 + #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 185 + #define XGBE_DMA_PCI_AWARCR 0x00000f0f 186 186 187 187 /* DMA channel interrupt modes */ 188 188 #define XGBE_IRQ_MODE_EDGE 0