Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu/gfx9: store the eop gpu addr in the ring structure

Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

+6 -8
+6 -8
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 613 613 struct amdgpu_ring *ring, 614 614 struct amdgpu_irq_src *irq) 615 615 { 616 + struct amdgpu_kiq *kiq = &adev->gfx.kiq; 616 617 int r = 0; 617 618 618 619 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); ··· 634 633 635 634 irq->data = ring; 636 635 ring->queue = 0; 636 + ring->eop_gpu_addr = kiq->eop_gpu_addr; 637 637 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); 638 638 r = amdgpu_ring_init(adev, ring, 1024, 639 639 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); ··· 1096 1094 ring->me = 1; /* first MEC */ 1097 1095 ring->pipe = i / 8; 1098 1096 ring->queue = i % 8; 1097 + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 1099 1098 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 1100 1099 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 1101 1100 /* type-2 packets are deprecated on MEC, use type-3 instead */ ··· 1895 1892 } 1896 1893 1897 1894 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring, 1898 - struct v9_mqd *mqd, 1899 - uint64_t eop_gpu_addr) 1895 + struct v9_mqd *mqd) 1900 1896 { 1901 1897 struct amdgpu_device *adev = ring->adev; 1902 1898 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; ··· 1909 1907 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1910 1908 mqd->compute_misc_reserved = 0x00000003; 1911 1909 1912 - eop_base_addr = eop_gpu_addr >> 8; 1910 + eop_base_addr = ring->eop_gpu_addr >> 8; 1913 1911 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1914 1912 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1915 1913 ··· 2136 2134 { 2137 2135 struct amdgpu_device *adev = ring->adev; 2138 2136 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 2139 - uint64_t eop_gpu_addr; 2140 2137 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); 2141 2138 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2142 2139 2143 2140 if (is_kiq) { 2144 - eop_gpu_addr = kiq->eop_gpu_addr; 2145 2141 gfx_v9_0_kiq_setting(&kiq->ring); 2146 2142 } else { 2147 - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 2148 - ring->queue * MEC_HPD_SIZE; 2149 2143 mqd_idx = ring - &adev->gfx.compute_ring[0]; 2150 2144 } 2151 2145 ··· 2149 2151 memset((void *)mqd, 0, sizeof(*mqd)); 2150 2152 mutex_lock(&adev->srbm_mutex); 2151 2153 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2152 - gfx_v9_0_mqd_init(ring, mqd, eop_gpu_addr); 2154 + gfx_v9_0_mqd_init(ring, mqd); 2153 2155 if (is_kiq) 2154 2156 gfx_v9_0_kiq_init_register(ring, mqd); 2155 2157 soc15_grbm_select(adev, 0, 0, 0, 0);