tjh.dev / kernel
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ARM: dts: rockchip: change gpio nodenames

Currently all gpio nodenames are sort of identical to there label.
Nodenames should be of a generic type, so change them all.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20211007144019.7461-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Johan Jonker and committed by
Heiko Stuebner d7077ac5 3e6f8124

+30 -30
+3 -3
arch/arm/boot/dts/rk3036.dtsi
··· 575 575 #size-cells = <1>; 576 576 ranges; 577 577 578 - gpio0: gpio0@2007c000 { 578 + gpio0: gpio@2007c000 { 579 579 compatible = "rockchip,gpio-bank"; 580 580 reg = <0x2007c000 0x100>; 581 581 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; ··· 588 588 #interrupt-cells = <2>; 589 589 }; 590 590 591 - gpio1: gpio1@20080000 { 591 + gpio1: gpio@20080000 { 592 592 compatible = "rockchip,gpio-bank"; 593 593 reg = <0x20080000 0x100>; 594 594 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ··· 601 601 #interrupt-cells = <2>; 602 602 }; 603 603 604 - gpio2: gpio2@20084000 { 604 + gpio2: gpio@20084000 { 605 605 compatible = "rockchip,gpio-bank"; 606 606 reg = <0x20084000 0x100>; 607 607 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+6 -6
arch/arm/boot/dts/rk3066a.dtsi
··· 272 272 #size-cells = <1>; 273 273 ranges; 274 274 275 - gpio0: gpio0@20034000 { 275 + gpio0: gpio@20034000 { 276 276 compatible = "rockchip,gpio-bank"; 277 277 reg = <0x20034000 0x100>; 278 278 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; ··· 285 285 #interrupt-cells = <2>; 286 286 }; 287 287 288 - gpio1: gpio1@2003c000 { 288 + gpio1: gpio@2003c000 { 289 289 compatible = "rockchip,gpio-bank"; 290 290 reg = <0x2003c000 0x100>; 291 291 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; ··· 298 298 #interrupt-cells = <2>; 299 299 }; 300 300 301 - gpio2: gpio2@2003e000 { 301 + gpio2: gpio@2003e000 { 302 302 compatible = "rockchip,gpio-bank"; 303 303 reg = <0x2003e000 0x100>; 304 304 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; ··· 311 311 #interrupt-cells = <2>; 312 312 }; 313 313 314 - gpio3: gpio3@20080000 { 314 + gpio3: gpio@20080000 { 315 315 compatible = "rockchip,gpio-bank"; 316 316 reg = <0x20080000 0x100>; 317 317 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; ··· 324 324 #interrupt-cells = <2>; 325 325 }; 326 326 327 - gpio4: gpio4@20084000 { 327 + gpio4: gpio@20084000 { 328 328 compatible = "rockchip,gpio-bank"; 329 329 reg = <0x20084000 0x100>; 330 330 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; ··· 337 337 #interrupt-cells = <2>; 338 338 }; 339 339 340 - gpio6: gpio6@2000a000 { 340 + gpio6: gpio@2000a000 { 341 341 compatible = "rockchip,gpio-bank"; 342 342 reg = <0x2000a000 0x100>; 343 343 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+4 -4
arch/arm/boot/dts/rk3188.dtsi
··· 223 223 #size-cells = <1>; 224 224 ranges; 225 225 226 - gpio0: gpio0@2000a000 { 226 + gpio0: gpio@2000a000 { 227 227 compatible = "rockchip,rk3188-gpio-bank0"; 228 228 reg = <0x2000a000 0x100>; 229 229 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; ··· 236 236 #interrupt-cells = <2>; 237 237 }; 238 238 239 - gpio1: gpio1@2003c000 { 239 + gpio1: gpio@2003c000 { 240 240 compatible = "rockchip,gpio-bank"; 241 241 reg = <0x2003c000 0x100>; 242 242 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; ··· 249 249 #interrupt-cells = <2>; 250 250 }; 251 251 252 - gpio2: gpio2@2003e000 { 252 + gpio2: gpio@2003e000 { 253 253 compatible = "rockchip,gpio-bank"; 254 254 reg = <0x2003e000 0x100>; 255 255 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; ··· 262 262 #interrupt-cells = <2>; 263 263 }; 264 264 265 - gpio3: gpio3@20080000 { 265 + gpio3: gpio@20080000 { 266 266 compatible = "rockchip,gpio-bank"; 267 267 reg = <0x20080000 0x100>; 268 268 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+4 -4
arch/arm/boot/dts/rk322x.dtsi
··· 946 946 #size-cells = <1>; 947 947 ranges; 948 948 949 - gpio0: gpio0@11110000 { 949 + gpio0: gpio@11110000 { 950 950 compatible = "rockchip,gpio-bank"; 951 951 reg = <0x11110000 0x100>; 952 952 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; ··· 959 959 #interrupt-cells = <2>; 960 960 }; 961 961 962 - gpio1: gpio1@11120000 { 962 + gpio1: gpio@11120000 { 963 963 compatible = "rockchip,gpio-bank"; 964 964 reg = <0x11120000 0x100>; 965 965 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; ··· 972 972 #interrupt-cells = <2>; 973 973 }; 974 974 975 - gpio2: gpio2@11130000 { 975 + gpio2: gpio@11130000 { 976 976 compatible = "rockchip,gpio-bank"; 977 977 reg = <0x11130000 0x100>; 978 978 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; ··· 985 985 #interrupt-cells = <2>; 986 986 }; 987 987 988 - gpio3: gpio3@11140000 { 988 + gpio3: gpio@11140000 { 989 989 compatible = "rockchip,gpio-bank"; 990 990 reg = <0x11140000 0x100>; 991 991 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+9 -9
arch/arm/boot/dts/rk3288.dtsi
··· 1422 1422 #size-cells = <2>; 1423 1423 ranges; 1424 1424 1425 - gpio0: gpio0@ff750000 { 1425 + gpio0: gpio@ff750000 { 1426 1426 compatible = "rockchip,gpio-bank"; 1427 1427 reg = <0x0 0xff750000 0x0 0x100>; 1428 1428 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; ··· 1435 1435 #interrupt-cells = <2>; 1436 1436 }; 1437 1437 1438 - gpio1: gpio1@ff780000 { 1438 + gpio1: gpio@ff780000 { 1439 1439 compatible = "rockchip,gpio-bank"; 1440 1440 reg = <0x0 0xff780000 0x0 0x100>; 1441 1441 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; ··· 1448 1448 #interrupt-cells = <2>; 1449 1449 }; 1450 1450 1451 - gpio2: gpio2@ff790000 { 1451 + gpio2: gpio@ff790000 { 1452 1452 compatible = "rockchip,gpio-bank"; 1453 1453 reg = <0x0 0xff790000 0x0 0x100>; 1454 1454 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; ··· 1461 1461 #interrupt-cells = <2>; 1462 1462 }; 1463 1463 1464 - gpio3: gpio3@ff7a0000 { 1464 + gpio3: gpio@ff7a0000 { 1465 1465 compatible = "rockchip,gpio-bank"; 1466 1466 reg = <0x0 0xff7a0000 0x0 0x100>; 1467 1467 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; ··· 1474 1474 #interrupt-cells = <2>; 1475 1475 }; 1476 1476 1477 - gpio4: gpio4@ff7b0000 { 1477 + gpio4: gpio@ff7b0000 { 1478 1478 compatible = "rockchip,gpio-bank"; 1479 1479 reg = <0x0 0xff7b0000 0x0 0x100>; 1480 1480 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; ··· 1487 1487 #interrupt-cells = <2>; 1488 1488 }; 1489 1489 1490 - gpio5: gpio5@ff7c0000 { 1490 + gpio5: gpio@ff7c0000 { 1491 1491 compatible = "rockchip,gpio-bank"; 1492 1492 reg = <0x0 0xff7c0000 0x0 0x100>; 1493 1493 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; ··· 1500 1500 #interrupt-cells = <2>; 1501 1501 }; 1502 1502 1503 - gpio6: gpio6@ff7d0000 { 1503 + gpio6: gpio@ff7d0000 { 1504 1504 compatible = "rockchip,gpio-bank"; 1505 1505 reg = <0x0 0xff7d0000 0x0 0x100>; 1506 1506 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; ··· 1513 1513 #interrupt-cells = <2>; 1514 1514 }; 1515 1515 1516 - gpio7: gpio7@ff7e0000 { 1516 + gpio7: gpio@ff7e0000 { 1517 1517 compatible = "rockchip,gpio-bank"; 1518 1518 reg = <0x0 0xff7e0000 0x0 0x100>; 1519 1519 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; ··· 1526 1526 #interrupt-cells = <2>; 1527 1527 }; 1528 1528 1529 - gpio8: gpio8@ff7f0000 { 1529 + gpio8: gpio@ff7f0000 { 1530 1530 compatible = "rockchip,gpio-bank"; 1531 1531 reg = <0x0 0xff7f0000 0x0 0x100>; 1532 1532 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+4 -4
arch/arm/boot/dts/rv1108.dtsi
··· 600 600 #size-cells = <1>; 601 601 ranges; 602 602 603 - gpio0: gpio0@20030000 { 603 + gpio0: gpio@20030000 { 604 604 compatible = "rockchip,gpio-bank"; 605 605 reg = <0x20030000 0x100>; 606 606 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; ··· 613 613 #interrupt-cells = <2>; 614 614 }; 615 615 616 - gpio1: gpio1@10310000 { 616 + gpio1: gpio@10310000 { 617 617 compatible = "rockchip,gpio-bank"; 618 618 reg = <0x10310000 0x100>; 619 619 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ··· 626 626 #interrupt-cells = <2>; 627 627 }; 628 628 629 - gpio2: gpio2@10320000 { 629 + gpio2: gpio@10320000 { 630 630 compatible = "rockchip,gpio-bank"; 631 631 reg = <0x10320000 0x100>; 632 632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ··· 639 639 #interrupt-cells = <2>; 640 640 }; 641 641 642 - gpio3: gpio3@10330000 { 642 + gpio3: gpio@10330000 { 643 643 compatible = "rockchip,gpio-bank"; 644 644 reg = <0x10330000 0x100>; 645 645 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;