tjh.dev / kernel
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drm/amd/display: dce11.x /dce12 update formula input

[Description]
1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update)
2. using memory type to convert UMC's MCLK to Yclk.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Charlene Liu and committed by
Alex Deucher d6bbece2 0417df16

+27 -13
+5 -2
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
··· 98 98 struct dc_stream_state *stream = context->streams[j]; 99 99 uint32_t vertical_blank_in_pixels = 0; 100 100 uint32_t vertical_blank_time = 0; 101 + uint32_t vertical_total_min = stream->timing.v_total; 102 + struct dc_crtc_timing_adjust adjust = stream->adjust; 103 + if (adjust.v_total_max != adjust.v_total_min) 104 + vertical_total_min = adjust.v_total_min; 101 105 102 106 vertical_blank_in_pixels = stream->timing.h_total * 103 - (stream->timing.v_total 107 + (vertical_total_min 104 108 - stream->timing.v_addressable); 105 - 106 109 vertical_blank_time = vertical_blank_in_pixels 107 110 * 10000 / stream->timing.pix_clk_100hz; 108 111
+2 -2
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
··· 148 148 pte->min_pte_before_flip_horiz_scan; 149 149 150 150 REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 151 - GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff); 151 + GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0x7f); 152 152 153 153 REG_UPDATE_3(DVMM_PTE_CONTROL, 154 154 DVMM_PAGE_WIDTH, page_width, ··· 157 157 158 158 REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, 159 159 DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk, 160 - DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff); 160 + DVMM_MAX_PTE_REQ_OUTSTANDING, 0x7f); 161 161 } 162 162 163 163 static void program_urgency_watermark(
+10 -6
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
··· 987 987 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 988 988 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 989 989 struct dm_pp_clock_levels clks = {0}; 990 + int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 991 + 992 + if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) 993 + memory_type_multiplier = MEMORY_TYPE_HBM; 990 994 991 995 /*do system clock TODO PPLIB: after PPLIB implement, 992 996 * then remove old way ··· 1030 1026 &clks); 1031 1027 1032 1028 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1033 - clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1029 + clks.clocks_in_khz[0] * memory_type_multiplier, 1000); 1034 1030 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1035 - clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, 1031 + clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, 1036 1032 1000); 1037 1033 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1038 - clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, 1034 + clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, 1039 1035 1000); 1040 1036 1041 1037 return; ··· 1071 1067 * YCLK = UMACLK*m_memoryTypeMultiplier 1072 1068 */ 1073 1069 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1074 - mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 1070 + mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 1075 1071 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1076 - mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1072 + mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 1077 1073 1000); 1078 1074 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1079 - mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1075 + mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 1080 1076 1000); 1081 1077 1082 1078 /* Now notify PPLib/SMU about which Watermarks sets they should select
+8 -3
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
··· 847 847 int i; 848 848 unsigned int clk; 849 849 unsigned int latency; 850 + /*original logic in dal3*/ 851 + int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 850 852 851 853 /*do system clock*/ 852 854 if (!dm_pp_get_clock_levels_by_type_with_latency( ··· 907 905 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 908 906 * YCLK = UMACLK*m_memoryTypeMultiplier 909 907 */ 908 + if (dc->bw_vbios->memory_type == bw_def_hbm) 909 + memory_type_multiplier = MEMORY_TYPE_HBM; 910 + 910 911 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 911 - mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); 912 + mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 912 913 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 913 - mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 914 + mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 914 915 1000); 915 916 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 916 - mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 917 + mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 917 918 1000); 918 919 919 920 /* Now notify PPLib/SMU about which Watermarks sets they should select
+2
drivers/gpu/drm/amd/display/dc/inc/resource.h
··· 31 31 #include "dm_pp_smu.h" 32 32 33 33 #define MEMORY_TYPE_MULTIPLIER_CZ 4 34 + #define MEMORY_TYPE_HBM 2 35 + 34 36 35 37 enum dce_version resource_parse_asic_id( 36 38 struct hw_asic_id asic_id);