tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'lpc32xx/multiplatform' into arm/soc

I revisited some older patches here, getting two of the remaining
ARM platforms to build with ARCH_MULTIPLATFORM like most others do.

In case of lpc32xx, I created a new set of patches, which seemed
easier than digging out what I did for an older release many
years ago.

* lpc32xx/multiplatform:
ARM: lpc32xx: allow multiplatform build
ARM: lpc32xx: clean up header files
serial: lpc32xx: allow compile testing
net: lpc-enet: allow compile testing
net: lpc-enet: fix printk format strings
net: lpc-enet: fix badzero.cocci warnings
net: lpc-enet: move phy setup into platform code
net: lpc-enet: factor out iram access
gpio: lpc32xx: allow building on non-lpc32xx targets
serial: lpc32xx_hs: allow compile-testing
watchdog: pnx4008_wdt: allow compile-testing
usb: udc: lpc32xx: allow compile-testing
usb: ohci-nxp: enable compile-testing

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann d64a1fd8 3584be9e

+242 -272
+2 -15
arch/arm/Kconfig
··· 424 424 help 425 425 Support for the Marvell Dove SoC 88AP510 426 426 427 - config ARCH_LPC32XX 428 - bool "NXP LPC32XX" 429 - select ARM_AMBA 430 - select CLKDEV_LOOKUP 431 - select CLKSRC_LPC32XX 432 - select COMMON_CLK 433 - select CPU_ARM926T 434 - select GENERIC_CLOCKEVENTS 435 - select GENERIC_IRQ_MULTI_HANDLER 436 - select GPIOLIB 437 - select SPARSE_IRQ 438 - select USE_OF 439 - help 440 - Support for the NXP LPC32XX family of processors 441 - 442 427 config ARCH_PXA 443 428 bool "PXA2xx/PXA3xx-based" 444 429 depends on MMU ··· 670 685 source "arch/arm/mach-ixp4xx/Kconfig" 671 686 672 687 source "arch/arm/mach-keystone/Kconfig" 688 + 689 + source "arch/arm/mach-lpc32xx/Kconfig" 673 690 674 691 source "arch/arm/mach-mediatek/Kconfig" 675 692
+2
arch/arm/configs/lpc32xx_defconfig
··· 12 12 CONFIG_SYSCTL_SYSCALL=y 13 13 CONFIG_EMBEDDED=y 14 14 CONFIG_SLAB=y 15 + # CONFIG_ARCH_MULTI_V7 is not set 15 16 CONFIG_ARCH_LPC32XX=y 16 17 CONFIG_AEABI=y 17 18 CONFIG_ZBOOT_ROM_TEXT=0x0 ··· 94 93 # CONFIG_HW_RANDOM is not set 95 94 CONFIG_I2C_CHARDEV=y 96 95 CONFIG_I2C_PNX=y 96 + CONFIG_GPIO_LPC32XX=y 97 97 CONFIG_SPI=y 98 98 CONFIG_SPI_PL022=y 99 99 CONFIG_GPIO_SYSFS=y
+11
arch/arm/mach-lpc32xx/Kconfig
··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + 3 + config ARCH_LPC32XX 4 + bool "NXP LPC32XX" 5 + depends on ARCH_MULTI_V5 6 + select ARM_AMBA 7 + select CLKSRC_LPC32XX 8 + select CPU_ARM926T 9 + select GPIOLIB 10 + help 11 + Support for the NXP LPC32XX family of processors
+20 -4
arch/arm/mach-lpc32xx/common.c
··· 8 8 */ 9 9 10 10 #include <linux/init.h> 11 + #include <linux/soc/nxp/lpc32xx-misc.h> 11 12 12 13 #include <asm/mach/map.h> 13 14 #include <asm/system_info.h> 14 15 15 - #include <mach/hardware.h> 16 - #include <mach/platform.h> 16 + #include "lpc32xx.h" 17 17 #include "common.h" 18 18 19 19 /* ··· 32 32 */ 33 33 #define LPC32XX_IRAM_BANK_SIZE SZ_128K 34 34 static u32 iram_size; 35 - u32 lpc32xx_return_iram_size(void) 35 + u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) 36 36 { 37 37 if (iram_size == 0) { 38 38 u32 savedval1, savedval2; ··· 53 53 } else 54 54 iram_size = LPC32XX_IRAM_BANK_SIZE * 2; 55 55 } 56 + if (dmaaddr) 57 + *dmaaddr = LPC32XX_IRAM_BASE; 58 + if (mapbase) 59 + *mapbase = io_p2v(LPC32XX_IRAM_BASE); 56 60 57 61 return iram_size; 58 62 } 59 - EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size); 63 + EXPORT_SYMBOL_GPL(lpc32xx_return_iram); 64 + 65 + void lpc32xx_set_phy_interface_mode(phy_interface_t mode) 66 + { 67 + u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); 68 + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; 69 + if (mode == PHY_INTERFACE_MODE_MII) 70 + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; 71 + else 72 + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; 73 + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); 74 + } 75 + EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode); 60 76 61 77 static struct map_desc lpc32xx_io_desc[] __initdata = { 62 78 {
-1
arch/arm/mach-lpc32xx/common.h
··· 23 23 */ 24 24 extern void lpc32xx_get_uid(u32 devid[4]); 25 25 26 - extern u32 lpc32xx_return_iram_size(void); 27 26 /* 28 27 * Pointers used for sizing and copying suspend function data 29 28 */
-15
arch/arm/mach-lpc32xx/include/mach/board.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * arm/arch/mach-lpc32xx/include/mach/board.h 4 - * 5 - * Author: Kevin Wells <kevin.wells@nxp.com> 6 - * 7 - * Copyright (C) 2010 NXP Semiconductors 8 - */ 9 - 10 - #ifndef __ASM_ARCH_BOARD_H 11 - #define __ASM_ARCH_BOARD_H 12 - 13 - extern u32 lpc32xx_return_iram_size(void); 14 - 15 - #endif /* __ASM_ARCH_BOARD_H */
-28
arch/arm/mach-lpc32xx/include/mach/entry-macro.S
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S 4 - * 5 - * Author: Kevin Wells <kevin.wells@nxp.com> 6 - * 7 - * Copyright (C) 2010 NXP Semiconductors 8 - */ 9 - 10 - #include <mach/hardware.h> 11 - #include <mach/platform.h> 12 - 13 - #define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 14 - 15 - .macro get_irqnr_preamble, base, tmp 16 - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) 17 - .endm 18 - 19 - /* 20 - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR 21 - * as set if an interrupt is pending. 22 - */ 23 - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 24 - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] 25 - clz \irqnr, \irqstat 26 - rsb \irqnr, \irqnr, #31 27 - teq \irqstat, #0 28 - .endm
-25
arch/arm/mach-lpc32xx/include/mach/hardware.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * arch/arm/mach-lpc32xx/include/mach/hardware.h 4 - * 5 - * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> 6 - */ 7 - 8 - #ifndef __ASM_ARCH_HARDWARE_H 9 - #define __ASM_ARCH_HARDWARE_H 10 - 11 - /* 12 - * Start of virtual addresses for IO devices 13 - */ 14 - #define IO_BASE 0xF0000000 15 - 16 - /* 17 - * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 18 - */ 19 - #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ 20 - IO_BASE) 21 - 22 - #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) 23 - #define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) 24 - 25 - #endif
+16 -2
arch/arm/mach-lpc32xx/include/mach/platform.h arch/arm/mach-lpc32xx/lpc32xx.h
··· 7 7 * Copyright (C) 2010 NXP Semiconductors 8 8 */ 9 9 10 - #ifndef __ASM_ARCH_PLATFORM_H 11 - #define __ASM_ARCH_PLATFORM_H 10 + #ifndef __ARM_LPC32XX_H 11 + #define __ARM_LPC32XX_H 12 12 13 13 #define _SBF(f, v) ((v) << (f)) 14 14 #define _BIT(n) _SBF(n, 1) ··· 699 699 #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) 700 700 #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) 701 701 #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) 702 + 703 + /* 704 + * Start of virtual addresses for IO devices 705 + */ 706 + #define IO_BASE 0xF0000000 707 + 708 + /* 709 + * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 710 + */ 711 + #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ 712 + IO_BASE) 713 + 714 + #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) 715 + #define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) 702 716 703 717 #endif
-50
arch/arm/mach-lpc32xx/include/mach/uncompress.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 - /* 3 - * arch/arm/mach-lpc32xx/include/mach/uncompress.h 4 - * 5 - * Author: Kevin Wells <kevin.wells@nxp.com> 6 - * 7 - * Copyright (C) 2010 NXP Semiconductors 8 - */ 9 - 10 - #ifndef __ASM_ARM_ARCH_UNCOMPRESS_H 11 - #define __ASM_ARM_ARCH_UNCOMPRESS_H 12 - 13 - #include <linux/io.h> 14 - 15 - #include <mach/hardware.h> 16 - #include <mach/platform.h> 17 - 18 - /* 19 - * Uncompress output is hardcoded to standard UART 5 20 - */ 21 - 22 - #define UART_FIFO_CTL_TX_RESET (1 << 2) 23 - #define UART_STATUS_TX_MT (1 << 6) 24 - 25 - #define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) 26 - 27 - #define LPC32XX_UART_DLLFIFO_O 0x00 28 - #define LPC32XX_UART_IIRFCR_O 0x08 29 - #define LPC32XX_UART_LSR_O 0x14 30 - 31 - static inline void putc(int ch) 32 - { 33 - /* Wait for transmit FIFO to empty */ 34 - while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & 35 - UART_STATUS_TX_MT) == 0) 36 - ; 37 - 38 - __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); 39 - } 40 - 41 - static inline void flush(void) 42 - { 43 - __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | 44 - UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); 45 - } 46 - 47 - /* NULL functions; we don't presently need them */ 48 - #define arch_decomp_setup() 49 - 50 - #endif
+1 -2
arch/arm/mach-lpc32xx/pm.c
··· 70 70 71 71 #include <asm/cacheflush.h> 72 72 73 - #include <mach/hardware.h> 74 - #include <mach/platform.h> 73 + #include "lpc32xx.h" 75 74 #include "common.h" 76 75 77 76 #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
+31 -2
arch/arm/mach-lpc32xx/serial.c
··· 16 16 #include <linux/clk.h> 17 17 #include <linux/io.h> 18 18 19 - #include <mach/hardware.h> 20 - #include <mach/platform.h> 19 + #include "lpc32xx.h" 21 20 #include "common.h" 22 21 23 22 #define LPC32XX_SUART_FIFO_SIZE 64 ··· 58 59 .mapbase = LPC32XX_UART6_BASE, 59 60 }, 60 61 }; 62 + 63 + /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ 64 + void lpc32xx_loopback_set(resource_size_t mapbase, int state) 65 + { 66 + int bit; 67 + u32 tmp; 68 + 69 + switch (mapbase) { 70 + case LPC32XX_HS_UART1_BASE: 71 + bit = 0; 72 + break; 73 + case LPC32XX_HS_UART2_BASE: 74 + bit = 1; 75 + break; 76 + case LPC32XX_HS_UART7_BASE: 77 + bit = 6; 78 + break; 79 + default: 80 + WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); 81 + return; 82 + } 83 + 84 + tmp = readl(LPC32XX_UARTCTL_CLOOP); 85 + if (state) 86 + tmp |= (1 << bit); 87 + else 88 + tmp &= ~(1 << bit); 89 + writel(tmp, LPC32XX_UARTCTL_CLOOP); 90 + } 91 + EXPORT_SYMBOL_GPL(lpc32xx_loopback_set); 61 92 62 93 void __init lpc32xx_serial_init(void) 63 94 {
+1 -2
arch/arm/mach-lpc32xx/suspend.S
··· 11 11 */ 12 12 #include <linux/linkage.h> 13 13 #include <asm/assembler.h> 14 - #include <mach/platform.h> 15 - #include <mach/hardware.h> 14 + #include "lpc32xx.h" 16 15 17 16 /* Using named register defines makes the code easier to follow */ 18 17 #define WORK1_REG r0
+7
drivers/gpio/Kconfig
··· 311 311 Select this option to enable GPIO driver for 312 312 NXP LPC18XX/43XX devices. 313 313 314 + config GPIO_LPC32XX 315 + tristate "NXP LPC32XX GPIO support" 316 + depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST) 317 + help 318 + Select this option to enable GPIO driver for 319 + NXP LPC32XX devices. 320 + 314 321 config GPIO_LYNXPOINT 315 322 tristate "Intel Lynxpoint GPIO support" 316 323 depends on ACPI && X86
+1 -1
drivers/gpio/Makefile
··· 74 74 obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o 75 75 obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o 76 76 obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o 77 - obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o 77 + obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o 78 78 obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o 79 79 obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o 80 80 obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
+68 -50
drivers/gpio/gpio-lpc32xx.c
··· 16 16 #include <linux/platform_device.h> 17 17 #include <linux/module.h> 18 18 19 - #include <mach/hardware.h> 20 - #include <mach/platform.h> 21 - 22 - #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 23 - #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 24 - #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 25 - #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 26 - #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 27 - #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 28 - #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 29 - #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 30 - #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 31 - #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 32 - #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 33 - #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 34 - #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 35 - #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 36 - #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 37 - #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 38 - #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 39 - #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 40 - #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 41 - #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 42 - #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 43 - #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 44 - #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 45 - #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 46 - #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 47 - #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 48 - #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 19 + #define LPC32XX_GPIO_P3_INP_STATE (0x000) 20 + #define LPC32XX_GPIO_P3_OUTP_SET (0x004) 21 + #define LPC32XX_GPIO_P3_OUTP_CLR (0x008) 22 + #define LPC32XX_GPIO_P3_OUTP_STATE (0x00C) 23 + #define LPC32XX_GPIO_P2_DIR_SET (0x010) 24 + #define LPC32XX_GPIO_P2_DIR_CLR (0x014) 25 + #define LPC32XX_GPIO_P2_DIR_STATE (0x018) 26 + #define LPC32XX_GPIO_P2_INP_STATE (0x01C) 27 + #define LPC32XX_GPIO_P2_OUTP_SET (0x020) 28 + #define LPC32XX_GPIO_P2_OUTP_CLR (0x024) 29 + #define LPC32XX_GPIO_P2_MUX_SET (0x028) 30 + #define LPC32XX_GPIO_P2_MUX_CLR (0x02C) 31 + #define LPC32XX_GPIO_P2_MUX_STATE (0x030) 32 + #define LPC32XX_GPIO_P0_INP_STATE (0x040) 33 + #define LPC32XX_GPIO_P0_OUTP_SET (0x044) 34 + #define LPC32XX_GPIO_P0_OUTP_CLR (0x048) 35 + #define LPC32XX_GPIO_P0_OUTP_STATE (0x04C) 36 + #define LPC32XX_GPIO_P0_DIR_SET (0x050) 37 + #define LPC32XX_GPIO_P0_DIR_CLR (0x054) 38 + #define LPC32XX_GPIO_P0_DIR_STATE (0x058) 39 + #define LPC32XX_GPIO_P1_INP_STATE (0x060) 40 + #define LPC32XX_GPIO_P1_OUTP_SET (0x064) 41 + #define LPC32XX_GPIO_P1_OUTP_CLR (0x068) 42 + #define LPC32XX_GPIO_P1_OUTP_STATE (0x06C) 43 + #define LPC32XX_GPIO_P1_DIR_SET (0x070) 44 + #define LPC32XX_GPIO_P1_DIR_CLR (0x074) 45 + #define LPC32XX_GPIO_P1_DIR_STATE (0x078) 49 46 50 47 #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 51 48 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) ··· 69 72 #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) 70 73 71 74 struct gpio_regs { 72 - void __iomem *inp_state; 73 - void __iomem *outp_state; 74 - void __iomem *outp_set; 75 - void __iomem *outp_clr; 76 - void __iomem *dir_set; 77 - void __iomem *dir_clr; 75 + unsigned long inp_state; 76 + unsigned long outp_state; 77 + unsigned long outp_set; 78 + unsigned long outp_clr; 79 + unsigned long dir_set; 80 + unsigned long dir_clr; 78 81 }; 79 82 80 83 /* ··· 162 165 struct lpc32xx_gpio_chip { 163 166 struct gpio_chip chip; 164 167 struct gpio_regs *gpio_grp; 168 + void __iomem *reg_base; 165 169 }; 170 + 171 + static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) 172 + { 173 + return __raw_readl(group->reg_base + offset); 174 + } 175 + 176 + static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) 177 + { 178 + __raw_writel(val, group->reg_base + offset); 179 + } 166 180 167 181 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 168 182 unsigned pin, int input) 169 183 { 170 184 if (input) 171 - __raw_writel(GPIO012_PIN_TO_BIT(pin), 185 + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), 172 186 group->gpio_grp->dir_clr); 173 187 else 174 - __raw_writel(GPIO012_PIN_TO_BIT(pin), 188 + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), 175 189 group->gpio_grp->dir_set); 176 190 } 177 191 ··· 192 184 u32 u = GPIO3_PIN_TO_BIT(pin); 193 185 194 186 if (input) 195 - __raw_writel(u, group->gpio_grp->dir_clr); 187 + gpreg_write(group, u, group->gpio_grp->dir_clr); 196 188 else 197 - __raw_writel(u, group->gpio_grp->dir_set); 189 + gpreg_write(group, u, group->gpio_grp->dir_set); 198 190 } 199 191 200 192 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 201 193 unsigned pin, int high) 202 194 { 203 195 if (high) 204 - __raw_writel(GPIO012_PIN_TO_BIT(pin), 196 + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), 205 197 group->gpio_grp->outp_set); 206 198 else 207 - __raw_writel(GPIO012_PIN_TO_BIT(pin), 199 + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), 208 200 group->gpio_grp->outp_clr); 209 201 } 210 202 ··· 214 206 u32 u = GPIO3_PIN_TO_BIT(pin); 215 207 216 208 if (high) 217 - __raw_writel(u, group->gpio_grp->outp_set); 209 + gpreg_write(group, u, group->gpio_grp->outp_set); 218 210 else 219 - __raw_writel(u, group->gpio_grp->outp_clr); 211 + gpreg_write(group, u, group->gpio_grp->outp_clr); 220 212 } 221 213 222 214 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 223 215 unsigned pin, int high) 224 216 { 225 217 if (high) 226 - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 218 + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 227 219 else 228 - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 220 + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 229 221 } 230 222 231 223 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 232 224 unsigned pin) 233 225 { 234 - return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 226 + return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), 235 227 pin); 236 228 } 237 229 238 230 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 239 231 unsigned pin) 240 232 { 241 - int state = __raw_readl(group->gpio_grp->inp_state); 233 + int state = gpreg_read(group, group->gpio_grp->inp_state); 242 234 243 235 /* 244 236 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped ··· 250 242 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 251 243 unsigned pin) 252 244 { 253 - return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 245 + return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin); 254 246 } 255 247 256 248 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 257 249 unsigned pin) 258 250 { 259 - return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 251 + return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin); 260 252 } 261 253 262 254 /* ··· 505 497 static int lpc32xx_gpio_probe(struct platform_device *pdev) 506 498 { 507 499 int i; 500 + void __iomem *reg_base; 501 + 502 + reg_base = devm_platform_ioremap_resource(pdev, 0); 503 + if (IS_ERR(reg_base)) 504 + return PTR_ERR(reg_base); 508 505 509 506 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { 510 507 if (pdev->dev.of_node) { 511 508 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; 512 509 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; 513 510 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; 511 + lpc32xx_gpiochip[i].reg_base = reg_base; 514 512 } 515 513 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, 516 514 &lpc32xx_gpiochip[i]); ··· 541 527 }; 542 528 543 529 module_platform_driver(lpc32xx_gpio_driver); 530 + 531 + MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 532 + MODULE_LICENSE("GPL"); 533 + MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
+1 -1
drivers/net/ethernet/nxp/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 config LPC_ENET 3 3 tristate "NXP ethernet MAC on LPC devices" 4 - depends on ARCH_LPC32XX 4 + depends on ARCH_LPC32XX || COMPILE_TEST 5 5 select PHYLIB 6 6 help 7 7 Say Y or M here if you want to use the NXP ethernet MAC included on
+18 -27
drivers/net/ethernet/nxp/lpc_eth.c
··· 14 14 #include <linux/crc32.h> 15 15 #include <linux/etherdevice.h> 16 16 #include <linux/module.h> 17 + #include <linux/of.h> 17 18 #include <linux/of_net.h> 18 19 #include <linux/phy.h> 19 20 #include <linux/platform_device.h> 20 21 #include <linux/spinlock.h> 21 - 22 - #include <mach/board.h> 23 - #include <mach/hardware.h> 24 - #include <mach/platform.h> 22 + #include <linux/soc/nxp/lpc32xx-misc.h> 25 23 26 24 #define MODNAME "lpc-eth" 27 25 #define DRV_VERSION "1.00" ··· 1235 1237 dma_addr_t dma_handle; 1236 1238 struct resource *res; 1237 1239 int irq, ret; 1238 - u32 tmp; 1239 1240 1240 1241 /* Setup network interface for RMII or MII mode */ 1241 - tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); 1242 - tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; 1243 - if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII) 1244 - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; 1245 - else 1246 - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; 1247 - __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); 1242 + lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev)); 1248 1243 1249 1244 /* Get platform resources */ 1250 1245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ··· 1302 1311 /* Get size of DMA buffers/descriptors region */ 1303 1312 pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE + 1304 1313 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); 1305 - pldat->dma_buff_base_v = 0; 1306 1314 1307 1315 if (use_iram_for_net(dev)) { 1308 - dma_handle = LPC32XX_IRAM_BASE; 1309 - if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) 1310 - pldat->dma_buff_base_v = 1311 - io_p2v(LPC32XX_IRAM_BASE); 1312 - else 1316 + if (pldat->dma_buff_size > 1317 + lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) { 1318 + pldat->dma_buff_base_v = NULL; 1319 + pldat->dma_buff_size = 0; 1313 1320 netdev_err(ndev, 1314 1321 "IRAM not big enough for net buffers, using SDRAM instead.\n"); 1322 + } 1315 1323 } 1316 1324 1317 - if (pldat->dma_buff_base_v == 0) { 1325 + if (pldat->dma_buff_base_v == NULL) { 1318 1326 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1319 1327 if (ret) 1320 1328 goto err_out_free_irq; ··· 1334 1344 pldat->dma_buff_base_p = dma_handle; 1335 1345 1336 1346 netdev_dbg(ndev, "IO address space :%pR\n", res); 1337 - netdev_dbg(ndev, "IO address size :%d\n", resource_size(res)); 1347 + netdev_dbg(ndev, "IO address size :%zd\n", 1348 + (size_t)resource_size(res)); 1338 1349 netdev_dbg(ndev, "IO address (mapped) :0x%p\n", 1339 1350 pldat->net_base); 1340 1351 netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq); 1341 - netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size); 1342 - netdev_dbg(ndev, "DMA buffer P address :0x%08x\n", 1343 - pldat->dma_buff_base_p); 1352 + netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size); 1353 + netdev_dbg(ndev, "DMA buffer P address :%pad\n", 1354 + &pldat->dma_buff_base_p); 1344 1355 netdev_dbg(ndev, "DMA buffer V address :0x%p\n", 1345 1356 pldat->dma_buff_base_v); 1346 1357 ··· 1388 1397 if (ret) 1389 1398 goto err_out_unregister_netdev; 1390 1399 1391 - netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", 1392 - res->start, ndev->irq); 1400 + netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n", 1401 + (unsigned long)res->start, ndev->irq); 1393 1402 1394 1403 device_init_wakeup(dev, 1); 1395 1404 device_set_wakeup_enable(dev, 0); ··· 1400 1409 unregister_netdev(ndev); 1401 1410 err_out_dma_unmap: 1402 1411 if (!use_iram_for_net(dev) || 1403 - pldat->dma_buff_size > lpc32xx_return_iram_size()) 1412 + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) 1404 1413 dma_free_coherent(dev, pldat->dma_buff_size, 1405 1414 pldat->dma_buff_base_v, 1406 1415 pldat->dma_buff_base_p); ··· 1427 1436 unregister_netdev(ndev); 1428 1437 1429 1438 if (!use_iram_for_net(&pldat->pdev->dev) || 1430 - pldat->dma_buff_size > lpc32xx_return_iram_size()) 1439 + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) 1431 1440 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, 1432 1441 pldat->dma_buff_base_v, 1433 1442 pldat->dma_buff_base_p);
+2 -1
drivers/tty/serial/Kconfig
··· 739 739 740 740 config SERIAL_HS_LPC32XX 741 741 tristate "LPC32XX high speed serial port support" 742 - depends on ARCH_LPC32XX && OF 742 + depends on ARCH_LPC32XX || COMPILE_TEST 743 + depends on OF 743 744 select SERIAL_CORE 744 745 help 745 746 Support for the LPC32XX high speed serial ports (up to 900kbps).
+4 -33
drivers/tty/serial/lpc32xx_hs.c
··· 25 25 #include <linux/irq.h> 26 26 #include <linux/gpio.h> 27 27 #include <linux/of.h> 28 - #include <mach/platform.h> 29 - #include <mach/hardware.h> 28 + #include <linux/sizes.h> 29 + #include <linux/soc/nxp/lpc32xx-misc.h> 30 30 31 31 /* 32 32 * High Speed UART register offsets ··· 80 80 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 81 81 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 82 82 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 83 + 84 + #define LPC32XX_MAIN_OSC_FREQ 13000000 83 85 84 86 #define MODNAME "lpc32xx_hsuart" 85 87 ··· 152 150 spin_unlock(&up->port.lock); 153 151 local_irq_restore(flags); 154 152 } 155 - 156 - static void lpc32xx_loopback_set(resource_size_t mapbase, int state); 157 153 158 154 static int __init lpc32xx_hsuart_console_setup(struct console *co, 159 155 char *options) ··· 437 437 tmp &= ~LPC32XX_HSU_BREAK; 438 438 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 439 439 spin_unlock_irqrestore(&port->lock, flags); 440 - } 441 - 442 - /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ 443 - static void lpc32xx_loopback_set(resource_size_t mapbase, int state) 444 - { 445 - int bit; 446 - u32 tmp; 447 - 448 - switch (mapbase) { 449 - case LPC32XX_HS_UART1_BASE: 450 - bit = 0; 451 - break; 452 - case LPC32XX_HS_UART2_BASE: 453 - bit = 1; 454 - break; 455 - case LPC32XX_HS_UART7_BASE: 456 - bit = 6; 457 - break; 458 - default: 459 - WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); 460 - return; 461 - } 462 - 463 - tmp = readl(LPC32XX_UARTCTL_CLOOP); 464 - if (state) 465 - tmp |= (1 << bit); 466 - else 467 - tmp &= ~(1 << bit); 468 - writel(tmp, LPC32XX_UARTCTL_CLOOP); 469 440 } 470 441 471 442 /* port->lock is not held. */
+2 -1
drivers/usb/gadget/udc/Kconfig
··· 45 45 46 46 config USB_LPC32XX 47 47 tristate "LPC32XX USB Peripheral Controller" 48 - depends on ARCH_LPC32XX && I2C 48 + depends on ARCH_LPC32XX || COMPILE_TEST 49 + depends on I2C 49 50 select USB_ISP1301 50 51 help 51 52 This option selects the USB device controller in the LPC32xx SoC.
+1 -2
drivers/usb/gadget/udc/lpc32xx_udc.c
··· 24 24 #include <linux/module.h> 25 25 #include <linux/of.h> 26 26 #include <linux/platform_device.h> 27 + #include <linux/prefetch.h> 27 28 #include <linux/proc_fs.h> 28 29 #include <linux/slab.h> 29 30 #include <linux/usb/ch9.h> ··· 35 34 #include <linux/debugfs.h> 36 35 #include <linux/seq_file.h> 37 36 #endif 38 - 39 - #include <mach/hardware.h> 40 37 41 38 /* 42 39 * USB device configuration structure
+2 -1
drivers/usb/host/Kconfig
··· 441 441 442 442 config USB_OHCI_HCD_LPC32XX 443 443 tristate "Support for LPC on-chip OHCI USB controller" 444 - depends on USB_OHCI_HCD && ARCH_LPC32XX 444 + depends on USB_OHCI_HCD 445 + depends on ARCH_LPC32XX || COMPILE_TEST 445 446 depends on USB_ISP1301 446 447 default y 447 448 ---help---
+18 -7
drivers/usb/host/ohci-nxp.c
··· 29 29 30 30 #include "ohci.h" 31 31 32 - #include <mach/hardware.h> 33 - 34 32 #define USB_CONFIG_BASE 0x31020000 35 - #define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110) 36 33 37 34 /* USB_OTG_STAT_CONTROL bit defines */ 38 35 #define TRANSPARENT_I2C_EN (1 << 7) ··· 119 122 120 123 static void ohci_nxp_start_hc(void) 121 124 { 122 - unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; 125 + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); 126 + unsigned long tmp; 123 127 124 - __raw_writel(tmp, USB_OTG_STAT_CONTROL); 128 + if (WARN_ON(!usb_otg_stat_control)) 129 + return; 130 + 131 + tmp = __raw_readl(usb_otg_stat_control) | HOST_EN; 132 + 133 + __raw_writel(tmp, usb_otg_stat_control); 125 134 isp1301_vbus_on(); 135 + 136 + iounmap(usb_otg_stat_control); 126 137 } 127 138 128 139 static void ohci_nxp_stop_hc(void) 129 140 { 141 + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); 130 142 unsigned long tmp; 131 143 144 + if (WARN_ON(!usb_otg_stat_control)) 145 + return; 146 + 132 147 isp1301_vbus_off(); 133 - tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; 134 - __raw_writel(tmp, USB_OTG_STAT_CONTROL); 148 + tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN; 149 + __raw_writel(tmp, usb_otg_stat_control); 150 + 151 + iounmap(usb_otg_stat_control); 135 152 } 136 153 137 154 static int ohci_hcd_nxp_probe(struct platform_device *pdev)
+1 -1
drivers/watchdog/Kconfig
··· 551 551 552 552 config PNX4008_WATCHDOG 553 553 tristate "LPC32XX Watchdog" 554 - depends on ARCH_LPC32XX 554 + depends on ARCH_LPC32XX || COMPILE_TEST 555 555 select WATCHDOG_CORE 556 556 help 557 557 Say Y here if to include support for the watchdog timer
-1
drivers/watchdog/pnx4008_wdt.c
··· 30 30 #include <linux/of.h> 31 31 #include <linux/delay.h> 32 32 #include <linux/reboot.h> 33 - #include <mach/hardware.h> 34 33 35 34 /* WatchDog Timer - Chapter 23 Page 207 */ 36 35
+33
include/linux/soc/nxp/lpc32xx-misc.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Author: Kevin Wells <kevin.wells@nxp.com> 4 + * 5 + * Copyright (C) 2010 NXP Semiconductors 6 + */ 7 + 8 + #ifndef __SOC_LPC32XX_MISC_H 9 + #define __SOC_LPC32XX_MISC_H 10 + 11 + #include <linux/types.h> 12 + #include <linux/phy.h> 13 + 14 + #ifdef CONFIG_ARCH_LPC32XX 15 + extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); 16 + extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode); 17 + extern void lpc32xx_loopback_set(resource_size_t mapbase, int state); 18 + #else 19 + static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) 20 + { 21 + *mapbase = NULL; 22 + *dmaaddr = 0; 23 + return 0; 24 + } 25 + static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode) 26 + { 27 + } 28 + static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state) 29 + { 30 + } 31 + #endif 32 + 33 + #endif /* __SOC_LPC32XX_MISC_H */