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MIPS: Create a common <asm/mach-generic/war.h>

11 platforms require at least one of these workarounds to be enabled; 22
platforms do not. In the latter case we can fall back to a generic version.

Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9567/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Kevin Cernekee and committed by
Ralf Baechle d631fc60 a47eb351

+3 -509
-24
arch/mips/include/asm/mach-ar7/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_AR7_WAR_H 9 - #define __ASM_MIPS_MACH_AR7_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_AR7_WAR_H */
-25
arch/mips/include/asm/mach-ath25/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org> 7 - */ 8 - #ifndef __ASM_MACH_ATH25_WAR_H 9 - #define __ASM_MACH_ATH25_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define RM9000_CDEX_SMP_WAR 0 21 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 22 - #define R10000_LLSC_WAR 0 23 - #define MIPS34K_MISSED_ITLB_WAR 0 24 - 25 - #endif /* __ASM_MACH_ATH25_WAR_H */
-24
arch/mips/include/asm/mach-ath79/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MACH_ATH79_WAR_H 9 - #define __ASM_MACH_ATH79_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MACH_ATH79_WAR_H */
-24
arch/mips/include/asm/mach-au1x00/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_AU1X00_WAR_H 9 - #define __ASM_MIPS_MACH_AU1X00_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
-24
arch/mips/include/asm/mach-bcm3384/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_BCM3384_WAR_H 9 - #define __ASM_MIPS_MACH_BCM3384_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_BCM3384_WAR_H */
-24
arch/mips/include/asm/mach-bcm47xx/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_BCM47XX_WAR_H 9 - #define __ASM_MIPS_MACH_BCM47XX_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_BCM47XX_WAR_H */
+3 -3
arch/mips/include/asm/mach-bcm63xx/war.h arch/mips/include/asm/mach-generic/war.h
··· 5 5 * 6 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 7 */ 8 - #ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H 9 - #define __ASM_MIPS_MACH_BCM63XX_WAR_H 8 + #ifndef __ASM_MACH_GENERIC_WAR_H 9 + #define __ASM_MACH_GENERIC_WAR_H 10 10 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 ··· 21 21 #define R10000_LLSC_WAR 0 22 22 #define MIPS34K_MISSED_ITLB_WAR 0 23 23 24 - #endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */ 24 + #endif /* __ASM_MACH_GENERIC_WAR_H */
-24
arch/mips/include/asm/mach-cobalt/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_COBALT_WAR_H 9 - #define __ASM_MIPS_MACH_COBALT_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
-24
arch/mips/include/asm/mach-dec/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_DEC_WAR_H 9 - #define __ASM_MIPS_MACH_DEC_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_DEC_WAR_H */
-24
arch/mips/include/asm/mach-emma2rh/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H 9 - #define __ASM_MIPS_MACH_EMMA2RH_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
-24
arch/mips/include/asm/mach-jazz/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_JAZZ_WAR_H 9 - #define __ASM_MIPS_MACH_JAZZ_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
-24
arch/mips/include/asm/mach-jz4740/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_JZ4740_WAR_H 9 - #define __ASM_MIPS_MACH_JZ4740_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
-23
arch/mips/include/asm/mach-lantiq/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - */ 7 - #ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H 8 - #define __ASM_MIPS_MACH_LANTIQ_WAR_H 9 - 10 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 11 - #define R4600_V1_HIT_CACHEOP_WAR 0 12 - #define R4600_V2_HIT_CACHEOP_WAR 0 13 - #define R5432_CP0_INTERRUPT_WAR 0 14 - #define BCM1250_M3_WAR 0 15 - #define SIBYTE_1956_WAR 0 16 - #define MIPS4K_ICACHE_REFILL_WAR 0 17 - #define MIPS_CACHE_SYNC_WAR 0 18 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 19 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 20 - #define R10000_LLSC_WAR 0 21 - #define MIPS34K_MISSED_ITLB_WAR 0 22 - 23 - #endif
-24
arch/mips/include/asm/mach-lasat/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_LASAT_WAR_H 9 - #define __ASM_MIPS_MACH_LASAT_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
-24
arch/mips/include/asm/mach-loongson/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MACH_LOONGSON_WAR_H 9 - #define __ASM_MACH_LOONGSON_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MACH_LEMOTE_WAR_H */
-24
arch/mips/include/asm/mach-loongson1/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MACH_LOONGSON1_WAR_H 9 - #define __ASM_MACH_LOONGSON1_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MACH_LOONGSON1_WAR_H */
-25
arch/mips/include/asm/mach-netlogic/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2011 Netlogic Microsystems. 7 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 8 - */ 9 - #ifndef __ASM_MIPS_MACH_NLM_WAR_H 10 - #define __ASM_MIPS_MACH_NLM_WAR_H 11 - 12 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 13 - #define R4600_V1_HIT_CACHEOP_WAR 0 14 - #define R4600_V2_HIT_CACHEOP_WAR 0 15 - #define R5432_CP0_INTERRUPT_WAR 0 16 - #define BCM1250_M3_WAR 0 17 - #define SIBYTE_1956_WAR 0 18 - #define MIPS4K_ICACHE_REFILL_WAR 0 19 - #define MIPS_CACHE_SYNC_WAR 0 20 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 21 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 22 - #define R10000_LLSC_WAR 0 23 - #define MIPS34K_MISSED_ITLB_WAR 0 24 - 25 - #endif /* __ASM_MIPS_MACH_NLM_WAR_H */
-25
arch/mips/include/asm/mach-paravirt/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - * Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com> 8 - */ 9 - #ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H 10 - #define __ASM_MIPS_MACH_PARAVIRT_WAR_H 11 - 12 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 13 - #define R4600_V1_HIT_CACHEOP_WAR 0 14 - #define R4600_V2_HIT_CACHEOP_WAR 0 15 - #define R5432_CP0_INTERRUPT_WAR 0 16 - #define BCM1250_M3_WAR 0 17 - #define SIBYTE_1956_WAR 0 18 - #define MIPS4K_ICACHE_REFILL_WAR 0 19 - #define MIPS_CACHE_SYNC_WAR 0 20 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 21 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 22 - #define R10000_LLSC_WAR 0 23 - #define MIPS34K_MISSED_ITLB_WAR 0 24 - 25 - #endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */
-24
arch/mips/include/asm/mach-pnx833x/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_PNX833X_WAR_H 9 - #define __ASM_MIPS_MACH_PNX833X_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */
-24
arch/mips/include/asm/mach-ralink/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MACH_RALINK_WAR_H 9 - #define __ASM_MACH_RALINK_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MACH_RALINK_WAR_H */
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arch/mips/include/asm/mach-tx39xx/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_TX39XX_WAR_H 9 - #define __ASM_MIPS_MACH_TX39XX_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
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arch/mips/include/asm/mach-vr41xx/war.h
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_VR41XX_WAR_H 9 - #define __ASM_MIPS_MACH_VR41XX_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 0 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */