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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
ARM: tegra: colibri: Properly align pin names
Align pin names on subsequent lines with the first the name of the first
pin in the first line.
Signed-off-by: Thierry Reding <treding@nvidia.com>
+36
-36
+36
-36
arch/arm/boot/dts/tegra30-colibri.dtsi
+36
-36
arch/arm/boot/dts/tegra30-colibri.dtsi
···
39
39
40
40
/* Colibri Backlight PWM<A> */
41
41
sdmmc3_dat3_pb4 {
42
-
nvidia,pins = "sdmmc3_dat3_pb4";
42
+
nvidia,pins = "sdmmc3_dat3_pb4";
43
43
nvidia,function = "pwm0";
44
44
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45
45
nvidia,tristate = <TEGRA_PIN_DISABLE>;
···
74
74
nvidia,tristate = <TEGRA_PIN_DISABLE>;
75
75
};
76
76
kb_row11_ps3 {
77
-
nvidia,pins = "kb_row11_ps3",
78
-
"kb_row12_ps4",
79
-
"kb_row13_ps5",
80
-
"kb_row14_ps6",
81
-
"kb_row15_ps7";
77
+
nvidia,pins = "kb_row11_ps3",
78
+
"kb_row12_ps4",
79
+
"kb_row13_ps5",
80
+
"kb_row14_ps6",
81
+
"kb_row15_ps7";
82
82
nvidia,function = "sdmmc2";
83
83
nvidia,pull = <TEGRA_PIN_PULL_UP>;
84
84
nvidia,tristate = <TEGRA_PIN_DISABLE>;
···
86
86
87
87
/* Colibri SSP */
88
88
ulpi_clk_py0 {
89
-
nvidia,pins = "ulpi_clk_py0",
90
-
"ulpi_dir_py1",
91
-
"ulpi_nxt_py2",
92
-
"ulpi_stp_py3";
89
+
nvidia,pins = "ulpi_clk_py0",
90
+
"ulpi_dir_py1",
91
+
"ulpi_nxt_py2",
92
+
"ulpi_stp_py3";
93
93
nvidia,function = "spi1";
94
94
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95
95
nvidia,tristate = <TEGRA_PIN_DISABLE>;
96
96
};
97
97
sdmmc3_dat6_pd3 {
98
-
nvidia,pins = "sdmmc3_dat6_pd3",
99
-
"sdmmc3_dat7_pd4";
98
+
nvidia,pins = "sdmmc3_dat6_pd3",
99
+
"sdmmc3_dat7_pd4";
100
100
nvidia,function = "spdif";
101
101
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102
102
nvidia,tristate = <TEGRA_PIN_ENABLE>;
···
104
104
105
105
/* Colibri UART_A */
106
106
ulpi_data0 {
107
-
nvidia,pins = "ulpi_data0_po1",
108
-
"ulpi_data1_po2",
109
-
"ulpi_data2_po3",
110
-
"ulpi_data3_po4",
111
-
"ulpi_data4_po5",
112
-
"ulpi_data5_po6",
113
-
"ulpi_data6_po7",
114
-
"ulpi_data7_po0";
107
+
nvidia,pins = "ulpi_data0_po1",
108
+
"ulpi_data1_po2",
109
+
"ulpi_data2_po3",
110
+
"ulpi_data3_po4",
111
+
"ulpi_data4_po5",
112
+
"ulpi_data5_po6",
113
+
"ulpi_data6_po7",
114
+
"ulpi_data7_po0";
115
115
nvidia,function = "uarta";
116
116
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117
117
nvidia,tristate = <TEGRA_PIN_DISABLE>;
···
119
119
120
120
/* Colibri UART_B */
121
121
gmi_a16_pj7 {
122
-
nvidia,pins = "gmi_a16_pj7",
123
-
"gmi_a17_pb0",
124
-
"gmi_a18_pb1",
125
-
"gmi_a19_pk7";
122
+
nvidia,pins = "gmi_a16_pj7",
123
+
"gmi_a17_pb0",
124
+
"gmi_a18_pb1",
125
+
"gmi_a19_pk7";
126
126
nvidia,function = "uartd";
127
127
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
128
128
nvidia,tristate = <TEGRA_PIN_DISABLE>;
···
130
130
131
131
/* Colibri UART_C */
132
132
uart2_rxd {
133
-
nvidia,pins = "uart2_rxd_pc3",
134
-
"uart2_txd_pc2";
133
+
nvidia,pins = "uart2_rxd_pc3",
134
+
"uart2_txd_pc2";
135
135
nvidia,function = "uartb";
136
136
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137
137
nvidia,tristate = <TEGRA_PIN_DISABLE>;
···
139
139
140
140
/* eMMC */
141
141
sdmmc4_clk_pcc4 {
142
-
nvidia,pins = "sdmmc4_clk_pcc4",
143
-
"sdmmc4_rst_n_pcc3";
142
+
nvidia,pins = "sdmmc4_clk_pcc4",
143
+
"sdmmc4_rst_n_pcc3";
144
144
nvidia,function = "sdmmc4";
145
145
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146
146
nvidia,tristate = <TEGRA_PIN_DISABLE>;
147
147
};
148
148
sdmmc4_dat0_paa0 {
149
-
nvidia,pins = "sdmmc4_dat0_paa0",
150
-
"sdmmc4_dat1_paa1",
151
-
"sdmmc4_dat2_paa2",
152
-
"sdmmc4_dat3_paa3",
153
-
"sdmmc4_dat4_paa4",
154
-
"sdmmc4_dat5_paa5",
155
-
"sdmmc4_dat6_paa6",
156
-
"sdmmc4_dat7_paa7";
149
+
nvidia,pins = "sdmmc4_dat0_paa0",
150
+
"sdmmc4_dat1_paa1",
151
+
"sdmmc4_dat2_paa2",
152
+
"sdmmc4_dat3_paa3",
153
+
"sdmmc4_dat4_paa4",
154
+
"sdmmc4_dat5_paa5",
155
+
"sdmmc4_dat6_paa6",
156
+
"sdmmc4_dat7_paa7";
157
157
nvidia,function = "sdmmc4";
158
158
nvidia,pull = <TEGRA_PIN_PULL_UP>;
159
159
nvidia,tristate = <TEGRA_PIN_DISABLE>;