tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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dt-bindings: xilinx: Switch xilinx.com emails to amd.com

@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.

Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com

Michal Simek d5c421d2 45fe0dc4

+31 -31
+1 -1
Documentation/devicetree/bindings/arm/xilinx.yaml
··· 7 7 title: Xilinx Zynq Platforms 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 description: | 13 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
+1 -1
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
··· 7 7 title: Ceva AHCI SATA Controller 8 8 9 9 maintainers: 10 - - Piyush Mehta <piyush.mehta@xilinx.com> 10 + - Piyush Mehta <piyush.mehta@amd.com> 11 11 12 12 description: | 13 13 The Ceva SATA controller mostly conforms to the AHCI interface with some
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Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
··· 7 7 title: Xilinx clocking wizard 8 8 9 9 maintainers: 10 - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> 10 + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 11 11 12 12 description: 13 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
+1 -1
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
··· 7 7 title: Xilinx Versal clock controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 - Jolly Shah <jolly.shah@xilinx.com> 12 12 - Rajan Vaja <rajan.vaja@xilinx.com> 13 13
+2 -2
Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
··· 7 7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator 8 8 9 9 maintainers: 10 - - Kalyani Akula <kalyani.akula@xilinx.com> 11 - - Michal Simek <michal.simek@xilinx.com> 10 + - Kalyani Akula <kalyani.akula@amd.com> 11 + - Michal Simek <michal.simek@amd.com> 12 12 13 13 description: | 14 14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
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Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
··· 7 7 title: Xilinx firmware driver 8 8 9 9 maintainers: 10 - - Nava kishore Manne <nava.manne@xilinx.com> 10 + - Nava kishore Manne <nava.kishore.manne@amd.com> 11 11 12 12 description: The zynqmp-firmware node describes the interface to platform 13 13 firmware. ZynqMP has an interface to communicate with secure firmware.
+1 -1
Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
··· 7 7 title: Xilinx Zynq FPGA Manager 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
··· 7 7 title: Xilinx Versal FPGA driver. 8 8 9 9 maintainers: 10 - - Nava kishore Manne <nava.manne@xilinx.com> 10 + - Nava kishore Manne <nava.kishore.manne@amd.com> 11 11 12 12 description: | 13 13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
+1 -1
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
··· 7 7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager 8 8 9 9 maintainers: 10 - - Nava kishore Manne <navam@xilinx.com> 10 + - Nava kishore Manne <nava.kishore.manne@amd.com> 11 11 12 12 description: | 13 13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
+1 -1
Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
··· 7 7 title: Xilinx Zynq GPIO controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
··· 7 7 title: Xilinx AXI GPIO controller 8 8 9 9 maintainers: 10 - - Neeli Srinivas <srinivas.neeli@xilinx.com> 10 + - Neeli Srinivas <srinivas.neeli@amd.com> 11 11 12 12 description: 13 13 The AXI GPIO design provides a general purpose input/output interface
+1 -1
Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
··· 12 12 PS_MODE). Every pin can be configured as input/output. 13 13 14 14 maintainers: 15 - - Piyush Mehta <piyush.mehta@xilinx.com> 15 + - Piyush Mehta <piyush.mehta@amd.com> 16 16 17 17 properties: 18 18 compatible:
+1 -1
Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
··· 7 7 title: Cadence I2C controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 allOf: 13 13 - $ref: /schemas/i2c/i2c-controller.yaml#
+1 -1
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
··· 33 33 +------------------------------------------+ 34 34 35 35 maintainers: 36 - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> 36 + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 37 37 38 38 properties: 39 39 compatible:
+1 -1
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
··· 7 7 title: Xilinx MIPI CSI-2 Receiver Subsystem 8 8 9 9 maintainers: 10 - - Vishal Sagar <vishal.sagar@xilinx.com> 10 + - Vishal Sagar <vishal.sagar@amd.com> 11 11 12 12 description: | 13 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
+1 -1
Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
··· 9 9 maintainers: 10 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 11 - Manish Narani <manish.narani@xilinx.com> 12 - - Michal Simek <michal.simek@xilinx.com> 12 + - Michal Simek <michal.simek@amd.com> 13 13 14 14 description: | 15 15 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
+1 -1
Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
··· 9 9 maintainers: 10 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 11 - Manish Narani <manish.narani@xilinx.com> 12 - - Michal Simek <michal.simek@xilinx.com> 12 + - Michal Simek <michal.simek@amd.com> 13 13 14 14 description: 15 15 The Zynq DDR ECC controller has an optional ECC support in half-bus width
+1 -1
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
··· 7 7 title: CPM Host Controller device tree for Xilinx Versal SoCs 8 8 9 9 maintainers: 10 - - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> 10 + - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> 11 11 12 12 allOf: 13 13 - $ref: /schemas/pci/pci-bus.yaml#
+1 -1
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
··· 7 7 title: Xilinx Zynq Pinctrl 8 8 9 9 maintainers: 10 - - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> 10 + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> 11 11 12 12 description: | 13 13 Please refer to pinctrl-bindings.txt in this directory for details of the
+1 -1
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
··· 7 7 title: Xilinx ZynqMP Pinctrl 8 8 9 9 maintainers: 10 - - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> 10 + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> 11 11 - Rajan Vaja <rajan.vaja@xilinx.com> 12 12 13 13 description: |
+1 -1
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
··· 7 7 title: Xilinx Zynq MPSoC Power Management 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 description: | 13 13 The zynqmp-power node describes the power management configurations.
+1 -1
Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
··· 11 11 The RTC controller has separate IRQ lines for seconds and alarm. 12 12 13 13 maintainers: 14 - - Michal Simek <michal.simek@xilinx.com> 14 + - Michal Simek <michal.simek@amd.com> 15 15 16 16 allOf: 17 17 - $ref: rtc.yaml#
+1 -1
Documentation/devicetree/bindings/serial/cdns,uart.yaml
··· 7 7 title: Cadence UART Controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/spi/spi-cadence.yaml
··· 7 7 title: Cadence SPI controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 allOf: 13 13 - $ref: spi-controller.yaml#
+1 -1
Documentation/devicetree/bindings/spi/spi-xilinx.yaml
··· 7 7 title: Xilinx SPI controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 allOf: 13 13 - $ref: spi-controller.yaml#
+1 -1
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
··· 7 7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 allOf: 13 13 - $ref: spi-controller.yaml#
+1 -1
Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
··· 14 14 - $ref: spi-controller.yaml# 15 15 16 16 maintainers: 17 - - Michal Simek <michal.simek@xilinx.com> 17 + - Michal Simek <michal.simek@amd.com> 18 18 19 19 # Everything else is described in the common file 20 20 properties:
+1 -1
Documentation/devicetree/bindings/timer/cdns,ttc.yaml
··· 7 7 title: Cadence TTC - Triple Timer Counter 8 8 9 9 maintainers: 10 - - Michal Simek <michal.simek@xilinx.com> 10 + - Michal Simek <michal.simek@amd.com> 11 11 12 12 properties: 13 13 compatible:
+2 -2
Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
··· 7 7 title: Xilinx AXI/PLB softcore and window Watchdog Timer 8 8 9 9 maintainers: 10 - - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> 11 - - Srinivas Neeli <srinivas.neeli@xilinx.com> 10 + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 11 + - Srinivas Neeli <srinivas.neeli@amd.com> 12 12 13 13 description: 14 14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.