Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Use DCC meta pitch for MALL allocation requirements

[Description]
Calculations for determining DCC meta size should be pitch*height*bpp/256.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dillon Varone and committed by
Alex Deucher
d5bec403 359bcc90

+11 -6
+3 -3
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
··· 262 262 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 263 263 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 264 264 265 - /* For DCC: 266 - * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1) 265 + /*For DCC: 266 + * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1) 267 267 */ 268 268 if (pipe->plane_state->dcc.enable) 269 - num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel + 269 + num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel + 270 270 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 271 271 272 272 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
+8 -3
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
··· 121 121 */ 122 122 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * 123 123 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); 124 + 125 + /*For DCC: 126 + * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1) 127 + */ 128 + if (pipe->plane_state->dcc.enable) 129 + num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel + 130 + (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES); 131 + 124 132 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES; 125 133 // cache lines used is total bytes / cache_line size. Add +2 for worst case alignment 126 134 // (MALL is 64-byte aligned) 127 135 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2; 128 136 129 - /* For DCC divide by 256 */ 130 - if (pipe->plane_state->dcc.enable) 131 - cache_lines_per_plane = cache_lines_per_plane + (cache_lines_per_plane / 256) + 1; 132 137 cache_lines_used += cache_lines_per_plane; 133 138 } 134 139 }