tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/nvc0: implement support for copy engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+777
-2
+1
-1
drivers/gpu/drm/nouveau/Makefile
+1
-1
drivers/gpu/drm/nouveau/Makefile
···
20
20
nv40_graph.o nv50_graph.o nvc0_graph.o \
21
21
nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
22
22
nv84_crypt.o \
23
-
nva3_copy.o \
23
+
nva3_copy.o nvc0_copy.o \
24
24
nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
25
25
nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
26
26
nv50_cursor.o nv50_display.o \
+1
drivers/gpu/drm/nouveau/nouveau_drv.h
+1
drivers/gpu/drm/nouveau/nouveau_drv.h
+4
drivers/gpu/drm/nouveau/nouveau_state.c
+4
drivers/gpu/drm/nouveau/nouveau_state.c
+243
drivers/gpu/drm/nouveau/nvc0_copy.c
+243
drivers/gpu/drm/nouveau/nvc0_copy.c
···
1
+
/*
2
+
* Copyright 2011 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: Ben Skeggs
23
+
*/
24
+
25
+
#include <linux/firmware.h>
26
+
#include "drmP.h"
27
+
#include "nouveau_drv.h"
28
+
#include "nouveau_util.h"
29
+
#include "nouveau_vm.h"
30
+
#include "nouveau_ramht.h"
31
+
#include "nvc0_copy.fuc.h"
32
+
33
+
struct nvc0_copy_engine {
34
+
struct nouveau_exec_engine base;
35
+
u32 irq;
36
+
u32 pmc;
37
+
u32 fuc;
38
+
u32 ctx;
39
+
};
40
+
41
+
static int
42
+
nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
43
+
{
44
+
struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
45
+
struct drm_device *dev = chan->dev;
46
+
struct drm_nouveau_private *dev_priv = dev->dev_private;
47
+
struct nouveau_gpuobj *ramin = chan->ramin;
48
+
struct nouveau_gpuobj *ctx = NULL;
49
+
int ret;
50
+
51
+
ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
52
+
NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER |
53
+
NVOBJ_FLAG_ZERO_ALLOC, &ctx);
54
+
if (ret)
55
+
return ret;
56
+
57
+
nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));
58
+
nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));
59
+
dev_priv->engine.instmem.flush(dev);
60
+
61
+
chan->engctx[engine] = ctx;
62
+
return 0;
63
+
}
64
+
65
+
static int
66
+
nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
67
+
u32 handle, u16 class)
68
+
{
69
+
return 0;
70
+
}
71
+
72
+
static void
73
+
nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
74
+
{
75
+
struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
76
+
struct nouveau_gpuobj *ctx = chan->engctx[engine];
77
+
struct drm_device *dev = chan->dev;
78
+
u32 inst;
79
+
80
+
inst = (chan->ramin->vinst >> 12);
81
+
inst |= 0x40000000;
82
+
83
+
/* disable fifo access */
84
+
nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
85
+
/* mark channel as unloaded if it's currently active */
86
+
if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
87
+
nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
88
+
/* mark next channel as invalid if it's about to be loaded */
89
+
if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
90
+
nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
91
+
/* restore fifo access */
92
+
nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
93
+
94
+
nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
95
+
nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
96
+
nouveau_gpuobj_ref(NULL, &ctx);
97
+
98
+
chan->engctx[engine] = ctx;
99
+
}
100
+
101
+
static int
102
+
nvc0_copy_init(struct drm_device *dev, int engine)
103
+
{
104
+
struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
105
+
int i;
106
+
107
+
nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
108
+
nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
109
+
nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
110
+
111
+
nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
112
+
for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
113
+
nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
114
+
115
+
nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
116
+
for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
117
+
if ((i & 0x3f) == 0)
118
+
nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
119
+
nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
120
+
}
121
+
122
+
nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
123
+
nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
124
+
nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
125
+
nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
126
+
return 0;
127
+
}
128
+
129
+
static int
130
+
nvc0_copy_fini(struct drm_device *dev, int engine)
131
+
{
132
+
struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
133
+
134
+
nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
135
+
136
+
/* trigger fuc context unload */
137
+
nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
138
+
nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
139
+
nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
140
+
nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
141
+
142
+
nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
143
+
return 0;
144
+
}
145
+
146
+
static struct nouveau_enum nvc0_copy_isr_error_name[] = {
147
+
{ 0x0001, "ILLEGAL_MTHD" },
148
+
{ 0x0002, "INVALID_ENUM" },
149
+
{ 0x0003, "INVALID_BITFIELD" },
150
+
{}
151
+
};
152
+
153
+
static void
154
+
nvc0_copy_isr(struct drm_device *dev, int engine)
155
+
{
156
+
struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
157
+
u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
158
+
u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
159
+
u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
160
+
u32 chid = nvc0_graph_isr_chid(dev, inst);
161
+
u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
162
+
u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
163
+
u32 mthd = (addr & 0x07ff) << 2;
164
+
u32 subc = (addr & 0x3800) >> 11;
165
+
u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
166
+
167
+
if (stat & 0x00000040) {
168
+
NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
169
+
nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
170
+
printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
171
+
chid, inst, subc, mthd, data);
172
+
nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
173
+
stat &= ~0x00000040;
174
+
}
175
+
176
+
if (stat) {
177
+
NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
178
+
nv_wr32(dev, pcopy->fuc + 0x004, stat);
179
+
}
180
+
}
181
+
182
+
static void
183
+
nvc0_copy_isr_0(struct drm_device *dev)
184
+
{
185
+
nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
186
+
}
187
+
188
+
static void
189
+
nvc0_copy_isr_1(struct drm_device *dev)
190
+
{
191
+
nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
192
+
}
193
+
194
+
static void
195
+
nvc0_copy_destroy(struct drm_device *dev, int engine)
196
+
{
197
+
struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
198
+
199
+
nouveau_irq_unregister(dev, pcopy->irq);
200
+
201
+
if (engine == NVOBJ_ENGINE_COPY0)
202
+
NVOBJ_ENGINE_DEL(dev, COPY0);
203
+
else
204
+
NVOBJ_ENGINE_DEL(dev, COPY1);
205
+
kfree(pcopy);
206
+
}
207
+
208
+
int
209
+
nvc0_copy_create(struct drm_device *dev, int engine)
210
+
{
211
+
struct nvc0_copy_engine *pcopy;
212
+
213
+
pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
214
+
if (!pcopy)
215
+
return -ENOMEM;
216
+
217
+
pcopy->base.destroy = nvc0_copy_destroy;
218
+
pcopy->base.init = nvc0_copy_init;
219
+
pcopy->base.fini = nvc0_copy_fini;
220
+
pcopy->base.context_new = nvc0_copy_context_new;
221
+
pcopy->base.context_del = nvc0_copy_context_del;
222
+
pcopy->base.object_new = nvc0_copy_object_new;
223
+
224
+
if (engine == 0) {
225
+
pcopy->irq = 5;
226
+
pcopy->pmc = 0x00000040;
227
+
pcopy->fuc = 0x104000;
228
+
pcopy->ctx = 0x0230;
229
+
nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
230
+
NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
231
+
NVOBJ_CLASS(dev, 0x90b5, COPY0);
232
+
} else {
233
+
pcopy->irq = 6;
234
+
pcopy->pmc = 0x00000080;
235
+
pcopy->fuc = 0x105000;
236
+
pcopy->ctx = 0x0240;
237
+
nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
238
+
NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
239
+
NVOBJ_CLASS(dev, 0x90b8, COPY1);
240
+
}
241
+
242
+
return 0;
243
+
}
+527
drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
+527
drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
···
1
+
uint32_t nvc0_pcopy_data[] = {
2
+
0x00000000,
3
+
0x00000000,
4
+
0x00000000,
5
+
0x00000000,
6
+
0x00000000,
7
+
0x00000000,
8
+
0x00000000,
9
+
0x00000000,
10
+
0x00000000,
11
+
0x00000000,
12
+
0x00000000,
13
+
0x00000000,
14
+
0x00000000,
15
+
0x00000000,
16
+
0x00000000,
17
+
0x00000000,
18
+
0x00000000,
19
+
0x00000000,
20
+
0x00000000,
21
+
0x00000000,
22
+
0x00000000,
23
+
0x00000000,
24
+
0x00000000,
25
+
0x00000000,
26
+
0x00000000,
27
+
0x00000000,
28
+
0x00000000,
29
+
0x00000000,
30
+
0x00000000,
31
+
0x00000000,
32
+
0x00000000,
33
+
0x00000000,
34
+
0x00000000,
35
+
0x00000000,
36
+
0x00000000,
37
+
0x00000000,
38
+
0x00000000,
39
+
0x00000000,
40
+
0x00000000,
41
+
0x00000000,
42
+
0x00000000,
43
+
0x00000000,
44
+
0x00000000,
45
+
0x00000000,
46
+
0x00000000,
47
+
0x00000000,
48
+
0x00000000,
49
+
0x00000000,
50
+
0x00000000,
51
+
0x00000000,
52
+
0x00000000,
53
+
0x00000000,
54
+
0x00000000,
55
+
0x00000000,
56
+
0x00000000,
57
+
0x00000000,
58
+
0x00000000,
59
+
0x00000000,
60
+
0x00000000,
61
+
0x00000000,
62
+
0x00000000,
63
+
0x00000000,
64
+
0x00000000,
65
+
0x00000000,
66
+
0x00010000,
67
+
0x00000000,
68
+
0x00000000,
69
+
0x00010040,
70
+
0x0001019f,
71
+
0x00000000,
72
+
0x00010050,
73
+
0x000101a1,
74
+
0x00000000,
75
+
0x00070080,
76
+
0x0000001c,
77
+
0xfffff000,
78
+
0x00000020,
79
+
0xfff80000,
80
+
0x00000024,
81
+
0xffffe000,
82
+
0x00000028,
83
+
0xfffff800,
84
+
0x0000002c,
85
+
0xfffff000,
86
+
0x00000030,
87
+
0xfff80000,
88
+
0x00000034,
89
+
0xffffe000,
90
+
0x00070088,
91
+
0x00000048,
92
+
0xfffff000,
93
+
0x0000004c,
94
+
0xfff80000,
95
+
0x00000050,
96
+
0xffffe000,
97
+
0x00000054,
98
+
0xfffff800,
99
+
0x00000058,
100
+
0xfffff000,
101
+
0x0000005c,
102
+
0xfff80000,
103
+
0x00000060,
104
+
0xffffe000,
105
+
0x000200c0,
106
+
0x000104b8,
107
+
0x00000000,
108
+
0x00010541,
109
+
0x00000000,
110
+
0x000e00c3,
111
+
0x00000010,
112
+
0xffffff00,
113
+
0x00000014,
114
+
0x0000000f,
115
+
0x0000003c,
116
+
0xffffff00,
117
+
0x00000040,
118
+
0x0000000f,
119
+
0x00000018,
120
+
0xfff80000,
121
+
0x00000044,
122
+
0xfff80000,
123
+
0x00000074,
124
+
0xffff0000,
125
+
0x00000078,
126
+
0xffffe000,
127
+
0x00000068,
128
+
0xfccc0000,
129
+
0x0000006c,
130
+
0x00000000,
131
+
0x00000070,
132
+
0x00000000,
133
+
0x00000004,
134
+
0xffffff00,
135
+
0x00000008,
136
+
0x00000000,
137
+
0x0000000c,
138
+
0x00000000,
139
+
0x00000800,
140
+
};
141
+
142
+
uint32_t nvc0_pcopy_code[] = {
143
+
0x04fe04bd,
144
+
0x3517f000,
145
+
0xf10010fe,
146
+
0xf1040017,
147
+
0xf0fff327,
148
+
0x22d00023,
149
+
0x0c25f0c0,
150
+
0xf40012d0,
151
+
0x17f11031,
152
+
0x27f01200,
153
+
0x0012d003,
154
+
0xf40031f4,
155
+
0x0ef40028,
156
+
0x8001cffd,
157
+
0xf40812c4,
158
+
0x21f4060b,
159
+
0x0412c4ca,
160
+
0xf5070bf4,
161
+
0xc4010221,
162
+
0x01d00c11,
163
+
0xf101f840,
164
+
0xfe770047,
165
+
0x47f1004b,
166
+
0x44cf2100,
167
+
0x0144f000,
168
+
0xb60444b6,
169
+
0xf7f13040,
170
+
0xf4b6061c,
171
+
0x1457f106,
172
+
0x00f5d101,
173
+
0xb6043594,
174
+
0x57fe0250,
175
+
0x0145fe00,
176
+
0x010052b7,
177
+
0x00ff67f1,
178
+
0x56fd60bd,
179
+
0x0253f004,
180
+
0xf80545fa,
181
+
0x0053f003,
182
+
0xd100e7f0,
183
+
0x549800fe,
184
+
0x0845b600,
185
+
0xb6015698,
186
+
0x46fd1864,
187
+
0x0047fe05,
188
+
0xf00204b9,
189
+
0x01f40643,
190
+
0x0604fa09,
191
+
0xfa060ef4,
192
+
0x03f80504,
193
+
0x27f100f8,
194
+
0x23cf1400,
195
+
0x1e3fc800,
196
+
0xf4170bf4,
197
+
0x21f40132,
198
+
0x1e3af053,
199
+
0xf00023d0,
200
+
0x24d00147,
201
+
0xcf00f880,
202
+
0x3dc84023,
203
+
0x090bf41e,
204
+
0xf40131f4,
205
+
0x37f05321,
206
+
0x8023d002,
207
+
0x37f100f8,
208
+
0x32cf1900,
209
+
0x0033cf40,
210
+
0x07ff24e4,
211
+
0xf11024b6,
212
+
0xbd010057,
213
+
0x5874bd64,
214
+
0x57580056,
215
+
0x0450b601,
216
+
0xf40446b8,
217
+
0x76bb4d08,
218
+
0x0447b800,
219
+
0xbb0f08f4,
220
+
0x74b60276,
221
+
0x0057bb03,
222
+
0xbbdf0ef4,
223
+
0x44b60246,
224
+
0x0045bb03,
225
+
0xfd014598,
226
+
0x54b00453,
227
+
0x201bf400,
228
+
0x58004558,
229
+
0x64b00146,
230
+
0x091bf400,
231
+
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